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Searched refs:GENMASK (Results 1 – 25 of 1796) sorted by relevance

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/Linux-v6.1/include/soc/mscc/
Docelot_ana.h15 #define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14))
16 #define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
17 #define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14)
19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
20 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
24 #define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3))
25 #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
26 #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3)
28 #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0))
29 #define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0)
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Docelot_hsio.h90 #define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23))
91 #define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
92 #define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23)
93 #define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18))
94 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
95 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18)
96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
103 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6))
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Docelot_qsys.h25 #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8))
26 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
27 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8)
28 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0))
29 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0)
33 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8))
34 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8)
35 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8)
36 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0))
37 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0)
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Docelot_sys.h20 #define SYS_FRM_AGING_MAX_AGE(x) ((x) & GENMASK(19, 0))
21 #define SYS_FRM_AGING_MAX_AGE_M GENMASK(19, 0)
23 #define SYS_STAT_CFG_STAT_CLEAR_SHOT(x) (((x) << 10) & GENMASK(16, 10))
24 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_M GENMASK(16, 10)
25 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x) (((x) & GENMASK(16, 10)) >> 10)
26 #define SYS_STAT_CFG_STAT_VIEW(x) ((x) & GENMASK(9, 0))
27 #define SYS_STAT_CFG_STAT_VIEW_M GENMASK(9, 0)
40 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x) (((x) << 6) & GENMASK(21, 6))
41 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6)
42 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x) (((x) & GENMASK(21, 6)) >> 6)
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Docelot_dev.h17 #define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0))
18 #define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
27 #define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15))
28 #define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
29 #define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15)
30 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
31 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
32 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
33 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1))
34 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)
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/Linux-v6.1/drivers/net/wireless/mediatek/mt76/
Dmt76_connac2_mac.h35 #define MT_TXD0_Q_IDX GENMASK(31, 25)
36 #define MT_TXD0_PKT_FMT GENMASK(24, 23)
37 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
38 #define MT_TXD0_TX_BYTES GENMASK(15, 0)
42 #define MT_TXD1_OWN_MAC GENMASK(29, 24)
44 #define MT_TXD1_TID GENMASK(22, 20)
45 #define MT_TXD1_HDR_PAD GENMASK(19, 18)
46 #define MT_TXD1_HDR_FORMAT GENMASK(17, 16)
47 #define MT_TXD1_HDR_INFO GENMASK(15, 11)
50 #define MT_TXD1_WLAN_IDX GENMASK(9, 0)
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Dmt76x02_regs.h19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
20 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
21 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
22 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
23 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
54 #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */
55 #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */
56 #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */
68 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
71 #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)
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/Linux-v6.1/drivers/net/wireless/mediatek/mt76/mt7603/
Dmac.h6 #define MT_RXD0_LENGTH GENMASK(15, 0)
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
9 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
27 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
28 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
31 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
32 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
33 #define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)
57 #define MT_RXD2_NORMAL_SEC_MODE GENMASK(15, 12)
58 #define MT_RXD2_NORMAL_TID GENMASK(11, 8)
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Dregs.h14 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
15 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
18 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
19 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
29 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
30 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
44 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
47 #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)
56 #define MT_WPDMA_DEBUG_VALUE GENMASK(17, 0)
58 #define MT_WPDMA_DEBUG_IDX GENMASK(31, 28)
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/Linux-v6.1/drivers/net/wireless/mediatek/mt76/mt7615/
Dmac.h10 #define MT_RXD0_LENGTH GENMASK(15, 0)
11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
34 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
35 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
36 #define MT_RXD1_FIRST_AMSDU_FRAME GENMASK(1, 0)
41 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
42 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
43 #define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)
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Dregs.h43 #define MT_TOP_OFF_RSV_FW_STATE GENMASK(18, 16)
46 #define MT_TOP_MISC2_FW_STATE GENMASK(2, 0)
48 #define MT7663_TOP_MISC2_FW_STATE GENMASK(3, 1)
55 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
56 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
60 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
61 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
84 #define MT7663_MCU_PCIE_REMAP_2_OFFSET GENMASK(15, 0)
85 #define MT7663_MCU_PCIE_REMAP_2_BASE GENMASK(31, 16)
111 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
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/Linux-v6.1/drivers/net/wireless/realtek/rtw89/
Dreg.h12 #define B_AX_PWC_EV2EF_MASK GENMASK(15, 14)
46 #define B_AX_EF_PGPD_MASK GENMASK(30, 28)
48 #define B_AX_EF_VDDQST_MASK GENMASK(26, 24)
49 #define B_AX_EF_PGTS_MASK GENMASK(23, 20)
52 #define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8)
55 #define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30)
58 #define B_AX_EF_ADDR_MASK GENMASK(26, 16)
59 #define B_AX_EF_DATA_MASK GENMASK(15, 0)
64 #define B_AX_EF_TEST_SEL_MASK GENMASK(18, 16)
84 #define B_AX_BTMODE_MASK GENMASK(7, 6)
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Dtxrx.h10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7)
11 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0)
13 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0)
15 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4)
16 #define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0)
26 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24)
27 #define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24)
31 #define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16)
32 #define RTW89_TXWD_BODY0_HDR_LLC_LEN GENMASK(15, 11)
35 #define RTW89_TXWD_BODY0_HW_SSN_SEL GENMASK(3, 2)
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Dfw.h22 u32_get_bits(info, GENMASK(6, 0))
24 u32_get_bits(info, GENMASK(11, 8))
27 u32p_replace_bits(info, val, GENMASK(6, 0))
29 u32p_replace_bits(info, val, GENMASK(11, 8))
67 u32_get_bits(*((const u32 *)(info)), GENMASK(6, 0))
71 u32_get_bits(*((const u32 *)(info)), GENMASK(11, 8))
73 u32_get_bits(*((const u32 *)(info)), GENMASK(15, 12))
75 u32_get_bits(*((const u32 *)(info)), GENMASK(23, 16))
77 u32_get_bits(*((const u32 *)(info)), GENMASK(31, 24))
79 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(7, 0))
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/Linux-v6.1/drivers/gpu/drm/mediatek/
Dmtk_dp_reg.h17 #define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(20, 16)
19 #define RG_CKM_PT0_CKTX_IMPSEL GENMASK(23, 20)
38 #define RG_XTP_LN0_TX_IMPSEL_PMOS GENMASK(15, 12)
39 #define RG_XTP_LN0_TX_IMPSEL_NMOS GENMASK(19, 16)
41 #define RG_XTP_LN1_TX_IMPSEL_PMOS GENMASK(15, 12)
42 #define RG_XTP_LN1_TX_IMPSEL_NMOS GENMASK(19, 16)
44 #define RG_XTP_LN2_TX_IMPSEL_PMOS GENMASK(15, 12)
45 #define RG_XTP_LN2_TX_IMPSEL_NMOS GENMASK(19, 16)
47 #define RG_XTP_LN3_TX_IMPSEL_PMOS GENMASK(15, 12)
48 #define RG_XTP_LN3_TX_IMPSEL_NMOS GENMASK(19, 16)
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/Linux-v6.1/drivers/media/platform/ti/cal/
Dcal_regs.h91 #define CAL_HL_REVISION_MINOR_MASK GENMASK(5, 0)
92 #define CAL_HL_REVISION_CUSTOM_MASK GENMASK(7, 6)
93 #define CAL_HL_REVISION_MAJOR_MASK GENMASK(10, 8)
94 #define CAL_HL_REVISION_RTL_MASK GENMASK(15, 11)
95 #define CAL_HL_REVISION_FUNC_MASK GENMASK(27, 16)
96 #define CAL_HL_REVISION_SCHEME_MASK GENMASK(31, 30)
100 #define CAL_HL_HWINFO_WFIFO_MASK GENMASK(3, 0)
101 #define CAL_HL_HWINFO_RFIFO_MASK GENMASK(7, 4)
102 #define CAL_HL_HWINFO_PCTX_MASK GENMASK(12, 8)
103 #define CAL_HL_HWINFO_WCTX_MASK GENMASK(18, 13)
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/Linux-v6.1/drivers/net/can/ctucanfd/
Dctucanfd_kregs.h98 #define REG_DEVICE_ID_DEVICE_ID GENMASK(15, 0)
99 #define REG_DEVICE_ID_VER_MINOR GENMASK(23, 16)
100 #define REG_DEVICE_ID_VER_MAJOR GENMASK(31, 24)
115 #define REG_MODE_RTRTH GENMASK(20, 17)
159 #define REG_INT_ENA_SET_INT_ENA_SET GENMASK(11, 0)
162 #define REG_INT_ENA_CLR_INT_ENA_CLR GENMASK(11, 0)
165 #define REG_INT_MASK_SET_INT_MASK_SET GENMASK(11, 0)
168 #define REG_INT_MASK_CLR_INT_MASK_CLR GENMASK(11, 0)
171 #define REG_BTR_PROP GENMASK(6, 0)
172 #define REG_BTR_PH1 GENMASK(12, 7)
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/Linux-v6.1/drivers/net/ipa/
Dgsi_reg.h81 #define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0)
82 #define CHTYPE_DIR_FMASK GENMASK(3, 3)
83 #define EE_FMASK GENMASK(7, 4)
84 #define CHID_FMASK GENMASK(12, 8)
86 #define CHTYPE_PROTOCOL_MSB_FMASK GENMASK(13, 13)
87 #define ERINDEX_FMASK GENMASK(18, 14)
88 #define CHSTATE_FMASK GENMASK(23, 20)
89 #define ELEMENT_SIZE_FMASK GENMASK(31, 24)
115 return u32_encode_bits(length, GENMASK(15, 0)); in r_length_encoded()
116 return u32_encode_bits(length, GENMASK(19, 0)); in r_length_encoded()
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/Linux-v6.1/drivers/mtd/nand/raw/
Ddenali.h24 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
27 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
30 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
33 #define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
55 #define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)
67 #define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
68 #define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
72 #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
73 #define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
76 #define RE_2_WE__VALUE GENMASK(5, 0)
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/Linux-v6.1/drivers/net/ipa/reg/
Dipa_reg-v4.5.c28 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17),
74 [ROUTE_DEF_PIPE] = GENMASK(5, 1),
76 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
77 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
86 [MEM_SIZE] = GENMASK(15, 0),
87 [MEM_BADDR] = GENMASK(31, 16),
93 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
94 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
101 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
102 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
[all …]
Dipa_reg-v3.1.c46 [ROUTE_DEF_PIPE] = GENMASK(5, 1),
48 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
49 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
58 [MEM_SIZE] = GENMASK(15, 0),
59 [MEM_BADDR] = GENMASK(31, 16),
65 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
66 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
73 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
74 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
111 [IPA_BASE_ADDR] = GENMASK(16, 0),
[all …]
/Linux-v6.1/drivers/net/wireless/mediatek/mt7601u/
Dregs.h22 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
23 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
24 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
25 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
26 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
52 #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */
53 #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */
54 #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */
63 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
66 #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)
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/Linux-v6.1/drivers/net/wwan/t7xx/
Dt7xx_hif_dpmaif_rx.h25 #define NETIF_MASK GENMASK(4, 0)
48 #define PD_PIT_DATA_LEN GENMASK(31, 16)
49 #define PD_PIT_BUFFER_ID GENMASK(15, 3)
54 #define PD_PIT_DLQ_DONE GENMASK(31, 30)
55 #define PD_PIT_ULQ_DONE GENMASK(29, 24)
56 #define PD_PIT_HEADER_OFFSET GENMASK(23, 19)
57 #define PD_PIT_BI_F GENMASK(18, 17)
59 #define PD_PIT_RES GENMASK(15, 11)
60 #define PD_PIT_H_BID GENMASK(10, 8)
61 #define PD_PIT_PIT_SEQ GENMASK(7, 0)
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/Linux-v6.1/drivers/net/wireless/ath/ath11k/
Dhal_desc.h10 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)
12 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)
13 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8)
14 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11)
475 #define HAL_TLV_HDR_TAG GENMASK(9, 1)
476 #define HAL_TLV_HDR_LEN GENMASK(25, 10)
477 #define HAL_TLV_USR_ID GENMASK(31, 26)
486 #define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0)
487 #define RX_MPDU_DESC_INFO0_SEQ_NUM GENMASK(19, 8)
500 #define RX_MPDU_DESC_META_DATA_PEER_ID GENMASK(15, 0)
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/Linux-v6.1/drivers/net/wireless/realtek/rtw88/
Drtw8822c.h137 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
139 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
141 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(21, 16))
143 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
145 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(29, 24))
149 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
151 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
153 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
155 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
157 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
[all …]

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