Lines Matching refs:GENMASK

12 #define B_AX_PWC_EV2EF_MASK GENMASK(15, 14)
46 #define B_AX_EF_PGPD_MASK GENMASK(30, 28)
48 #define B_AX_EF_VDDQST_MASK GENMASK(26, 24)
49 #define B_AX_EF_PGTS_MASK GENMASK(23, 20)
52 #define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8)
55 #define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30)
58 #define B_AX_EF_ADDR_MASK GENMASK(26, 16)
59 #define B_AX_EF_DATA_MASK GENMASK(15, 0)
64 #define B_AX_EF_TEST_SEL_MASK GENMASK(18, 16)
84 #define B_AX_BTMODE_MASK GENMASK(7, 6)
92 #define B_AX_GPIOSEL_MASK GENMASK(1, 0)
95 #define B_AX_DBG_SEL1_4BIT GENMASK(31, 30)
97 #define B_AX_DBG_SEL1 GENMASK(23, 16)
98 #define B_AX_DBG_SEL0_4BIT GENMASK(15, 14)
100 #define B_AX_DBG_SEL0 GENMASK(7, 0)
119 #define B_AX_R_AX_BG GENMASK(1, 0)
131 #define B_MAC_AX_SB_FW_MASK GENMASK(30, 24)
132 #define B_MAC_AX_SB_DRV_MASK GENMASK(23, 0)
138 #define B_AX_DEBUG_ST_MASK GENMASK(31, 0)
144 #define B_AX_PCIE_MIO_ADDR_PAGE_V1_MASK GENMASK(20, 16)
147 #define B_AX_PCIE_MIO_WE_MASK GENMASK(11, 8)
149 #define B_AX_PCIE_MIO_ADDR_MASK GENMASK(7, 0)
150 #define MIO_ADDR_PAGE_MASK GENMASK(12, 8)
153 #define B_AX_PCIE_MIO_DATA_MASK GENMASK(31, 0)
156 #define B_AX_CHIP_VER_MASK GENMASK(15, 12)
159 #define B_AX_SEL_0XC0_MASK GENMASK(17, 16)
160 #define B_AX_PAD_HCI_SEL_V2_MASK GENMASK(5, 3)
174 #define B_AX_WCPU_FWDL_STS_MASK GENMASK(7, 5)
183 #define PS_RPWM_SEQ_NUM GENMASK(13, 12)
187 #define PS_CPWM_SEQ_NUM GENMASK(13, 12)
188 #define PS_CPWM_RSP_SEQ_NUM GENMASK(9, 8)
189 #define PS_CPWM_STATE GENMASK(2, 0)
193 #define B_AX_BOOT_REASON_MASK GENMASK(2, 0)
204 #define B_AX_VREFPFM_L_MASK GENMASK(25, 22)
205 #define B_AX_REG_ZCDC_H_MASK GENMASK(18, 17)
206 #define B_AX_OCP_L1_MASK GENMASK(15, 13)
207 #define B_AX_VOL_L1_MASK GENMASK(3, 0)
217 #define B_AX_WL_XTAL_SI_MODE_MASK GENMASK(25, 24)
220 #define B_AX_WL_XTAL_SI_BITMASK_MASK GENMASK(23, 16)
221 #define B_AX_WL_XTAL_SI_DATA_MASK GENMASK(15, 8)
222 #define B_AX_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
226 #define B_AX_XTAL_SC_XO_MASK GENMASK(23, 17)
227 #define B_AX_XTAL_SC_XI_MASK GENMASK(16, 10)
228 #define B_AX_XTAL_SC_MASK GENMASK(6, 0)
245 #define B_AX_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16)
246 #define B_AX_WLMAC_PWR_STE_MASK GENMASK(9, 8)
247 #define B_AX_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6)
248 #define B_AX_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4)
249 #define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
250 #define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
253 #define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24)
255 #define B_AX_S0_LDO_VSEL_F_MASK GENMASK(22, 21)
260 #define B_AX_WD_ITVL_IDLE_V1_MASK GENMASK(31, 28)
261 #define B_AX_WD_ITVL_ACT_V1_MASK GENMASK(27, 24)
262 #define B_AX_DMA_MODE_MASK GENMASK(19, 18)
271 #define B_AX_HAXI_MAX_RXDMA_MASK GENMASK(9, 8)
275 #define B_AX_HAXI_MAX_TXDMA_MASK GENMASK(1, 0)
307 #define B_AX_DBG_DUMMY_MASK GENMASK(23, 16)
308 #define B_AX_DBG_SEL_MASK GENMASK(15, 13)
328 #define B_AX_LTR_CURR_IDX_DRV_MASK GENMASK(15, 14)
330 #define B_AX_LTR_CURR_IDX_FW_MASK GENMASK(12, 11)
332 #define B_AX_LTR_CURR_IDX_HW_MASK GENMASK(9, 8)
334 #define B_AX_LTR_IDX_DRV_MASK GENMASK(6, 5)
339 #define B_AX_LTR_SPACE_IDX_V1_MASK GENMASK(1, 0)
484 #define B_AX_LTR_SPACE_IDX_MASK GENMASK(13, 12)
485 #define B_AX_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8)
494 #define B_AX_LTR_RX1_TH_MASK GENMASK(27, 16)
495 #define B_AX_LTR_RX0_TH_MASK GENMASK(11, 0)
502 #define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28)
538 #define DMAC_ERR_IMR_EN GENMASK(31, 0)
921 #define B_AX_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10)
922 #define B_AX_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8)
923 #define B_AX_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6)
924 #define B_AX_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4)
926 #define B_AX_HCI_FC_MODE_MASK GENMASK(2, 1)
930 #define B_AX_PREC_PAGE_CH12_MASK GENMASK(24, 16)
931 #define B_AX_PREC_PAGE_CH011_MASK GENMASK(8, 0)
933 #define B_AX_MAX_PG_MASK GENMASK(28, 16)
934 #define B_AX_MIN_PG_MASK GENMASK(12, 0)
949 #define B_AX_AVAL_PG_MASK GENMASK(27, 16)
950 #define B_AX_USE_PG_MASK GENMASK(12, 0)
966 #define B_AX_G1_AVAL_PG_MASK GENMASK(28, 16)
967 #define B_AX_G0_AVAL_PG_MASK GENMASK(12, 0)
970 #define B_AX_PUBPG_G1_MASK GENMASK(28, 16)
971 #define B_AX_PUBPG_G0_MASK GENMASK(12, 0)
974 #define B_AX_PUBPG_ALL_MASK GENMASK(12, 0)
977 #define B_AX_G1_USE_PG_MASK GENMASK(28, 16)
978 #define B_AX_G0_USE_PG_MASK GENMASK(12, 0)
981 #define B_AX_PUB_AVAL_PG_MASK GENMASK(12, 0)
984 #define B_AX_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16)
985 #define B_AX_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0)
988 #define B_AX_WP_THRD_MASK GENMASK(12, 0)
991 #define B_AX_WP_AVAL_PG_MASK GENMASK(28, 16)
994 #define B_AX_WDE_START_BOUND_MASK GENMASK(13, 8)
995 #define B_AX_WDE_PAGE_SEL_MASK GENMASK(1, 0)
996 #define B_AX_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
999 #define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
1155 #define B_AX_WDE_MAX_SIZE_MASK GENMASK(27, 16)
1156 #define B_AX_WDE_MIN_SIZE_MASK GENMASK(11, 0)
1163 #define B_AX_DLE_PUB_PGNUM GENMASK(12, 0)
1164 #define B_AX_DLE_FREE_HEADPG GENMASK(11, 0)
1165 #define B_AX_DLE_FREE_TAILPG GENMASK(27, 16)
1166 #define B_AX_DLE_USE_PGNUM GENMASK(27, 16)
1167 #define B_AX_DLE_RSV_PGNUM GENMASK(11, 0)
1168 #define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0)
1176 #define B_AX_WDE_DFI_TRGSEL_MASK GENMASK(19, 16)
1177 #define B_AX_WDE_DFI_ADDR_MASK GENMASK(15, 0)
1179 #define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0)
1182 #define B_AX_PLE_START_BOUND_MASK GENMASK(13, 8)
1183 #define B_AX_PLE_PAGE_SEL_MASK GENMASK(1, 0)
1184 #define B_AX_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
1307 #define B_AX_PLE_MAX_SIZE_MASK GENMASK(27, 16)
1308 #define B_AX_PLE_MIN_SIZE_MASK GENMASK(11, 0)
1316 #define B_AX_PLE_Q6_MAX_SIZE_MASK GENMASK(27, 16)
1317 #define B_AX_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0)
1330 #define B_AX_PLE_DFI_TRGSEL_MASK GENMASK(19, 16)
1331 #define B_AX_PLE_DFI_ADDR_MASK GENMASK(15, 0)
1333 #define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0)
1336 #define B_AX_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8)
1337 #define B_AX_WDRLS_MODE_MASK GENMASK(1, 0)
1340 #define B_AX_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24)
1341 #define B_AX_RLSRPT0_PKTTYPE_MASK GENMASK(19, 16)
1342 #define B_AX_RLSRPT0_PID_MASK GENMASK(10, 8)
1343 #define B_AX_RLSRPT0_QID_MASK GENMASK(5, 0)
1346 #define B_AX_RLSRPT0_TO_MASK GENMASK(23, 16)
1347 #define B_AX_RLSRPT0_AGGNUM_MASK GENMASK(7, 0)
1454 #define B_AX_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16)
1455 #define B_AX_WD_BUF_REQ_LEN_MASK GENMASK(15, 0)
1460 #define B_AX_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0)
1465 #define B_AX_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)
1466 #define B_AX_CPUQ_OP_MACID_MASK GENMASK(23, 16)
1467 #define B_AX_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
1471 #define B_AX_CPUQ_OP_SRC_PID_MASK GENMASK(24, 22)
1472 #define B_AX_CPUQ_OP_SRC_QID_MASK GENMASK(21, 16)
1473 #define B_AX_CPUQ_OP_DST_PID_MASK GENMASK(8, 6)
1474 #define B_AX_CPUQ_OP_DST_QID_MASK GENMASK(5, 0)
1478 #define B_AX_WD_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16)
1479 #define B_AX_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)
1484 #define B_AX_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0)
1542 #define B_AX_FWD_PPDU_STAT_MASK GENMASK(1, 0)
1580 #define B_AX_TX_TIMEOUT_SEL_MASK GENMASK(31, 30)
1600 #define B_AX_SS_REL_QUEUE_MASK GENMASK(29, 24)
1601 #define B_AX_SS_REL_PORT_MASK GENMASK(18, 16)
1602 #define B_AX_SS_DEST_QUEUE_MASK GENMASK(13, 8)
1604 #define B_AX_SS_DEST_PORT_MASK GENMASK(2, 0)
1608 #define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0)
1612 #define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0)
1616 #define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0)
1620 #define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0)
1672 #define B_AX_DFI_TRGSEL_MASK GENMASK(19, 16)
1673 #define B_AX_DFI_ADDR_MASK GENMASK(15, 0)
1675 #define B_AX_DFI_DATA_MASK GENMASK(31, 0)
1679 #define B_AX_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
1682 #define B_AX_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
1683 #define B_AX_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
1686 #define B_AX_B0_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
1688 #define B_AX_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
1728 #define B_AX_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
1730 #define B_AX_B1_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
1731 #define B_AX_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
1734 #define B_AX_B1_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
1735 #define B_AX_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
1805 #define B_AX_CMAC_ALLCKEN GENMASK(31, 0)
1816 #define B_AX_WMAC_RFMOD_MASK GENMASK(1, 0)
1837 #define B_AX_TXSC_80M_MASK GENMASK(11, 8)
1838 #define B_AX_TXSC_40M_MASK GENMASK(7, 4)
1839 #define B_AX_TXSC_20M_MASK GENMASK(3, 0)
1843 #define B_AX_RRSR_RATE_EN_MASK GENMASK(11, 8)
1845 #define B_AX_RSC_MASK GENMASK(7, 6)
1846 #define B_AX_RRSR_CCK_MASK GENMASK(3, 0)
1857 #define CMAC0_ERR_IMR_EN GENMASK(31, 0)
1858 #define CMAC1_ERR_IMR_EN GENMASK(31, 0)
1875 #define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0)
1880 #define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0)
1885 #define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0)
1890 #define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0)
1895 #define B_AX_PREBKF_TIME_MASK GENMASK(4, 0)
1899 #define B_AX_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(30, 24)
1900 #define B_AX_SIFS_PREBKF_MASK GENMASK(23, 16)
1901 #define B_AX_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8)
1902 #define B_AX_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)
1934 #define B_AX_CTN_TXEN_ALL_MASK GENMASK(15, 0)
1938 #define B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK GENMASK(31, 16)
1939 #define B_AX_MUEDCA_BE_PARAM_0_CW_MASK GENMASK(15, 8)
1940 #define B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK GENMASK(7, 0)
1985 #define B_AX_CTN_TXEN_ALL_MASK_V1 GENMASK(17, 0)
1997 #define B_AX_SCH_CFG_CMD_SEL GENMASK(15, 8)
1998 #define B_AX_SCH_DBG_SEL_MASK GENMASK(7, 0)
2002 #define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0)
2018 #define B_AX_NET_TYPE_MASK GENMASK(11, 10)
2035 #define B_AX_TBTT_HOLD_MASK GENMASK(27, 16)
2036 #define B_AX_TBTT_SETUP_MASK GENMASK(7, 0)
2043 #define B_AX_BCN_MSK_AREA_MASK GENMASK(27, 16)
2044 #define B_AX_BCN_CTN_AREA_MASK GENMASK(11, 0)
2051 #define B_AX_BCNERLY_MASK GENMASK(11, 0)
2058 #define B_AX_TBTTERLY_MASK GENMASK(11, 0)
2065 #define B_AX_TBTT_AGG_NUM_MASK GENMASK(15, 8)
2072 #define B_AX_SUB_BCN_SPACE_MASK GENMASK(23, 16)
2073 #define B_AX_BCN_SPACE_MASK GENMASK(15, 0)
2080 #define B_AX_FORCE_BCN_CURRCNT_MASK GENMASK(23, 16)
2081 #define B_AX_FORCE_BCN_NUM_MASK GENMASK(15, 0)
2082 #define B_AX_BCN_MAX_ERR_MASK GENMASK(7, 0)
2089 #define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24)
2090 #define B_AX_BCN_ERR_CNT_NAV_MASK GENMASK(23, 16)
2091 #define B_AX_BCN_ERR_CNT_EDCCA_MASK GENMASK(15, 0)
2092 #define B_AX_BCN_ERR_CNT_CCA_MASK GENMASK(7, 0)
2112 #define B_AX_DTIM_NUM_MASK GENMASK(15, 8)
2113 #define B_AX_DTIM_CURRCNT_MASK GENMASK(7, 0)
2120 #define B_AX_TBTT_SHIFT_OFST_MASK GENMASK(11, 0)
2122 #define B_AX_TBTT_SHIFT_OFST_MAG GENMASK(10, 0)
2129 #define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0)
2136 #define B_AX_TSFTR_LOW_MASK GENMASK(31, 0)
2143 #define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0)
2147 #define B_AX_P0MB_ALL_MASK GENMASK(23, 1)
2148 #define B_AX_P0MB_NUM_MASK GENMASK(19, 16)
2172 #define B_AX_PCIE_MODE_MASK GENMASK(15, 14)
2183 #define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
2184 #define B_AX_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16)
2185 #define B_AX_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8)
2186 #define B_AX_MAX_AGG_NUM_MASK GENMASK(7, 0)
2190 #define B_AX_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)
2191 #define B_AX_RTS_TXTIME_TH_MASK GENMASK(15, 8)
2192 #define B_AX_RTS_LEN_TH_MASK GENMASK(7, 0)
2197 #define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
2198 #define B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18)
2201 #define B_AX_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8)
2202 #define B_AX_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0)
2207 #define B_AX_DEFT_RATE_MASK GENMASK(15, 7)
2209 #define B_AX_MAX_TXNSS_MASK GENMASK(3, 2)
2216 #define B_AX_S_TXCNT_LMT_MASK GENMASK(29, 24)
2217 #define B_AX_L_TXCNT_LMT_MASK GENMASK(21, 16)
2222 #define B_AX_RATE_SEL_MASK GENMASK(29, 24)
2223 #define B_AX_PORT_DROP_4_0_MASK GENMASK(20, 16)
2224 #define B_AX_MBSSID_DROP_15_0_MASK GENMASK(15, 0)
2228 #define B_AX_RPT_LATCH_PHY_TIME_MASK GENMASK(15, 12)
2231 #define B_AX_BCN_RPT_PATH_MASK GENMASK(7, 6)
2232 #define B_AX_SPE_RPT_PATH_MASK GENMASK(5, 4)
2234 #define B_AX_TX_RPT_PATH_MASK GENMASK(3, 2)
2240 #define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16)
2254 #define B_AX_BSS_COLOB_AX_PORT_3_MASK GENMASK(29, 24)
2255 #define B_AX_BSS_COLOB_AX_PORT_2_MASK GENMASK(21, 16)
2256 #define B_AX_BSS_COLOB_AX_PORT_1_MASK GENMASK(13, 8)
2257 #define B_AX_BSS_COLOB_AX_PORT_0_MASK GENMASK(5, 0)
2261 #define B_AX_BSS_COLOB_AX_PORT_4_MASK GENMASK(5, 0)
2283 #define B_AX_PTCL_IMR_CLR_ALL GENMASK(31, 0)
2316 #define B_AX_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0)
2324 #define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0)
2328 #define B_AX_PTCL_DBG_SEL_MASK GENMASK(7, 0)
2344 #define B_AX_RXDMA_DBG_SEL_MASK GENMASK(30, 29)
2345 #define B_AX_RXDMA_FIFO_DBG_SEL_MASK GENMASK(28, 25)
2346 #define B_AX_RXDMA_DEFAULT_PAGE_MASK GENMASK(22, 21)
2347 #define B_AX_RXDMA_BUFF_REQ_PRI_MASK GENMASK(20, 19)
2348 #define B_AX_RXDMA_TGT_QUEID_MASK GENMASK(18, 13)
2349 #define B_AX_RXDMA_TGT_PRID_MASK GENMASK(12, 10)
2494 #define B_AX_TCR_ZLD_NUM_MASK GENMASK(31, 24)
2496 #define B_AX_TCR_UDF_THSD_MASK GENMASK(22, 16)
2498 #define B_AX_TCR_ERRSTEN_MASK GENMASK(15, 10)
2512 #define B_AX_TXDFIFO_THRESHOLD GENMASK(31, 28)
2515 #define B_AX_TCR_USTIME GENMASK(23, 16)
2520 #define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON GENMASK(11, 8)
2521 #define B_AX_TCR_TXTIMEOUT GENMASK(7, 0)
2525 #define B_AX_TSFT_OFS_MASK GENMASK(31, 16)
2526 #define B_AX_STMP_THSD_MASK GENMASK(15, 8)
2535 #define B_AX_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(28, 24)
2536 #define B_AX_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(20, 16)
2537 #define B_AX_TXDFIFO_HIGH_MCS_THRE_MASK GENMASK(15, 12)
2539 #define B_AX_TXDFIFO_LOW_MCS_THRE_MASK GENMASK(11, 8)
2541 #define B_AX_HIGH_MCS_PHY_RATE_MASK GENMASK(7, 4)
2542 #define B_AX_BW_PHY_RATE_MASK GENMASK(1, 0)
2546 #define B_AX_MACTX_MPDU_CNT GENMASK(31, 24)
2547 #define B_AX_MACTX_DMA_CNT GENMASK(23, 16)
2552 #define B_AX_DBGSEL_MACTX_MASK GENMASK(5, 0)
2556 #define B_AX_TX_CTRL_DEBUG_SEL_MASK GENMASK(3, 0)
2560 #define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0)
2564 #define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0)
2576 #define B_AX_ACKTO_CCK_MASK GENMASK(15, 8)
2577 #define B_AX_ACKTO_MASK GENMASK(7, 0)
2594 #define B_AX_WMAC_SPEC_SIFS_OFDM_MASK GENMASK(15, 8)
2595 #define B_AX_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0)
2604 #define B_AX_RESP_TX_PWRMODE_MASK GENMASK(30, 28)
2605 #define B_AX_FTM_RRSR_RATE_EN_MASK GENMASK(27, 24)
2606 #define B_AX_NESS_MASK GENMASK(23, 22)
2609 #define B_AX_WMAC_RRSB_AX_CCK_MASK GENMASK(19, 16)
2610 #define B_AX_WMAC_RESP_RATE_EN_MASK GENMASK(15, 12)
2611 #define B_AX_WMAC_RESP_RSC_MASK GENMASK(11, 10)
2613 #define B_AX_WMAC_RESP_REF_RATE_MASK GENMASK(8, 0)
2622 #define B_AX_WMAC_0P125US_TIMER_MASK GENMASK(25, 18)
2625 #define B_AX_WMAC_NAV_UPPER_MASK GENMASK(15, 8)
2628 #define B_AX_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0)
2632 #define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24)
2635 #define B_AX_RXTRIG_PORT_SEL_MASK GENMASK(19, 17)
2637 #define B_AX_RXTRIG_USERINFO_2_MASK GENMASK(15, 0)
2642 #define B_AX_WMAC_TIMETOUT_THR_MASK GENMASK(21, 16)
2672 #define B_AX_WMAC_TX_TF_INFO_SEL_MASK GENMASK(2, 0)
2676 #define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0)
2680 #define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0)
2697 #define B_AX_TMAC_TIMETOUT_THR_MASK GENMASK(5, 0)
2709 #define B_AX_DBGSEL_TRXPTCL_MASK GENMASK(7, 0)
2713 #define B_AX_PHYINTF_TIMEOUT_THR_MSAK_V1 GENMASK(21, 16)
2747 #define B_AX_PHYINTF_TIMEOUT_THR_MSAK GENMASK(5, 0)
2760 #define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24)
2761 #define B_AX_BFMER_VHT_CSI_OFFSET_MASK GENMASK(23, 16)
2762 #define B_AX_BFMER_HT_CSI_OFFSET_MASK GENMASK(15, 8)
2768 #define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24)
2769 #define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK GENMASK(23, 20)
2770 #define B_AX_MU_BFRPTSEG_SEL_MASK GENMASK(18, 17)
2784 #define B_AX_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24)
2789 #define B_AX_BFMEE_CSI_RSC_MASK GENMASK(19, 18)
2796 #define B_AX_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10)
2797 #define B_AX_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8)
2798 #define B_AX_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6)
2799 #define B_AX_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3)
2800 #define B_AX_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0)
2808 #define B_AX_BFMEE_HE_CSI_RATE_MASK GENMASK(22, 16)
2809 #define B_AX_BFMEE_VHT_CSI_RATE_MASK GENMASK(14, 8)
2810 #define B_AX_BFMEE_HT_CSI_RATE_MASK GENMASK(6, 0)
2818 #define B_AX_DRV_INFO_SIZE_MASK GENMASK(10, 8)
2819 #define B_AX_CH_EN_MASK GENMASK(3, 0)
2823 #define B_AX_RX_DLK_CCA_TIME_MASK GENMASK(15, 8)
2824 #define B_AX_RX_DLK_DATA_TIME_MASK GENMASK(7, 4)
2839 #define B_AX_UID_FILTER_MASK GENMASK(31, 24)
2841 #define B_AX_UNSPT_FILTER_MASK GENMASK(23, 22)
2842 #define B_AX_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16)
2849 #define B_AX_A_BCN_CHK_RULE_MASK GENMASK(9, 8)
2877 #define B_AX_ADDR_CAM_RANGE_MASK GENMASK(23, 16)
2878 #define B_AX_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12)
2887 #define B_AX_BACAM_RST_MASK GENMASK(1, 0)
2911 #define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0)
2912 #define B_AX_STATE_CUR_MASK GENMASK(31, 16)
2913 #define B_AX_STATE_NXT_MASK GENMASK(13, 8)
2915 #define B_AX_STATE_SEL_MASK GENMASK(4, 0)
2984 #define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0)
2985 #define B_AX_PCLP_MON_SEL_MASK GENMASK(31, 28)
2986 #define B_AX_PCLP_MON_CONT_MASK GENMASK(27, 0)
2990 #define B_AX_DEBUG_SEL_MASK GENMASK(7, 0)
2995 #define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0)
3000 #define B_AX_TXAGC_BT_MASK GENMASK(11, 3)
3004 #define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0)
3009 #define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0)
3010 #define B_AX_PWR_UL_TB_1T_V1_MASK GENMASK(7, 0)
3012 #define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0)
3013 #define B_AX_PWR_UL_TB_2T_V1_MASK GENMASK(7, 0)
3072 #define B_AX_BANDEDGE_CFG_IDX_MASK GENMASK(31, 30)
3085 #define B_AX_BTC_MODE_MASK GENMASK(25, 24)
3088 #define B_AX_COEX_DLY_CLK_MASK GENMASK(15, 8)
3092 #define B_AX_BTC_DBG_SEL_MASK GENMASK(4, 3)
3101 #define B_AX_BT_L_RX_ULTRA_MASK GENMASK(15, 14)
3102 #define B_AX_BT_L_TX_ULTRA_MASK GENMASK(13, 12)
3103 #define B_AX_BT_H_RX_ULTRA_MASK GENMASK(11, 10)
3104 #define B_AX_BT_H_TX_ULTRA_MASK GENMASK(9, 8)
3105 #define B_AX_SAMPLE_CLK_MASK GENMASK(7, 0)
3137 #define B_AX_TIMER_MASK GENMASK(7, 0)
3143 #define B_AX_BT_STAT_DELAY_MASK GENMASK(15, 12)
3145 #define B_AX_BT_TRX_INIT_DETECT_MASK GENMASK(11, 8)
3147 #define B_AX_BT_PRI_DETECT_TO_MASK GENMASK(7, 4)
3157 #define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16)
3158 #define B_AX_STATIS_BT_HI_TX_MASK GENMASK(15, 0)
3160 #define B_AX_STATIS_BT_LO_TX_1_MASK GENMASK(15, 0)
3161 #define B_AX_STATIS_BT_LO_RX_1_MASK GENMASK(31, 16)
3202 #define B_AX_R_BT_CMD_RPT_MASK GENMASK(31, 16)
3203 #define B_AX_R_RPT_FROM_BT_MASK GENMASK(15, 8)
3204 #define B_AX_BT_HID_ISR_SET_MASK GENMASK(7, 6)
3214 #define B_AX_BT_TIME_MASK GENMASK(31, 6)
3215 #define B_AX_BT_RPT_SAMPLE_RATE_MASK GENMASK(5, 0)
3253 #define B_AX_LTECOEX_OP_MODE_SEL_MASK GENMASK(5, 4)
3255 #define B_AX_LTECOEX_UART_MODE_SEL_MASK GENMASK(2, 0)
3271 #define RR_MOD_IQK GENMASK(19, 4)
3272 #define RR_MOD_DPK GENMASK(19, 5)
3273 #define RR_MOD_MASK GENMASK(19, 16)
3282 #define RR_MOD_NBW GENMASK(15, 14)
3283 #define RR_MOD_M_RXG GENMASK(13, 4)
3284 #define RR_MOD_M_RXBB GENMASK(9, 5)
3286 #define RR_MODOPT_M_TXPWR GENMASK(5, 0)
3288 #define RR_WLSEL_AG GENMASK(18, 16)
3296 #define RR_LOKVB_COI GENMASK(19, 14)
3297 #define RR_LOKVB_COQ GENMASK(9, 4)
3299 #define RR_TXIG_TG GENMASK(16, 12)
3300 #define RR_TXIG_GR1 GENMASK(6, 4)
3301 #define RR_TXIG_GR0 GENMASK(1, 0)
3303 #define RR_CHTR_MOD GENMASK(11, 10)
3304 #define RR_CHTR_TXRX GENMASK(9, 0)
3307 #define RR_CFGCH_BAND1 GENMASK(17, 16)
3311 #define RR_CFGCH_BAND0 GENMASK(9, 8)
3315 #define RR_CFGCH_BW GENMASK(11, 10)
3316 #define RR_CFGCH_CH GENMASK(7, 0)
3322 #define RR_APK_MOD GENMASK(5, 4)
3324 #define RR_BTC_TXBB GENMASK(14, 12)
3325 #define RR_BTC_RXBB GENMASK(11, 10)
3327 #define RR_RCKC_CA GENMASK(14, 10)
3330 #define RR_RCKO_OFF GENMASK(13, 9)
3332 #define RR_RXKPLL_OFF GENMASK(5, 0)
3335 #define RR_RSV4_AGH GENMASK(17, 16)
3336 #define RR_RSV4_PLLCH GENMASK(9, 0)
3342 #define RR_LUTWA_MASK GENMASK(9, 0)
3343 #define RR_LUTWA_M2 GENMASK(4, 0)
3346 #define RR_LUTWD0_LB GENMASK(5, 0)
3349 #define RR_TM_VAL GENMASK(6, 1)
3351 #define RR_TM2_OFF GENMASK(19, 16)
3360 #define RR_TXGA_LOK_EXT GENMASK(4, 0)
3363 #define RR_GAINTX_ALL GENMASK(15, 0)
3364 #define RR_GAINTX_PAD GENMASK(9, 5)
3365 #define RR_GAINTX_BB GENMASK(4, 0)
3367 #define RR_TXMO_COI GENMASK(19, 15)
3368 #define RR_TXMO_COQ GENMASK(14, 10)
3369 #define RR_TXMO_FII GENMASK(9, 6)
3370 #define RR_TXMO_FIQ GENMASK(5, 2)
3372 #define RR_TXA_TRK GENMASK(19, 14)
3378 #define RR_BIASA_TXG GENMASK(15, 12)
3379 #define RR_BIASA_TXA GENMASK(19, 16)
3380 #define RR_BIASA_A GENMASK(2, 0)
3382 #define RR_BIASA2_LB GENMASK(4, 2)
3384 #define RR_TXATANK_LBSW2 GENMASK(17, 15)
3385 #define RR_TXATANK_LBSW GENMASK(16, 15)
3387 #define RR_TXA2_LDO GENMASK(19, 16)
3395 #define RR_RXPOW_IQK GENMASK(17, 16)
3397 #define RR_RXBB_VOBUF GENMASK(15, 12)
3398 #define RR_RXBB_C2G GENMASK(16, 10)
3399 #define RR_RXBB_C1G GENMASK(9, 8)
3400 #define RR_RXBB_ATTR GENMASK(7, 4)
3401 #define RR_RXBB_ATTC GENMASK(2, 0)
3403 #define RR_RXG_IQKMOD GENMASK(19, 16)
3405 #define RR_XGLNA2_SW GENMASK(1, 0)
3407 #define RR_RXAE_IQKMOD GENMASK(3, 0)
3409 #define RR_RXA_DPK GENMASK(9, 8)
3411 #define RR_RXA2_C1 GENMASK(12, 10)
3412 #define RR_RXA2_C2 GENMASK(9, 3)
3413 #define RR_RXA2_IATT GENMASK(7, 4)
3414 #define RR_RXA2_ATT GENMASK(3, 0)
3416 #define RR_RXIQGEN_ATTL GENMASK(12, 8)
3417 #define RR_RXIQGEN_ATTH GENMASK(14, 13)
3421 #define RR_EN_TIA_IDA GENMASK(11, 10)
3422 #define RR_RXBB2_IDAC GENMASK(11, 9)
3423 #define RR_RXBB2_EBW GENMASK(6, 5)
3425 #define RR_XALNA2_SW GENMASK(1, 0)
3427 #define RR_DCK_DONE GENMASK(7, 5)
3432 #define RR_DCK1_CLR GENMASK(3, 0)
3435 #define RR_DCK2_CYCLE GENMASK(7, 2)
3439 #define RR_IQGEN_BIAS GENMASK(11, 8)
3441 #define RR_TXIQK_ATT2 GENMASK(15, 12)
3445 #define RR_MIXER_GN GENMASK(4, 3)
3447 #define RR_LOGEN_RPT GENMASK(19, 16)
3453 #define RR_IQKPLL_MOD GENMASK(9, 8)
3455 #define RR_RCKD_POW GENMASK(19, 13)
3474 #define B_ANAPAR_PW15 GENMASK(31, 24)
3475 #define B_ANAPAR_PW15_H GENMASK(27, 24)
3476 #define B_ANAPAR_PW15_H2 GENMASK(27, 26)
3478 #define B_ANAPAR_15 GENMASK(31, 16)
3481 #define B_ANAPAR_CRXBB GENMASK(18, 16)
3482 #define B_ANAPAR_14 GENMASK(15, 0)
3488 #define B_SWSI_DATA_VAL_V1 GENMASK(19, 0)
3489 #define B_SWSI_DATA_ADDR_V1 GENMASK(27, 20)
3490 #define B_SWSI_DATA_PATH_V1 GENMASK(30, 28)
3493 #define B_SWSI_BIT_MASK_V1 GENMASK(19, 0)
3495 #define B_SWSI_READ_ADDR_ADDR_V1 GENMASK(7, 0)
3496 #define B_SWSI_READ_ADDR_PATH_V1 GENMASK(10, 8)
3497 #define B_SWSI_READ_ADDR_V1 GENMASK(10, 0)
3499 #define B_UPD_CLK_ADC_VAL GENMASK(26, 25)
3505 #define B_CH_IDX_SEG0 GENMASK(23, 16)
3507 #define B_STS_PARSING_TIME GENMASK(19, 16)
3511 #define B_PHY_STS_BITMAP_ADDR_MASK GENMASK(6, 2)
3531 #define B_PMAC_GNT_P1 GENMASK(20, 17)
3532 #define B_PMAC_GNT_P2 GENMASK(29, 26)
3534 #define B_PMAC_OPT1_MSK GENMASK(11, 0)
3536 #define B_PMAC_RXMOD_MSK GENMASK(7, 4)
3541 #define B_MAC_SEL_MOD GENMASK(4, 2)
3545 #define B_PMAC_TX_PRD_MSK GENMASK(31, 8)
3549 #define B_PMAC_TX_CNT_MSK GENMASK(31, 0)
3555 #define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4)
3560 #define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16)
3561 #define B_IFS_CLM_COUNTER_UNIT_MSK GENMASK(15, 14)
3565 #define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16)
3567 #define B_IFS_T1_TH_LOW_MSK GENMASK(14, 0)
3569 #define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16)
3571 #define B_IFS_T2_TH_LOW_MSK GENMASK(14, 0)
3573 #define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16)
3575 #define B_IFS_T3_TH_LOW_MSK GENMASK(14, 0)
3577 #define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16)
3579 #define B_IFS_T4_TH_LOW_MSK GENMASK(14, 0)
3589 #define B_SNDCCA_A1_EN GENMASK(19, 12)
3591 #define B_SNDCCA_A2_VAL GENMASK(19, 12)
3593 #define B_RXHT_MCS_LIMIT GENMASK(9, 8)
3595 #define B_RXVHT_MCS_LIMIT GENMASK(22, 21)
3599 #define B_RXHETB_MAX_NSS GENMASK(25, 23)
3600 #define B_RXHE_MAX_NSS GENMASK(16, 14)
3601 #define B_RXHE_USER_MAX GENMASK(13, 6)
3611 #define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
3614 #define B_P0_TXCK_ALL GENMASK(19, 12)
3616 #define B_P0_RXCK_VAL GENMASK(18, 16)
3618 #define B_P0_TXCK_VAL GENMASK(14, 12)
3620 #define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
3621 #define B_P0_RFMODE_MUX GENMASK(11, 4)
3625 #define B_S0_RXDC_I GENMASK(25, 16)
3626 #define B_S0_RXDC_Q GENMASK(31, 26)
3628 #define B_S0_RXDC2_SEL GENMASK(9, 8)
3629 #define B_S0_RXDC2_AVG GENMASK(7, 6)
3630 #define B_S0_RXDC2_MEN GENMASK(5, 4)
3631 #define B_S0_RXDC2_Q2 GENMASK(3, 0)
3642 #define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16)
3643 #define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0)
3645 #define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16)
3646 #define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0)
3648 #define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16)
3649 #define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0)
3651 #define B_IFS_T4_HIS_MSK GENMASK(31, 24)
3652 #define B_IFS_T3_HIS_MSK GENMASK(23, 16)
3653 #define B_IFS_T2_HIS_MSK GENMASK(15, 8)
3654 #define B_IFS_T1_HIS_MSK GENMASK(7, 0)
3656 #define B_IFS_T2_AVG_MSK GENMASK(31, 16)
3657 #define B_IFS_T1_AVG_MSK GENMASK(15, 0)
3659 #define B_IFS_T4_AVG_MSK GENMASK(31, 16)
3660 #define B_IFS_T3_AVG_MSK GENMASK(15, 0)
3662 #define B_IFS_T2_CCA_MSK GENMASK(31, 16)
3663 #define B_IFS_T1_CCA_MSK GENMASK(15, 0)
3665 #define B_IFS_T4_CCA_MSK GENMASK(31, 16)
3666 #define B_IFS_T3_CCA_MSK GENMASK(15, 0)
3669 #define B_IFSCNT_TOTAL_CNT_MSK GENMASK(15, 0)
3671 #define B_TXAGC_TP GENMASK(2, 0)
3673 #define B_TSSI_THER GENMASK(29, 24)
3675 #define B_TXAGC_BTP GENMASK(31, 24)
3677 #define B_TXAGC_BB_OFT GENMASK(31, 16)
3678 #define B_TXAGC_BB GENMASK(31, 24)
3680 #define B_S0_ADDCK_I GENMASK(9, 0)
3681 #define B_S0_ADDCK_Q GENMASK(19, 10)
3683 #define B_ADC_FIFO_RST GENMASK(31, 24)
3684 #define B_ADC_FIFO_RXK GENMASK(31, 16)
3690 #define B_TXFIR_C01 GENMASK(23, 0)
3692 #define B_TXFIR_C23 GENMASK(23, 0)
3694 #define B_TXFIR_C45 GENMASK(23, 0)
3696 #define B_TXFIR_C67 GENMASK(23, 0)
3698 #define B_TXFIR_C89 GENMASK(23, 0)
3700 #define B_TXFIR_CAB GENMASK(23, 0)
3702 #define B_TXFIR_CCD GENMASK(23, 0)
3704 #define B_TXFIR_CEF GENMASK(23, 0)
3708 #define B_RPL_OFST_MASK GENMASK(14, 8)
3716 #define B_RXSCOBC_TH GENMASK(18, 0)
3718 #define B_RXSCOCCK_TH GENMASK(18, 0)
3727 #define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
3729 #define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
3730 #define B_P1_RFMODE_MUX GENMASK(11, 4)
3734 #define B_S1_RXDC_I GENMASK(25, 16)
3735 #define B_S1_RXDC_Q GENMASK(31, 26)
3737 #define B_S1_RXDC2_EN GENMASK(5, 4)
3738 #define B_S1_RXDC2_SEL GENMASK(9, 8)
3739 #define B_S1_RXDC2_Q2 GENMASK(3, 0)
3741 #define B_TXAGC_BB_S1_OFT GENMASK(31, 16)
3742 #define B_TXAGC_BB_S1 GENMASK(31, 24)
3744 #define B_S1_ADDCK_I GENMASK(9, 0)
3745 #define B_S1_ADDCK_Q GENMASK(19, 10)
3749 #define B_DCFO GENMASK(1, 0)
3751 #define B_SEG0CSI_IDX GENMASK(11, 0)
3756 #define B_BSS_CLR_MAP_TGT GENMASK(27, 22)
3757 #define B_BSS_CLR_MAP_STAID GENMASK(21, 11)
3760 #define B_CFO_TRK_MSK GENMASK(14, 10)
3768 #define B_DCFO_COMP_S0_MSK GENMASK(11, 0)
3770 #define B_DCFO_WEIGHT_MSK GENMASK(27, 24)
3776 #define B_TXPATH_SEL_MSK GENMASK(31, 28)
3778 #define B_TXPWR_MSK GENMASK(30, 22)
3780 #define B_TXNSS_MAP_MSK GENMASK(20, 17)
3782 #define B_PCOEFF01_MSK_V1 GENMASK(23, 0)
3784 #define B_PCOEFF23_MSK_V1 GENMASK(23, 0)
3786 #define B_PCOEFF45_MSK_V1 GENMASK(23, 0)
3788 #define B_PCOEFF67_MSK_V1 GENMASK(23, 0)
3790 #define B_PCOEFF89_MSK_V1 GENMASK(23, 0)
3792 #define B_PCOEFFAB_MSK_V1 GENMASK(23, 0)
3794 #define B_PCOEFFCD_MSK_V1 GENMASK(23, 0)
3796 #define B_PCOEFFEF_MSK_V1 GENMASK(23, 0)
3798 #define B_PATH0_IB_PKPW_MSK GENMASK(11, 6)
3800 #define B_PATH0_LNA_ERR_G1_A_MSK GENMASK(29, 24)
3801 #define B_PATH0_LNA_ERR_G0_G_MSK GENMASK(17, 12)
3802 #define B_PATH0_LNA_ERR_G0_A_MSK GENMASK(11, 6)
3804 #define B_PATH0_LNA_ERR_G2_G_MSK GENMASK(23, 18)
3805 #define B_PATH0_LNA_ERR_G2_A_MSK GENMASK(17, 12)
3806 #define B_PATH0_LNA_ERR_G1_G_MSK GENMASK(5, 0)
3808 #define B_PATH0_LNA_ERR_G4_G_MSK GENMASK(29, 24)
3809 #define B_PATH0_LNA_ERR_G4_A_MSK GENMASK(23, 18)
3810 #define B_PATH0_LNA_ERR_G3_G_MSK GENMASK(11, 6)
3811 #define B_PATH0_LNA_ERR_G3_A_MSK GENMASK(5, 0)
3813 #define B_PATH0_LNA_ERR_G6_A_MSK GENMASK(29, 24)
3814 #define B_PATH0_LNA_ERR_G5_G_MSK GENMASK(17, 12)
3815 #define B_PATH0_LNA_ERR_G5_A_MSK GENMASK(11, 6)
3817 #define B_PATH0_LNA_ERR_G6_G_MSK GENMASK(5, 0)
3819 #define B_PATH0_TIA_ERR_G0_G_MSK GENMASK(23, 18)
3820 #define B_PATH0_TIA_ERR_G0_A_MSK GENMASK(17, 12)
3822 #define B_PATH0_TIA_ERR_G1_SEL GENMASK(31, 30)
3823 #define B_PATH0_TIA_ERR_G1_G_MSK GENMASK(11, 6)
3824 #define B_PATH0_TIA_ERR_G1_A_MSK GENMASK(5, 0)
3826 #define B_PATH0_IB_PBK_MSK GENMASK(14, 10)
3828 #define B_PATH0_RXB_INIT_IDX_MSK GENMASK(9, 5)
3831 #define B_PATH0_LNA_INIT_IDX_MSK GENMASK(26, 24)
3833 #define B_PATH0_BTG_SHEN GENMASK(18, 17)
3845 #define B_PATH0_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10)
3847 #define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24)
3849 #define B_PATH0_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
3851 #define B_PATH0_R_G_OFST_MASK GENMASK(23, 16)
3852 #define B_PATH0_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8)
3862 #define B_P0_NBIIDX_VAL GENMASK(11, 0)
3865 #define B_P0_BACKOFF_IBADC_V1 GENMASK(31, 26)
3868 #define B_P1_MODE_SEL GENMASK(31, 30)
3873 #define B_PATH1_LNA_INIT_IDX_MSK GENMASK(26, 24)
3879 #define B_PATH1_BTG_SHEN GENMASK(18, 17)
3881 #define B_PATH1_RXB_INIT_IDX_MSK GENMASK(9, 5)
3883 #define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24)
3893 #define B_PATH1_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
3895 #define B_PATH1_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8)
3903 #define B_P1_NBIIDX_VAL GENMASK(11, 0)
3909 #define B_SEG0R_PD_LOWER_BOUND_MSK GENMASK(10, 6)
3913 #define B_FC0_BW_INV GENMASK(6, 0)
3914 #define B_FC0_BW_SET GENMASK(31, 30)
3915 #define B_ANT_RX_BT_SEG0 GENMASK(25, 22)
3916 #define B_ANT_RX_1RCCA_SEG1 GENMASK(21, 18)
3917 #define B_ANT_RX_1RCCA_SEG0 GENMASK(17, 14)
3920 #define B_CHBW_MOD_SBW GENMASK(13, 12)
3921 #define B_CHBW_MOD_PRICH GENMASK(11, 8)
3922 #define B_ANT_RX_SEG0 GENMASK(3, 0)
3926 #define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26)
3928 #define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0)
3930 #define B_CCK_FC0_INV_MSK_V1 GENMASK(18, 0)
3932 #define B_PATH1_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10)
3938 #define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)
3940 #define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0)
3942 #define B_PATH0_BT_BACKOFF_V1 GENMASK(23, 0)
3944 #define B_PATH1_BT_BACKOFF_V1 GENMASK(23, 0)
3946 #define B_PATH0_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
3949 #define B_PATH0_NOTCH_VAL GENMASK(11, 0)
3952 #define B_PATH0_NOTCH2_VAL GENMASK(11, 0)
3957 #define B_PATH0_5MDET_TH GENMASK(5, 0)
3959 #define B_PATH1_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
3962 #define B_PATH1_NOTCH_VAL GENMASK(11, 0)
3965 #define B_PATH1_NOTCH2_VAL GENMASK(11, 0)
3970 #define B_PATH1_5MDET_TH GENMASK(5, 0)
3972 #define B_RPL_BIAS_COMP_MASK GENMASK(7, 0)
3974 #define B_RPL_PATHB_MASK GENMASK(23, 16)
3975 #define B_RPL_PATHA_MASK GENMASK(15, 8)
3977 #define B_RSSI_M_PATHB_MASK GENMASK(15, 8)
3978 #define B_RSSI_M_PATHA_MASK GENMASK(7, 0)
3980 #define B_FC0_MSK_V1 GENMASK(12, 0)
3984 #define B_DCFO_COMP_S0_V1_MSK GENMASK(13, 0)
3986 #define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)
3993 #define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24)
3994 #define B_CFO_COMP_VAL_MSK GENMASK(11, 0)
3997 #define B_ACK_VAL GENMASK(30, 29)
4003 #define B_TXPWRB_VAL GENMASK(27, 19)
4007 #define B_DPD_OFT_ADDR GENMASK(31, 27)
4011 #define B_P0_TMETER GENMASK(15, 10)
4017 #define B_P0_TSSI_OFT GENMASK(7, 0)
4019 #define B_P0_TSSI_AVG GENMASK(15, 12)
4021 #define B_P0_RFCTM_VAL GENMASK(25, 20)
4027 #define B_P0_TRSW_SO_A2 GENMASK(7, 5)
4032 #define B_P0_RFM_OUT GENMASK(4, 0)
4034 #define B_P0_TXDPD GENMASK(31, 28)
4039 #define B_P0_TSSI_MV_AVG GENMASK(13, 11)
4042 #define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
4045 #define B_S0_DACKI_AR GENMASK(31, 28)
4048 #define B_S0_DACKI2_K GENMASK(21, 12)
4050 #define B_S0_DACKI7_K GENMASK(15, 8)
4052 #define B_S0_DACKI8_K GENMASK(15, 8)
4054 #define B_S0_DACKQ_AR GENMASK(31, 28)
4057 #define B_S0_DACKQ2_K GENMASK(21, 12)
4059 #define B_S0_DACKQ7_K GENMASK(15, 8)
4061 #define B_S0_DACKQ8_K GENMASK(15, 8)
4063 #define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0)
4065 #define B_P1_TMETER GENMASK(15, 10)
4071 #define B_P1_TSSI_OFT GENMASK(7, 0)
4073 #define B_P1_TSSI_AVG GENMASK(15, 12)
4076 #define B_P1_RFCTM_VAL GENMASK(25, 20)
4081 #define B_P1_TSSI_MV_AVG GENMASK(13, 11)
4084 #define B_S1_DACKI_AR GENMASK(31, 28)
4087 #define B_S1_DACKI2_K GENMASK(21, 12)
4089 #define B_S1_DACKI_K GENMASK(15, 8)
4091 #define B_S1_DACKI8_K GENMASK(15, 8)
4093 #define B_S1_DACKQ_AR GENMASK(31, 28)
4096 #define B_S1_DACKQ2_K GENMASK(21, 12)
4098 #define B_S1_DACKQ7_K GENMASK(15, 8)
4100 #define B_S1_DACKQ8_K GENMASK(15, 8)
4102 #define B_NCTL_CFG_SPAGE GENMASK(2, 1)
4106 #define B_NCTL_N1_CIP GENMASK(7, 0)
4110 #define B_IQK_DIF_TRX GENMASK(1, 0)
4112 #define B_IQK_DIF1_TXPI GENMASK(19, 0)
4114 #define B_IQK_DIF2_RXPI GENMASK(19, 0)
4116 #define B_IQK_DIF4_RXT GENMASK(27, 16)
4117 #define B_IQK_DIF4_TXT GENMASK(11, 0)
4120 #define B_IQK_CFG_SET GENMASK(5, 4)
4123 #define B_TPG_MOD_F GENMASK(2, 1)
4126 #define B_MDPK_SYNC_MAN GENMASK(31, 28)
4130 #define B_KIP_MOD GENMASK(19, 0)
4138 #define B_LDL_NORM_PN GENMASK(12, 8)
4139 #define B_LDL_NORM_OP GENMASK(1, 0)
4143 #define B_DPK_CFG_IDX GENMASK(14, 12)
4148 #define B_KPATH_CFG_ED GENMASK(21, 20)
4150 #define B_KIP_RPT1_SEL GENMASK(21, 16)
4165 #define B_PRT_COM_DCI GENMASK(27, 16)
4166 #define B_PRT_COM_CORV GENMASK(15, 8)
4167 #define B_PRT_COM_DCQ GENMASK(11, 0)
4169 #define B_PRT_COM_GL GENMASK(7, 4)
4170 #define B_PRT_COM_CORI GENMASK(7, 0)
4171 #define B_PRT_COM_RXBB GENMASK(5, 0)
4178 #define B_IQK_RES_TXCFIR GENMASK(11, 8)
4179 #define B_IQK_RES_RXCFIR GENMASK(3, 0)
4184 #define B_RXIQC_NEWP GENMASK(19, 8)
4185 #define B_RXIQC_NEWX GENMASK(31, 20)
4190 #define B_RFGAIN_PAD GENMASK(4, 0)
4191 #define B_RFGAIN_TXBB GENMASK(12, 8)
4193 #define B_RFGAIN_BND GENMASK(4, 0)
4200 #define B_CFIR_LUT_GP_V1 GENMASK(2, 0)
4201 #define B_CFIR_LUT_GP GENMASK(1, 0)
4203 #define B_DPK_GN_EN GENMASK(17, 16)
4204 #define B_DPK_GN_AG GENMASK(9, 0)
4210 #define B_DPD_MEN GENMASK(31, 28)
4211 #define B_DPD_ORDER GENMASK(26, 24)
4212 #define B_DPD_SEL GENMASK(13, 8)
4214 #define B_TXAGC_RFK_CH0 GENMASK(5, 0)
4217 #define B_KIP_IQP_SW GENMASK(13, 12)
4218 #define B_KIP_IQP_IQSW GENMASK(5, 0)
4220 #define B_KIP_RPT_SEL GENMASK(21, 16)
4224 #define B_LOAD_COEF_CFIR GENMASK(1, 0)
4228 #define B_DPK_GL_A0 GENMASK(31, 28)
4229 #define B_DPK_GL_A1 GENMASK(17, 0)
4231 #define B_RPT_PER_TSSI GENMASK(28, 16)
4232 #define B_RPT_PER_OF GENMASK(15, 8)
4233 #define B_RPT_PER_TH GENMASK(5, 0)
4251 #define B_IQKINF_VER GENMASK(31, 24)
4252 #define B_IQKINF_FAIL_RXGRP GENMASK(23, 16)
4253 #define B_IQKINF_FAIL_TXGRP GENMASK(15, 8)
4254 #define B_IQKINF_FAIL GENMASK(3, 0)
4260 #define B_IQKCH_CH GENMASK(15, 8)
4261 #define B_IQKCH_BW GENMASK(7, 4)
4262 #define B_IQKCH_BAND GENMASK(3, 0)
4264 #define B_IQKINF2_FCNT GENMASK(23, 16)
4265 #define B_IQKINF2_KCNT GENMASK(15, 8)
4266 #define B_IQKINF2_NCTLV GENMASK(7, 0)
4268 #define B_DCOF0_V GENMASK(4, 1)
4272 #define B_DCOF8_V GENMASK(4, 1)
4276 #define B_DACK_BIAS00 GENMASK(11, 2)
4278 #define B_DACK_S0M0 GENMASK(31, 24)
4281 #define B_DACK_DADCK00 GENMASK(31, 24)
4285 #define B_DACK_BIAS01 GENMASK(11, 2)
4287 #define B_DACK_S0M1 GENMASK(31, 24)
4290 #define B_DACK_DADCK01 GENMASK(31, 24)
4294 #define B_DRCK_VAL GENMASK(4, 0)
4296 #define B_DRCK_RES GENMASK(19, 15)
4299 #define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
4301 #define B_P0_CFCH_BW0 GENMASK(27, 26)
4303 #define B_P0_CFCH_BW1 GENMASK(8, 5)
4305 #define B_ADDCK0 GENMASK(9, 8)
4309 #define B_ADDCK0_RLS GENMASK(29, 28)
4310 #define B_ADDCK0_RL1 GENMASK(27, 18)
4311 #define B_ADDCK0_RL0 GENMASK(17, 8)
4313 #define B_ADDCKR0_A0 GENMASK(19, 10)
4314 #define B_ADDCKR0_A1 GENMASK(9, 0)
4316 #define B_DACK10 GENMASK(4, 1)
4320 #define B_DACK11 GENMASK(4, 1)
4324 #define B_DACK_BIAS10 GENMASK(11, 2)
4326 #define B_DACK10S GENMASK(31, 24)
4330 #define B_DACK_DADCK10 GENMASK(31, 24)
4334 #define B_DACK_BIAS11 GENMASK(11, 2)
4336 #define B_DACK11S GENMASK(31, 24)
4340 #define B_DACK_DADCK11 GENMASK(31, 24)
4342 #define B_PATH1_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
4344 #define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5)
4346 #define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5)
4348 #define B_ADDCK1 GENMASK(9, 8)
4352 #define B_ADDCK1_RLS GENMASK(29, 28)
4353 #define B_ADDCK1_RL1 GENMASK(27, 18)
4354 #define B_ADDCK1_RL0 GENMASK(17, 8)
4356 #define B_ADDCKR1_A0 GENMASK(19, 10)
4357 #define B_ADDCKR1_A1 GENMASK(9, 0)
4367 #define B_AX_WDT_COUNT_MASK GENMASK(15, 0)