Lines Matching refs:GENMASK
19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
20 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
21 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
22 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
23 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
54 #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */
55 #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */
56 #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */
68 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
71 #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)
78 #define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0)
79 #define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8)
88 #define MT_USB_DMA_CFG_EP_OUT_VALID GENMASK(29, 24)
96 #define MT_WLAN_MTC_CTRL_BBP_MEM_PD GENMASK(19, 16)
110 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
111 #define MT_INT_TX_DONE_ALL GENMASK(13, 4)
130 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
133 #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)
142 #define MT_WMM_AIFSN_MASK GENMASK(3, 0)
146 #define MT_WMM_CWMIN_MASK GENMASK(3, 0)
150 #define MT_WMM_CWMAX_MASK GENMASK(3, 0)
156 #define MT_WMM_TXOP_MASK GENMASK(15, 0)
167 #define MT_US_CYC_CNT GENMASK(7, 0)
199 #define MT_RF_CSR_CFG_DATA GENMASK(7, 0)
200 #define MT_RF_CSR_CFG_REG_ID GENMASK(14, 8)
201 #define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 15)
213 #define MT_RF_CTRL_ADDR GENMASK(11, 0)
238 #define MT_LED_STATUS_OFF GENMASK(31, 24)
239 #define MT_LED_STATUS_ON GENMASK(23, 16)
240 #define MT_LED_STATUS_DURATION GENMASK(15, 8)
253 #define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN GENMASK(15, 8)
254 #define MT_FCE_L2_STUFF_TS_LEN_EN GENMASK(23, 16)
255 #define MT_FCE_L2_STUFF_OTHER_PORT GENMASK(25, 24)
277 #define MT_MAC_ADDR_DW1_U2ME_MASK GENMASK(23, 16)
281 #define MT_MAC_BSSID_DW1_ADDR GENMASK(15, 0)
282 #define MT_MAC_BSSID_DW1_MBSS_MODE GENMASK(17, 16)
283 #define MT_MAC_BSSID_DW1_MBEACON_N GENMASK(20, 18)
287 #define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE GENMASK(26, 24)
290 #define MT_MAX_LEN_CFG_AMPDU GENMASK(13, 12)
309 #define MT_MAC_APC_BSSID_H_ADDR GENMASK(15, 0)
313 #define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0)
314 #define MT_XIFS_TIME_CFG_OFDM_SIFS GENMASK(15, 8)
315 #define MT_XIFS_TIME_CFG_OFDM_XIFS GENMASK(19, 16)
316 #define MT_XIFS_TIME_CFG_EIFS GENMASK(28, 20)
320 #define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0)
321 #define MT_BKOFF_SLOT_CFG_CC_DELAY GENMASK(11, 8)
331 #define MT_CH_TIME_CFG_CH_TIMER_CLR GENMASK(9, 8)
332 #define MT_CH_TIME_CFG_MDRDY_CLR GENMASK(11, 10)
337 #define MT_BEACON_TIME_CFG_INTVAL GENMASK(15, 0)
339 #define MT_BEACON_TIME_CFG_SYNC_MODE GENMASK(18, 17)
342 #define MT_BEACON_TIME_CFG_TSF_COMP GENMASK(31, 24)
348 #define MT_TBTT_TIMER_VAL GENMASK(16, 0)
351 #define MT_INT_TIMER_CFG_PRE_TBTT GENMASK(15, 0)
352 #define MT_INT_TIMER_CFG_GP_TIMER GENMASK(31, 16)
382 #define MT_EDCA_CFG_TXOP GENMASK(7, 0)
383 #define MT_EDCA_CFG_AIFSN GENMASK(11, 8)
384 #define MT_EDCA_CFG_CWMIN GENMASK(15, 12)
385 #define MT_EDCA_CFG_CWMAX GENMASK(19, 16)
393 #define MT_TX_PIN_CFG_TXANT GENMASK(3, 0)
394 #define MT_TX_PIN_CFG_RXANT GENMASK(11, 8)
415 #define MT_TXOP_TRUN_EN GENMASK(5, 0)
416 #define MT_TXOP_EXT_CCA_DLY GENMASK(15, 8)
420 #define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0)
421 #define MT_TX_RTS_CFG_THRESH GENMASK(23, 8)
425 #define MT_TX_TIMEOUT_CFG_ACKTO GENMASK(15, 8)
435 #define MT_PROT_CFG_RATE GENMASK(15, 0)
436 #define MT_PROT_CFG_CTRL GENMASK(17, 16)
437 #define MT_PROT_CFG_NAV GENMASK(19, 18)
438 #define MT_PROT_CFG_TXOP_ALLOW GENMASK(25, 20)
448 #define MT_PROT_RATE GENMASK(15, 0)
465 #define MT_PROT_TXOP_ALLOW_ALL GENMASK(25, 20)
476 #define MT_TX_FBK_LIMIT_MPDU_FBK GENMASK(7, 0)
477 #define MT_TX_FBK_LIMIT_AMPDU_FBK GENMASK(15, 8)
488 #define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0)
489 #define MT_TX_ALC_CFG_0_CH_INIT_1 GENMASK(13, 8)
490 #define MT_TX_ALC_CFG_0_LIMIT_0 GENMASK(21, 16)
491 #define MT_TX_ALC_CFG_0_LIMIT_1 GENMASK(29, 24)
494 #define MT_TX_ALC_CFG_1_TEMP_COMP GENMASK(5, 0)
497 #define MT_TX_ALC_CFG_2_TEMP_COMP GENMASK(5, 0)
543 #define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0)
544 #define MT_EXT_CCA_CFG_CCA1 GENMASK(3, 2)
545 #define MT_EXT_CCA_CFG_CCA2 GENMASK(5, 4)
546 #define MT_EXT_CCA_CFG_CCA3 GENMASK(7, 6)
547 #define MT_EXT_CCA_CFG_CCA_MASK GENMASK(11, 8)
548 #define MT_EXT_CCA_CFG_ED_CCA_MASK GENMASK(15, 12)
558 #define MT_PROT_AUTO_TX_CFG_PROT_PADJ GENMASK(11, 8)
559 #define MT_PROT_AUTO_TX_CFG_AUTO_PADJ GENMASK(27, 24)
562 #define MT_RX_STAT_0_CRC_ERRORS GENMASK(15, 0)
563 #define MT_RX_STAT_0_PHY_ERRORS GENMASK(31, 16)
566 #define MT_RX_STAT_1_CCA_ERRORS GENMASK(15, 0)
567 #define MT_RX_STAT_1_PLCP_ERRORS GENMASK(31, 16)
570 #define MT_RX_STAT_2_DUP_ERRORS GENMASK(15, 0)
571 #define MT_RX_STAT_2_OVERFLOW_ERRORS GENMASK(31, 16)
574 #define MT_TX_STA_0_BEACONS GENMASK(31, 16)
584 #define MT_TX_STAT_FIFO_WCID GENMASK(15, 8)
585 #define MT_TX_STAT_FIFO_RATE GENMASK(31, 16)
598 #define MT_TX_STAT_FIFO_EXT_RETRY GENMASK(7, 0)
599 #define MT_TX_STAT_FIFO_EXT_PKTID GENMASK(15, 8)
621 #define MT_BBP_CORE_R1_BW GENMASK(4, 3)
623 #define MT_BBP_AGC_R0_CTRL_CHAN GENMASK(9, 8)
624 #define MT_BBP_AGC_R0_BW GENMASK(14, 12)
627 #define MT_BBP_AGC_LNA_HIGH_GAIN GENMASK(21, 16)
628 #define MT_BBP_AGC_LNA_MID_GAIN GENMASK(13, 8)
629 #define MT_BBP_AGC_LNA_LOW_GAIN GENMASK(5, 0)
632 #define MT_BBP_AGC_LNA_ULOW_GAIN GENMASK(5, 0)
635 #define MT_BBP_AGC_LNA_GAIN_MODE GENMASK(7, 6)
636 #define MT_BBP_AGC_GAIN GENMASK(14, 8)
638 #define MT_BBP_AGC20_RSSI0 GENMASK(7, 0)
639 #define MT_BBP_AGC20_RSSI1 GENMASK(15, 8)
641 #define MT_BBP_TXBE_R0_CTRL_CHAN GENMASK(1, 0)
658 #define MT_WCID_ATTR_PKEY_MODE GENMASK(3, 1)
659 #define MT_WCID_ATTR_BSS_IDX GENMASK(6, 4)
660 #define MT_WCID_ATTR_RXWI_UDF GENMASK(9, 7)
664 #define MT_WCID_ATTR_WAPI_KEYID GENMASK(31, 24)
677 #define MT_SKEY_MODE_MASK GENMASK(3, 0)
683 #define MT_TEMP_SENSOR_VAL GENMASK(6, 0)