Lines Matching refs:GENMASK
35 #define MT_TXD0_Q_IDX GENMASK(31, 25)
36 #define MT_TXD0_PKT_FMT GENMASK(24, 23)
37 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
38 #define MT_TXD0_TX_BYTES GENMASK(15, 0)
42 #define MT_TXD1_OWN_MAC GENMASK(29, 24)
44 #define MT_TXD1_TID GENMASK(22, 20)
45 #define MT_TXD1_HDR_PAD GENMASK(19, 18)
46 #define MT_TXD1_HDR_FORMAT GENMASK(17, 16)
47 #define MT_TXD1_HDR_INFO GENMASK(15, 11)
50 #define MT_TXD1_WLAN_IDX GENMASK(9, 0)
54 #define MT_TXD2_POWER_OFFSET GENMASK(29, 24)
55 #define MT_TXD2_MAX_TX_TIME GENMASK(23, 16)
56 #define MT_TXD2_FRAG GENMASK(15, 14)
65 #define MT_TXD2_FRAME_TYPE GENMASK(5, 4)
66 #define MT_TXD2_SUB_TYPE GENMASK(3, 0)
72 #define MT_TXD3_SEQ GENMASK(27, 16)
73 #define MT_TXD3_REM_TX_COUNT GENMASK(15, 11)
74 #define MT_TXD3_TX_COUNT GENMASK(10, 6)
82 #define MT_TXD4_PN_LOW GENMASK(31, 0)
84 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
90 #define MT_TXD5_PID GENMASK(7, 0)
94 #define MT_TXD6_TX_RATE GENMASK(29, 16)
95 #define MT_TXD6_SGI GENMASK(15, 14)
96 #define MT_TXD6_HELTF GENMASK(13, 12)
99 #define MT_TXD6_ANT_ID GENMASK(7, 4)
102 #define MT_TXD6_BW GENMASK(1, 0)
104 #define MT_TXD7_TXD_LEN GENMASK(31, 30)
107 #define MT_TXD7_TYPE GENMASK(21, 20)
108 #define MT_TXD7_SUB_TYPE GENMASK(19, 16)
110 #define MT_TXD7_PSE_FID GENMASK(27, 16)
111 #define MT_TXD7_SPE_IDX GENMASK(15, 11)
113 #define MT_TXD7_TX_TIME GENMASK(9, 0)
115 #define MT_TXD8_L_TYPE GENMASK(5, 4)
116 #define MT_TXD8_L_SUB_TYPE GENMASK(3, 0)
119 #define MT_TX_RATE_NSS GENMASK(12, 10)
120 #define MT_TX_RATE_MODE GENMASK(9, 6)
124 #define MT_TX_RATE_IDX GENMASK(5, 0)
127 #define MT_TXS0_BW GENMASK(30, 29)
128 #define MT_TXS0_TID GENMASK(28, 26)
130 #define MT_TXS0_TXS_FORMAT GENMASK(24, 23)
139 #define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16)
143 #define MT_TXS0_TX_RATE GENMASK(13, 0)
145 #define MT_TXS1_SEQNO GENMASK(31, 20)
146 #define MT_TXS1_RESP_RATE GENMASK(19, 16)
147 #define MT_TXS1_RXV_SEQNO GENMASK(15, 8)
148 #define MT_TXS1_TX_POWER_DBM GENMASK(7, 0)
150 #define MT_TXS2_BF_STATUS GENMASK(31, 30)
151 #define MT_TXS2_LAST_TX_RATE GENMASK(29, 27)
153 #define MT_TXS2_WCID GENMASK(25, 16)
154 #define MT_TXS2_TX_DELAY GENMASK(15, 0)
156 #define MT_TXS3_PID GENMASK(31, 24)
157 #define MT_TXS3_ANT_ID GENMASK(23, 0)
159 #define MT_TXS4_TIMESTAMP GENMASK(31, 0)
162 #define MT_TXS5_MPDU_TX_BYTE GENMASK(22, 0)
163 #define MT_TXS5_MPDU_TX_CNT GENMASK(31, 23)
165 #define MT_TXS6_MPDU_FAIL_CNT GENMASK(31, 23)
167 #define MT_TXS7_MPDU_RETRY_CNT GENMASK(31, 23)
170 #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(9, 0)
176 #define MT_RXD1_NORMAL_SEC_MODE GENMASK(20, 16)
177 #define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21)
189 #define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
192 #define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)
194 #define MT_RXD2_NORMAL_HDR_OFFSET GENMASK(15, 14)
195 #define MT_RXD2_NORMAL_TID GENMASK(19, 16)
209 #define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0)
210 #define MT_RXD4_FIRST_AMSDU_FRAME GENMASK(1, 0)
215 #define MT_RXD4_NORMAL_OFLD GENMASK(12, 11)
217 #define MT_RXD4_NORMAL_WOL GENMASK(18, 14)
218 #define MT_RXD4_NORMAL_CLS_BITMAP GENMASK(28, 19)
220 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
225 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
226 #define MT_RXD3_NORMAL_CH_FREQ GENMASK(15, 8)
227 #define MT_RXD3_NORMAL_ADDR_TYPE GENMASK(17, 16)
245 #define MT_RXD6_FRAME_CONTROL GENMASK(15, 0)
246 #define MT_RXD6_TA_LO GENMASK(31, 16)
248 #define MT_RXD7_TA_HI GENMASK(31, 0)
250 #define MT_RXD8_SEQ_CTRL GENMASK(15, 0)
251 #define MT_RXD8_QOS_CTL GENMASK(31, 16)
253 #define MT_RXD9_HT_CONTROL GENMASK(31, 0)
256 #define MT_PRXV_TX_RATE GENMASK(6, 0)
259 #define MT_PRXV_NSTS GENMASK(9, 7)
262 #define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
264 #define MT_PRXV_FRAME_MODE GENMASK(14, 12)
265 #define MT_PRXV_HT_SGI GENMASK(16, 15)
266 #define MT_PRXV_HT_STBC GENMASK(23, 22)
267 #define MT_PRXV_TX_MODE GENMASK(27, 24)
272 #define MT_PRXV_RCPI3 GENMASK(31, 24)
273 #define MT_PRXV_RCPI2 GENMASK(23, 16)
274 #define MT_PRXV_RCPI1 GENMASK(15, 8)
275 #define MT_PRXV_RCPI0 GENMASK(7, 0)
276 #define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0)
279 #define MT_CRXV_HT_STBC GENMASK(1, 0)
280 #define MT_CRXV_TX_MODE GENMASK(7, 4)
281 #define MT_CRXV_FRAME_MODE GENMASK(10, 8)
282 #define MT_CRXV_HT_SHORT_GI GENMASK(14, 13)
283 #define MT_CRXV_HE_LTF_SIZE GENMASK(18, 17)
286 #define MT_CRXV_HE_NUM_USER GENMASK(30, 24)
289 #define MT_CRXV_HE_RU0 GENMASK(7, 0)
290 #define MT_CRXV_HE_RU1 GENMASK(15, 8)
291 #define MT_CRXV_HE_RU2 GENMASK(23, 16)
292 #define MT_CRXV_HE_RU3 GENMASK(31, 24)
294 #define MT_CRXV_HE_MU_AID GENMASK(30, 20)
296 #define MT_CRXV_HE_SR_MASK GENMASK(11, 8)
297 #define MT_CRXV_HE_SR1_MASK GENMASK(16, 12)
298 #define MT_CRXV_HE_SR2_MASK GENMASK(20, 17)
299 #define MT_CRXV_HE_SR3_MASK GENMASK(24, 21)
301 #define MT_CRXV_HE_BSS_COLOR GENMASK(5, 0)
302 #define MT_CRXV_HE_TXOP_DUR GENMASK(12, 6)
306 #define MT_CRXV_SNR GENMASK(18, 13)
307 #define MT_CRXV_FOE_LO GENMASK(31, 19)
308 #define MT_CRXV_FOE_HI GENMASK(6, 0)