Lines Matching refs:GENMASK
137 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
139 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
141 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(21, 16))
143 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
145 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(29, 24))
149 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
151 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
153 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
155 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
157 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
159 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
161 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
163 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
165 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
167 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
169 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
174 #define XCAP_MASK GENMASK(6, 0)
182 #define BIT_ANT_PATH GENMASK(1, 0)
185 #define BIT_EDCCA_OPTION GENMASK(30, 29)
190 #define BITS_SUBTUNE GENMASK(15, 12)
209 #define BIT_3WIRE_EN GENMASK(1, 0)
218 #define BITS_RXAGC_CCK GENMASK(15, 12)
219 #define BITS_RXAGC_OFDM GENMASK(8, 4)
226 #define BIT_BBMODE GENMASK(2, 1)
248 #define BIT_SEL_PATH GENMASK(2, 1)
249 #define BIT_SUBPAGE GENMASK(3, 0)
251 #define BIT_GS_PWSF GENMASK(27, 0)
257 #define BIT_TX_CFIR GENMASK(31, 30)
258 #define BIT_CFIR_EN GENMASK(26, 24)
263 #define BIT_GLOSS_DB GENMASK(14, 12)
268 #define BIT_I_GAIN GENMASK(19, 16)
270 #define BIT_Q_GAIN_SEL GENMASK(14, 12)
271 #define BIT_Q_GAIN GENMASK(11, 0)
273 #define BIT_GAPK_RPT_IDX GENMASK(11, 8)
279 #define BIT_IQ_SWITCH GENMASK(5, 0)
284 #define BIT_RPT_SEL GENMASK(20, 16)
285 #define BIT_DPD_CLK GENMASK(7, 4)
291 #define BIT_RPT_DGAIN GENMASK(27, 16)
292 #define BIT_GAPK_RPT0 GENMASK(3, 0)
293 #define BIT_GAPK_RPT1 GENMASK(7, 4)
294 #define BIT_GAPK_RPT2 GENMASK(11, 8)
295 #define BIT_GAPK_RPT3 GENMASK(15, 12)
296 #define BIT_GAPK_RPT4 GENMASK(19, 16)
297 #define BIT_GAPK_RPT5 GENMASK(23, 20)
298 #define BIT_GAPK_RPT6 GENMASK(27, 24)
299 #define BIT_GAPK_RPT7 GENMASK(31, 28)
319 #define BIT_CCA_ON_BY_PW GENMASK(11, 3)
325 #define BIT_ANTSEG GENMASK(3, 0)
329 #define BIT_STOP_TX GENMASK(3, 0)
340 #define BIT_RPT_CIP_STATUS GENMASK(7, 0)
356 #define BIT_RF_MODE GENMASK(19, 16)
357 #define BIT_RXAGC GENMASK(9, 5)
358 #define BIT_TXAGC GENMASK(4, 0)
362 #define BIT_BW_TXBB GENMASK(14, 12)
363 #define BIT_BW_RXBB GENMASK(11, 10)
366 #define BIT_BB_GAIN GENMASK(18, 14)
367 #define BIT_RF_GAIN GENMASK(4, 2)
369 #define BIT_GAIN_TXBB GENMASK(4, 0)
371 #define BIT_TX_MODE GENMASK(19, 8)
373 #define BIT_GAIN_TX_PAD_H GENMASK(11, 8)
374 #define BIT_GAIN_TX_PAD_L GENMASK(7, 4)
376 #define RF_PABIAS_2G_MASK GENMASK(15, 12)
377 #define RF_PABIAS_5G_MASK GENMASK(19, 16)
379 #define BIT_TXA_LB_ATT GENMASK(15, 14)
380 #define BIT_LB_SW GENMASK(13, 12)
381 #define BIT_LB_ATT GENMASK(4, 2)
385 #define BIT_RXA_MIX_GAIN GENMASK(4, 3)
397 #define RF_THEMAL_MASK GENMASK(19, 16)
399 #define PPG_2G_A_MASK GENMASK(3, 0)
400 #define PPG_2G_B_MASK GENMASK(7, 4)
404 #define PPG_PABIAS_MASK GENMASK(3, 0)
407 #define PPG_5G_MASK GENMASK(4, 0)