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Searched refs:rcc (Results 1 – 25 of 61) sorted by relevance

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/Linux-v5.4/arch/arm/boot/dts/
Dstm32mp157c.dtsi130 clocks = <&rcc TIM2_K>;
158 clocks = <&rcc TIM3_K>;
187 clocks = <&rcc TIM4_K>;
214 clocks = <&rcc TIM5_K>;
243 clocks = <&rcc TIM6_K>;
261 clocks = <&rcc TIM7_K>;
279 clocks = <&rcc TIM12_K>;
301 clocks = <&rcc TIM13_K>;
323 clocks = <&rcc TIM14_K>;
345 clocks = <&rcc LPTIM1_K>;
[all …]
Dstm32f746.dtsi45 #include <dt-bindings/mfd/stm32f7-rcc.h>
82 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
91 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
112 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
121 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
142 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
151 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
172 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
180 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
201 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
[all …]
Dstm32f429.dtsi50 #include <dt-bindings/mfd/stm32f4-rcc.h>
100 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
130 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
160 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
169 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
190 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
198 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
[all …]
Dstm32h743.dtsi45 #include <dt-bindings/mfd/stm32h7-rcc.h>
77 clocks = <&rcc TIM5_CK>;
85 clocks = <&rcc LPTIM1_CK>;
113 clocks = <&rcc SPI2_CK>;
124 clocks = <&rcc SPI3_CK>;
133 clocks = <&rcc USART2_CK>;
143 resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
144 clocks = <&rcc I2C1_CK>;
155 resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
156 clocks = <&rcc I2C2_CK>;
[all …]
Dstm32f7-pinctrl.dtsi8 #include <dt-bindings/mfd/stm32f7-rcc.h>
26 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
36 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
46 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
56 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
66 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
76 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
86 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
96 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
106 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
[all …]
Dstm32h743-pinctrl.dtsi60 clocks = <&rcc GPIOA_CK>;
70 clocks = <&rcc GPIOB_CK>;
80 clocks = <&rcc GPIOC_CK>;
90 clocks = <&rcc GPIOD_CK>;
100 clocks = <&rcc GPIOE_CK>;
110 clocks = <&rcc GPIOF_CK>;
120 clocks = <&rcc GPIOG_CK>;
130 clocks = <&rcc GPIOH_CK>;
140 clocks = <&rcc GPIOI_CK>;
150 clocks = <&rcc GPIOJ_CK>;
[all …]
Dstm32f4-pinctrl.dtsi44 #include <dt-bindings/mfd/stm32f4-rcc.h>
62 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
72 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
82 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
92 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
102 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
112 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
122 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
132 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
142 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
[all …]
Dstm32f469.dtsi12 resets = <&rcc STM32F4_APB2_RESET(DSI)>;
14 clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
Dstm32f769-disco.dts93 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
105 &rcc {
106 compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc";
Dstm32mp157-pinctrl.dtsi25 clocks = <&rcc GPIOA>;
36 clocks = <&rcc GPIOB>;
47 clocks = <&rcc GPIOC>;
58 clocks = <&rcc GPIOD>;
69 clocks = <&rcc GPIOE>;
80 clocks = <&rcc GPIOF>;
91 clocks = <&rcc GPIOG>;
102 clocks = <&rcc GPIOH>;
113 clocks = <&rcc GPIOI>;
124 clocks = <&rcc GPIOJ>;
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/clock/
Dst,stm32-rcc.txt11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
29 rcc: rcc@40023800 {
32 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
53 - include/dt-bindings/mfd/stm32f4-rcc.h
59 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
64 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
117 clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
[all …]
Dst,stm32h7-rcc.txt11 "st,stm32h743-rcc"
31 rcc: reset-clock-controller@58024400 {
32 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
50 clocks = <&rcc TIM5_CK>;
70 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
Dst,stm32mp1-rcc.txt15 - compatible: "st,stm32mp1-rcc", "syscon"
25 rcc: rcc@50000000 {
26 compatible = "st,stm32mp1-rcc", "syscon";
/Linux-v5.4/Documentation/devicetree/bindings/rtc/
Dst,stm32-rtc.txt33 clocks = <&rcc 1 CLK_RTC>;
34 assigned-clocks = <&rcc 1 CLK_RTC>;
35 assigned-clock-parents = <&rcc 1 CLK_LSE>;
44 clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
46 assigned-clocks = <&rcc RTC_CK>;
47 assigned-clock-parents = <&rcc LSE_CK>;
57 clocks = <&rcc RTCAPB>, <&rcc RTC>;
/Linux-v5.4/drivers/clk/qcom/
Dclk-rpm.c306 struct rpm_cc *rcc = r->rpm_cc; in clk_rpm_xo_prepare() local
310 mutex_lock(&rcc->xo_lock); in clk_rpm_xo_prepare()
312 value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset); in clk_rpm_xo_prepare()
316 rcc->xo_buffer_value = value; in clk_rpm_xo_prepare()
319 mutex_unlock(&rcc->xo_lock); in clk_rpm_xo_prepare()
327 struct rpm_cc *rcc = r->rpm_cc; in clk_rpm_xo_unprepare() local
331 mutex_lock(&rcc->xo_lock); in clk_rpm_xo_unprepare()
333 value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset); in clk_rpm_xo_unprepare()
337 rcc->xo_buffer_value = value; in clk_rpm_xo_unprepare()
340 mutex_unlock(&rcc->xo_lock); in clk_rpm_xo_unprepare()
[all …]
Dclk-smd-rpm.c725 struct rpm_cc *rcc = data; in qcom_smdrpm_clk_hw_get() local
728 if (idx >= rcc->num_clks) { in qcom_smdrpm_clk_hw_get()
733 return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT); in qcom_smdrpm_clk_hw_get()
738 struct rpm_cc *rcc; in rpm_smd_clk_probe() local
758 rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL); in rpm_smd_clk_probe()
759 if (!rcc) in rpm_smd_clk_probe()
762 rcc->clks = rpm_smd_clks; in rpm_smd_clk_probe()
763 rcc->num_clks = num_clks; in rpm_smd_clk_probe()
790 rcc); in rpm_smd_clk_probe()
/Linux-v5.4/Documentation/devicetree/bindings/display/
Dst,stm32-ltdc.txt63 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
64 clocks = <&rcc 1 CLK_LCD>;
85 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
86 clocks = <&rcc 1 CLK_LCD>;
102 clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
104 resets = <&rcc STM32F4_APB2_RESET(DSI)>;
/Linux-v5.4/Documentation/devicetree/bindings/sound/
Dst,stm32-i2s.txt40 clocks = <&rcc PCLK1>, <&rcc SPI2_CK>, <&rcc PLL1_Q>, <&rcc PLL2_P>;
Dst,stm32-sai.txt78 clocks = <&rcc SAI1_CK>, <&rcc PLL1_Q>, <&rcc PLL2_P>;
85 clocks = <&rcc SAI1_CK>;
/Linux-v5.4/Documentation/devicetree/bindings/i2c/
Di2c-stm32.txt47 resets = <&rcc 277>;
48 clocks = <&rcc 0 149>;
60 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
61 clocks = <&rcc 1 CLK_I2C1>;
/Linux-v5.4/Documentation/devicetree/bindings/crypto/
Dst,stm32-cryp.txt17 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(CRYP)>;
18 resets = <&rcc STM32F7_AHB2_RESET(CRYP)>;
Dst,stm32-hash.txt25 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(HASH)>;
26 resets = <&rcc STM32F7_AHB2_RESET(HASH)>;
/Linux-v5.4/Documentation/devicetree/bindings/media/
Dst,stm32-dcmi.txt8 see Documentation/devicetree/bindings/reset/st,stm32-rcc.txt
29 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
30 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
Dst,stm32-cec.txt17 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
/Linux-v5.4/Documentation/devicetree/bindings/net/
Dstm32-dwmac.txt39 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;

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