Lines Matching refs:rcc
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
100 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
130 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
160 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
169 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
190 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
198 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
228 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
243 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
252 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
268 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
290 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
306 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
320 clocks = <&rcc 1 CLK_RTC>;
322 assigned-clocks = <&rcc 1 CLK_RTC>;
323 assigned-clock-parents = <&rcc 1 CLK_LSE>;
345 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
355 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
363 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
371 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
382 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
390 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
399 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
400 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
409 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
410 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
435 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
443 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
452 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
474 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
495 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
506 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
514 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
526 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
538 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
550 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
563 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
576 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
586 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
608 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
630 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
646 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
663 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
673 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
686 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
687 clocks = <&rcc 1 CLK_LCD>;
695 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
699 rcc: rcc@40023810 { label
702 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
706 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
721 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
736 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
748 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
749 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
750 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
761 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
770 clocks = <&rcc 0 39>;
779 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
780 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
793 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
800 clocks = <&rcc 1 SYSTICK>;