Lines Matching refs:rcc
130 clocks = <&rcc TIM2_K>;
158 clocks = <&rcc TIM3_K>;
187 clocks = <&rcc TIM4_K>;
214 clocks = <&rcc TIM5_K>;
243 clocks = <&rcc TIM6_K>;
261 clocks = <&rcc TIM7_K>;
279 clocks = <&rcc TIM12_K>;
301 clocks = <&rcc TIM13_K>;
323 clocks = <&rcc TIM14_K>;
345 clocks = <&rcc LPTIM1_K>;
373 clocks = <&rcc SPI2_K>;
374 resets = <&rcc SPI2_R>;
398 clocks = <&rcc SPI3_K>;
399 resets = <&rcc SPI3_R>;
421 clocks = <&rcc SPDIF_K>;
434 clocks = <&rcc USART2_K>;
442 clocks = <&rcc USART3_K>;
450 clocks = <&rcc UART4_K>;
458 clocks = <&rcc UART5_K>;
468 clocks = <&rcc I2C1_K>;
469 resets = <&rcc I2C1_R>;
481 clocks = <&rcc I2C2_K>;
482 resets = <&rcc I2C2_R>;
494 clocks = <&rcc I2C3_K>;
495 resets = <&rcc I2C3_R>;
507 clocks = <&rcc I2C5_K>;
508 resets = <&rcc I2C5_R>;
518 clocks = <&rcc CEC_K>, <&clk_lse>;
526 clocks = <&rcc DAC12>;
551 clocks = <&rcc UART7_K>;
559 clocks = <&rcc UART8_K>;
568 clocks = <&rcc TIM1_K>;
599 clocks = <&rcc TIM8_K>;
629 clocks = <&rcc USART6_K>;
639 clocks = <&rcc SPI1_K>;
640 resets = <&rcc SPI1_R>;
664 clocks = <&rcc SPI4_K>;
665 resets = <&rcc SPI4_R>;
677 clocks = <&rcc TIM15_K>;
704 clocks = <&rcc TIM16_K>;
728 clocks = <&rcc TIM17_K>;
754 clocks = <&rcc SPI5_K>;
755 resets = <&rcc SPI5_R>;
769 resets = <&rcc SAI1_R>;
777 clocks = <&rcc SAI1_K>;
787 clocks = <&rcc SAI1_K>;
801 resets = <&rcc SAI2_R>;
808 clocks = <&rcc SAI2_K>;
818 clocks = <&rcc SAI2_K>;
832 resets = <&rcc SAI3_R>;
839 clocks = <&rcc SAI3_K>;
849 clocks = <&rcc SAI3_K>;
859 clocks = <&rcc DFSDM_K>;
933 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
946 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
963 clocks = <&rcc DMA1>;
980 clocks = <&rcc DMA2>;
993 clocks = <&rcc DMAMUX>;
1001 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1036 clocks = <&rcc USBO_K>;
1038 resets = <&rcc USBO_R>;
1058 clocks = <&rcc IPCC>;
1067 resets = <&rcc CAMITF_R>;
1068 clocks = <&rcc DCMI>;
1075 rcc: rcc@50000000 { label
1076 compatible = "st,stm32mp1-rcc", "syscon";
1092 clocks = <&rcc SYSCFG>;
1100 clocks = <&rcc LPTIM2_K>;
1127 clocks = <&rcc LPTIM3_K>;
1147 clocks = <&rcc LPTIM4_K>;
1161 clocks = <&rcc LPTIM5_K>;
1177 clocks = <&rcc VREF>;
1188 resets = <&rcc SAI4_R>;
1195 clocks = <&rcc SAI4_K>;
1205 clocks = <&rcc SAI4_K>;
1216 clocks = <&rcc TMPSENS>;
1226 clocks = <&rcc CRYP1>;
1227 resets = <&rcc CRYP1_R>;
1235 clocks = <&rcc HASH1>;
1236 resets = <&rcc HASH1_R>;
1246 clocks = <&rcc RNG1_K>;
1247 resets = <&rcc RNG1_R>;
1255 clocks = <&rcc MDMA>;
1275 clocks = <&rcc FMC_K>;
1276 resets = <&rcc FMC_R>;
1288 clocks = <&rcc QSPI_K>;
1289 resets = <&rcc QSPI_R>;
1299 clocks = <&rcc SDMMC1_K>;
1301 resets = <&rcc SDMMC1_R>;
1310 clocks = <&rcc CRC1>;
1331 clocks = <&rcc ETHMAC>,
1332 <&rcc ETHTX>,
1333 <&rcc ETHRX>,
1334 <&rcc ETHSTP>,
1335 <&rcc SYSCFG>;
1347 clocks = <&rcc USBH>;
1348 resets = <&rcc USBH_R>;
1356 clocks = <&rcc USBH>;
1357 resets = <&rcc USBH_R>;
1367 clocks = <&rcc GPU>, <&rcc GPU_K>;
1369 resets = <&rcc GPU_R>;
1376 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
1378 resets = <&rcc DSI_R>;
1388 clocks = <&rcc LTDC_PX>;
1390 resets = <&rcc LTDC_R>;
1397 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1407 clocks = <&rcc USBPHY_K>;
1408 resets = <&rcc USBPHY_R>;
1426 clocks = <&rcc USART1_K>;
1436 clocks = <&rcc SPI6_K>;
1437 resets = <&rcc SPI6_R>;
1450 clocks = <&rcc I2C4_K>;
1451 resets = <&rcc I2C4_R>;
1460 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1485 clocks = <&rcc I2C6_K>;
1486 resets = <&rcc I2C6_R>;
1506 resets = <&rcc MCU_R>;
1507 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1508 st,syscfg-tz = <&rcc 0x000 0x1>;