1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp1-clks.h>
8#include <dt-bindings/reset/stm32mp1-resets.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-a7";
20			device_type = "cpu";
21			reg = <0>;
22		};
23
24		cpu1: cpu@1 {
25			compatible = "arm,cortex-a7";
26			device_type = "cpu";
27			reg = <1>;
28		};
29	};
30
31	psci {
32		compatible = "arm,psci";
33		method = "smc";
34		cpu_off = <0x84000002>;
35		cpu_on = <0x84000003>;
36	};
37
38	intc: interrupt-controller@a0021000 {
39		compatible = "arm,cortex-a7-gic";
40		#interrupt-cells = <3>;
41		interrupt-controller;
42		reg = <0xa0021000 0x1000>,
43		      <0xa0022000 0x2000>;
44	};
45
46	timer {
47		compatible = "arm,armv7-timer";
48		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
49			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
50			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
51			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
52		interrupt-parent = <&intc>;
53	};
54
55	clocks {
56		clk_hse: clk-hse {
57			#clock-cells = <0>;
58			compatible = "fixed-clock";
59			clock-frequency = <24000000>;
60		};
61
62		clk_hsi: clk-hsi {
63			#clock-cells = <0>;
64			compatible = "fixed-clock";
65			clock-frequency = <64000000>;
66		};
67
68		clk_lse: clk-lse {
69			#clock-cells = <0>;
70			compatible = "fixed-clock";
71			clock-frequency = <32768>;
72		};
73
74		clk_lsi: clk-lsi {
75			#clock-cells = <0>;
76			compatible = "fixed-clock";
77			clock-frequency = <32000>;
78		};
79
80		clk_csi: clk-csi {
81			#clock-cells = <0>;
82			compatible = "fixed-clock";
83			clock-frequency = <4000000>;
84		};
85	};
86
87	thermal-zones {
88		cpu_thermal: cpu-thermal {
89			polling-delay-passive = <0>;
90			polling-delay = <0>;
91			thermal-sensors = <&dts>;
92
93			trips {
94				cpu_alert1: cpu-alert1 {
95					temperature = <85000>;
96					hysteresis = <0>;
97					type = "passive";
98				};
99
100				cpu-crit {
101					temperature = <120000>;
102					hysteresis = <0>;
103					type = "critical";
104				};
105			};
106
107			cooling-maps {
108			};
109		};
110	};
111
112	booster: regulator-booster {
113		compatible = "st,stm32mp1-booster";
114		st,syscfg = <&syscfg>;
115		status = "disabled";
116	};
117
118	soc {
119		compatible = "simple-bus";
120		#address-cells = <1>;
121		#size-cells = <1>;
122		interrupt-parent = <&intc>;
123		ranges;
124
125		timers2: timer@40000000 {
126			#address-cells = <1>;
127			#size-cells = <0>;
128			compatible = "st,stm32-timers";
129			reg = <0x40000000 0x400>;
130			clocks = <&rcc TIM2_K>;
131			clock-names = "int";
132			dmas = <&dmamux1 18 0x400 0x1>,
133			       <&dmamux1 19 0x400 0x1>,
134			       <&dmamux1 20 0x400 0x1>,
135			       <&dmamux1 21 0x400 0x1>,
136			       <&dmamux1 22 0x400 0x1>;
137			dma-names = "ch1", "ch2", "ch3", "ch4", "up";
138			status = "disabled";
139
140			pwm {
141				compatible = "st,stm32-pwm";
142				#pwm-cells = <3>;
143				status = "disabled";
144			};
145
146			timer@1 {
147				compatible = "st,stm32h7-timer-trigger";
148				reg = <1>;
149				status = "disabled";
150			};
151		};
152
153		timers3: timer@40001000 {
154			#address-cells = <1>;
155			#size-cells = <0>;
156			compatible = "st,stm32-timers";
157			reg = <0x40001000 0x400>;
158			clocks = <&rcc TIM3_K>;
159			clock-names = "int";
160			dmas = <&dmamux1 23 0x400 0x1>,
161			       <&dmamux1 24 0x400 0x1>,
162			       <&dmamux1 25 0x400 0x1>,
163			       <&dmamux1 26 0x400 0x1>,
164			       <&dmamux1 27 0x400 0x1>,
165			       <&dmamux1 28 0x400 0x1>;
166			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
167			status = "disabled";
168
169			pwm {
170				compatible = "st,stm32-pwm";
171				#pwm-cells = <3>;
172				status = "disabled";
173			};
174
175			timer@2 {
176				compatible = "st,stm32h7-timer-trigger";
177				reg = <2>;
178				status = "disabled";
179			};
180		};
181
182		timers4: timer@40002000 {
183			#address-cells = <1>;
184			#size-cells = <0>;
185			compatible = "st,stm32-timers";
186			reg = <0x40002000 0x400>;
187			clocks = <&rcc TIM4_K>;
188			clock-names = "int";
189			dmas = <&dmamux1 29 0x400 0x1>,
190			       <&dmamux1 30 0x400 0x1>,
191			       <&dmamux1 31 0x400 0x1>,
192			       <&dmamux1 32 0x400 0x1>;
193			dma-names = "ch1", "ch2", "ch3", "ch4";
194			status = "disabled";
195
196			pwm {
197				compatible = "st,stm32-pwm";
198				#pwm-cells = <3>;
199				status = "disabled";
200			};
201
202			timer@3 {
203				compatible = "st,stm32h7-timer-trigger";
204				reg = <3>;
205				status = "disabled";
206			};
207		};
208
209		timers5: timer@40003000 {
210			#address-cells = <1>;
211			#size-cells = <0>;
212			compatible = "st,stm32-timers";
213			reg = <0x40003000 0x400>;
214			clocks = <&rcc TIM5_K>;
215			clock-names = "int";
216			dmas = <&dmamux1 55 0x400 0x1>,
217			       <&dmamux1 56 0x400 0x1>,
218			       <&dmamux1 57 0x400 0x1>,
219			       <&dmamux1 58 0x400 0x1>,
220			       <&dmamux1 59 0x400 0x1>,
221			       <&dmamux1 60 0x400 0x1>;
222			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
223			status = "disabled";
224
225			pwm {
226				compatible = "st,stm32-pwm";
227				#pwm-cells = <3>;
228				status = "disabled";
229			};
230
231			timer@4 {
232				compatible = "st,stm32h7-timer-trigger";
233				reg = <4>;
234				status = "disabled";
235			};
236		};
237
238		timers6: timer@40004000 {
239			#address-cells = <1>;
240			#size-cells = <0>;
241			compatible = "st,stm32-timers";
242			reg = <0x40004000 0x400>;
243			clocks = <&rcc TIM6_K>;
244			clock-names = "int";
245			dmas = <&dmamux1 69 0x400 0x1>;
246			dma-names = "up";
247			status = "disabled";
248
249			timer@5 {
250				compatible = "st,stm32h7-timer-trigger";
251				reg = <5>;
252				status = "disabled";
253			};
254		};
255
256		timers7: timer@40005000 {
257			#address-cells = <1>;
258			#size-cells = <0>;
259			compatible = "st,stm32-timers";
260			reg = <0x40005000 0x400>;
261			clocks = <&rcc TIM7_K>;
262			clock-names = "int";
263			dmas = <&dmamux1 70 0x400 0x1>;
264			dma-names = "up";
265			status = "disabled";
266
267			timer@6 {
268				compatible = "st,stm32h7-timer-trigger";
269				reg = <6>;
270				status = "disabled";
271			};
272		};
273
274		timers12: timer@40006000 {
275			#address-cells = <1>;
276			#size-cells = <0>;
277			compatible = "st,stm32-timers";
278			reg = <0x40006000 0x400>;
279			clocks = <&rcc TIM12_K>;
280			clock-names = "int";
281			status = "disabled";
282
283			pwm {
284				compatible = "st,stm32-pwm";
285				#pwm-cells = <3>;
286				status = "disabled";
287			};
288
289			timer@11 {
290				compatible = "st,stm32h7-timer-trigger";
291				reg = <11>;
292				status = "disabled";
293			};
294		};
295
296		timers13: timer@40007000 {
297			#address-cells = <1>;
298			#size-cells = <0>;
299			compatible = "st,stm32-timers";
300			reg = <0x40007000 0x400>;
301			clocks = <&rcc TIM13_K>;
302			clock-names = "int";
303			status = "disabled";
304
305			pwm {
306				compatible = "st,stm32-pwm";
307				#pwm-cells = <3>;
308				status = "disabled";
309			};
310
311			timer@12 {
312				compatible = "st,stm32h7-timer-trigger";
313				reg = <12>;
314				status = "disabled";
315			};
316		};
317
318		timers14: timer@40008000 {
319			#address-cells = <1>;
320			#size-cells = <0>;
321			compatible = "st,stm32-timers";
322			reg = <0x40008000 0x400>;
323			clocks = <&rcc TIM14_K>;
324			clock-names = "int";
325			status = "disabled";
326
327			pwm {
328				compatible = "st,stm32-pwm";
329				#pwm-cells = <3>;
330				status = "disabled";
331			};
332
333			timer@13 {
334				compatible = "st,stm32h7-timer-trigger";
335				reg = <13>;
336				status = "disabled";
337			};
338		};
339
340		lptimer1: timer@40009000 {
341			#address-cells = <1>;
342			#size-cells = <0>;
343			compatible = "st,stm32-lptimer";
344			reg = <0x40009000 0x400>;
345			clocks = <&rcc LPTIM1_K>;
346			clock-names = "mux";
347			status = "disabled";
348
349			pwm {
350				compatible = "st,stm32-pwm-lp";
351				#pwm-cells = <3>;
352				status = "disabled";
353			};
354
355			trigger@0 {
356				compatible = "st,stm32-lptimer-trigger";
357				reg = <0>;
358				status = "disabled";
359			};
360
361			counter {
362				compatible = "st,stm32-lptimer-counter";
363				status = "disabled";
364			};
365		};
366
367		spi2: spi@4000b000 {
368			#address-cells = <1>;
369			#size-cells = <0>;
370			compatible = "st,stm32h7-spi";
371			reg = <0x4000b000 0x400>;
372			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
373			clocks = <&rcc SPI2_K>;
374			resets = <&rcc SPI2_R>;
375			dmas = <&dmamux1 39 0x400 0x05>,
376			       <&dmamux1 40 0x400 0x05>;
377			dma-names = "rx", "tx";
378			status = "disabled";
379		};
380
381		i2s2: audio-controller@4000b000 {
382			compatible = "st,stm32h7-i2s";
383			#sound-dai-cells = <0>;
384			reg = <0x4000b000 0x400>;
385			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
386			dmas = <&dmamux1 39 0x400 0x01>,
387			       <&dmamux1 40 0x400 0x01>;
388			dma-names = "rx", "tx";
389			status = "disabled";
390		};
391
392		spi3: spi@4000c000 {
393			#address-cells = <1>;
394			#size-cells = <0>;
395			compatible = "st,stm32h7-spi";
396			reg = <0x4000c000 0x400>;
397			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
398			clocks = <&rcc SPI3_K>;
399			resets = <&rcc SPI3_R>;
400			dmas = <&dmamux1 61 0x400 0x05>,
401			       <&dmamux1 62 0x400 0x05>;
402			dma-names = "rx", "tx";
403			status = "disabled";
404		};
405
406		i2s3: audio-controller@4000c000 {
407			compatible = "st,stm32h7-i2s";
408			#sound-dai-cells = <0>;
409			reg = <0x4000c000 0x400>;
410			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
411			dmas = <&dmamux1 61 0x400 0x01>,
412			       <&dmamux1 62 0x400 0x01>;
413			dma-names = "rx", "tx";
414			status = "disabled";
415		};
416
417		spdifrx: audio-controller@4000d000 {
418			compatible = "st,stm32h7-spdifrx";
419			#sound-dai-cells = <0>;
420			reg = <0x4000d000 0x400>;
421			clocks = <&rcc SPDIF_K>;
422			clock-names = "kclk";
423			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
424			dmas = <&dmamux1 93 0x400 0x01>,
425			       <&dmamux1 94 0x400 0x01>;
426			dma-names = "rx", "rx-ctrl";
427			status = "disabled";
428		};
429
430		usart2: serial@4000e000 {
431			compatible = "st,stm32h7-uart";
432			reg = <0x4000e000 0x400>;
433			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
434			clocks = <&rcc USART2_K>;
435			status = "disabled";
436		};
437
438		usart3: serial@4000f000 {
439			compatible = "st,stm32h7-uart";
440			reg = <0x4000f000 0x400>;
441			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
442			clocks = <&rcc USART3_K>;
443			status = "disabled";
444		};
445
446		uart4: serial@40010000 {
447			compatible = "st,stm32h7-uart";
448			reg = <0x40010000 0x400>;
449			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
450			clocks = <&rcc UART4_K>;
451			status = "disabled";
452		};
453
454		uart5: serial@40011000 {
455			compatible = "st,stm32h7-uart";
456			reg = <0x40011000 0x400>;
457			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
458			clocks = <&rcc UART5_K>;
459			status = "disabled";
460		};
461
462		i2c1: i2c@40012000 {
463			compatible = "st,stm32f7-i2c";
464			reg = <0x40012000 0x400>;
465			interrupt-names = "event", "error";
466			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
467				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
468			clocks = <&rcc I2C1_K>;
469			resets = <&rcc I2C1_R>;
470			#address-cells = <1>;
471			#size-cells = <0>;
472			status = "disabled";
473		};
474
475		i2c2: i2c@40013000 {
476			compatible = "st,stm32f7-i2c";
477			reg = <0x40013000 0x400>;
478			interrupt-names = "event", "error";
479			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
480				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
481			clocks = <&rcc I2C2_K>;
482			resets = <&rcc I2C2_R>;
483			#address-cells = <1>;
484			#size-cells = <0>;
485			status = "disabled";
486		};
487
488		i2c3: i2c@40014000 {
489			compatible = "st,stm32f7-i2c";
490			reg = <0x40014000 0x400>;
491			interrupt-names = "event", "error";
492			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
493				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
494			clocks = <&rcc I2C3_K>;
495			resets = <&rcc I2C3_R>;
496			#address-cells = <1>;
497			#size-cells = <0>;
498			status = "disabled";
499		};
500
501		i2c5: i2c@40015000 {
502			compatible = "st,stm32f7-i2c";
503			reg = <0x40015000 0x400>;
504			interrupt-names = "event", "error";
505			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
506				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
507			clocks = <&rcc I2C5_K>;
508			resets = <&rcc I2C5_R>;
509			#address-cells = <1>;
510			#size-cells = <0>;
511			status = "disabled";
512		};
513
514		cec: cec@40016000 {
515			compatible = "st,stm32-cec";
516			reg = <0x40016000 0x400>;
517			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
518			clocks = <&rcc CEC_K>, <&clk_lse>;
519			clock-names = "cec", "hdmi-cec";
520			status = "disabled";
521		};
522
523		dac: dac@40017000 {
524			compatible = "st,stm32h7-dac-core";
525			reg = <0x40017000 0x400>;
526			clocks = <&rcc DAC12>;
527			clock-names = "pclk";
528			#address-cells = <1>;
529			#size-cells = <0>;
530			status = "disabled";
531
532			dac1: dac@1 {
533				compatible = "st,stm32-dac";
534				#io-channels-cells = <1>;
535				reg = <1>;
536				status = "disabled";
537			};
538
539			dac2: dac@2 {
540				compatible = "st,stm32-dac";
541				#io-channels-cells = <1>;
542				reg = <2>;
543				status = "disabled";
544			};
545		};
546
547		uart7: serial@40018000 {
548			compatible = "st,stm32h7-uart";
549			reg = <0x40018000 0x400>;
550			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
551			clocks = <&rcc UART7_K>;
552			status = "disabled";
553		};
554
555		uart8: serial@40019000 {
556			compatible = "st,stm32h7-uart";
557			reg = <0x40019000 0x400>;
558			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
559			clocks = <&rcc UART8_K>;
560			status = "disabled";
561		};
562
563		timers1: timer@44000000 {
564			#address-cells = <1>;
565			#size-cells = <0>;
566			compatible = "st,stm32-timers";
567			reg = <0x44000000 0x400>;
568			clocks = <&rcc TIM1_K>;
569			clock-names = "int";
570			dmas = <&dmamux1 11 0x400 0x1>,
571			       <&dmamux1 12 0x400 0x1>,
572			       <&dmamux1 13 0x400 0x1>,
573			       <&dmamux1 14 0x400 0x1>,
574			       <&dmamux1 15 0x400 0x1>,
575			       <&dmamux1 16 0x400 0x1>,
576			       <&dmamux1 17 0x400 0x1>;
577			dma-names = "ch1", "ch2", "ch3", "ch4",
578				    "up", "trig", "com";
579			status = "disabled";
580
581			pwm {
582				compatible = "st,stm32-pwm";
583				#pwm-cells = <3>;
584				status = "disabled";
585			};
586
587			timer@0 {
588				compatible = "st,stm32h7-timer-trigger";
589				reg = <0>;
590				status = "disabled";
591			};
592		};
593
594		timers8: timer@44001000 {
595			#address-cells = <1>;
596			#size-cells = <0>;
597			compatible = "st,stm32-timers";
598			reg = <0x44001000 0x400>;
599			clocks = <&rcc TIM8_K>;
600			clock-names = "int";
601			dmas = <&dmamux1 47 0x400 0x1>,
602			       <&dmamux1 48 0x400 0x1>,
603			       <&dmamux1 49 0x400 0x1>,
604			       <&dmamux1 50 0x400 0x1>,
605			       <&dmamux1 51 0x400 0x1>,
606			       <&dmamux1 52 0x400 0x1>,
607			       <&dmamux1 53 0x400 0x1>;
608			dma-names = "ch1", "ch2", "ch3", "ch4",
609				    "up", "trig", "com";
610			status = "disabled";
611
612			pwm {
613				compatible = "st,stm32-pwm";
614				#pwm-cells = <3>;
615				status = "disabled";
616			};
617
618			timer@7 {
619				compatible = "st,stm32h7-timer-trigger";
620				reg = <7>;
621				status = "disabled";
622			};
623		};
624
625		usart6: serial@44003000 {
626			compatible = "st,stm32h7-uart";
627			reg = <0x44003000 0x400>;
628			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
629			clocks = <&rcc USART6_K>;
630			status = "disabled";
631		};
632
633		spi1: spi@44004000 {
634			#address-cells = <1>;
635			#size-cells = <0>;
636			compatible = "st,stm32h7-spi";
637			reg = <0x44004000 0x400>;
638			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
639			clocks = <&rcc SPI1_K>;
640			resets = <&rcc SPI1_R>;
641			dmas = <&dmamux1 37 0x400 0x05>,
642			       <&dmamux1 38 0x400 0x05>;
643			dma-names = "rx", "tx";
644			status = "disabled";
645		};
646
647		i2s1: audio-controller@44004000 {
648			compatible = "st,stm32h7-i2s";
649			#sound-dai-cells = <0>;
650			reg = <0x44004000 0x400>;
651			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
652			dmas = <&dmamux1 37 0x400 0x01>,
653			       <&dmamux1 38 0x400 0x01>;
654			dma-names = "rx", "tx";
655			status = "disabled";
656		};
657
658		spi4: spi@44005000 {
659			#address-cells = <1>;
660			#size-cells = <0>;
661			compatible = "st,stm32h7-spi";
662			reg = <0x44005000 0x400>;
663			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
664			clocks = <&rcc SPI4_K>;
665			resets = <&rcc SPI4_R>;
666			dmas = <&dmamux1 83 0x400 0x05>,
667			       <&dmamux1 84 0x400 0x05>;
668			dma-names = "rx", "tx";
669			status = "disabled";
670		};
671
672		timers15: timer@44006000 {
673			#address-cells = <1>;
674			#size-cells = <0>;
675			compatible = "st,stm32-timers";
676			reg = <0x44006000 0x400>;
677			clocks = <&rcc TIM15_K>;
678			clock-names = "int";
679			dmas = <&dmamux1 105 0x400 0x1>,
680			       <&dmamux1 106 0x400 0x1>,
681			       <&dmamux1 107 0x400 0x1>,
682			       <&dmamux1 108 0x400 0x1>;
683			dma-names = "ch1", "up", "trig", "com";
684			status = "disabled";
685
686			pwm {
687				compatible = "st,stm32-pwm";
688				#pwm-cells = <3>;
689				status = "disabled";
690			};
691
692			timer@14 {
693				compatible = "st,stm32h7-timer-trigger";
694				reg = <14>;
695				status = "disabled";
696			};
697		};
698
699		timers16: timer@44007000 {
700			#address-cells = <1>;
701			#size-cells = <0>;
702			compatible = "st,stm32-timers";
703			reg = <0x44007000 0x400>;
704			clocks = <&rcc TIM16_K>;
705			clock-names = "int";
706			dmas = <&dmamux1 109 0x400 0x1>,
707			       <&dmamux1 110 0x400 0x1>;
708			dma-names = "ch1", "up";
709			status = "disabled";
710
711			pwm {
712				compatible = "st,stm32-pwm";
713				#pwm-cells = <3>;
714				status = "disabled";
715			};
716			timer@15 {
717				compatible = "st,stm32h7-timer-trigger";
718				reg = <15>;
719				status = "disabled";
720			};
721		};
722
723		timers17: timer@44008000 {
724			#address-cells = <1>;
725			#size-cells = <0>;
726			compatible = "st,stm32-timers";
727			reg = <0x44008000 0x400>;
728			clocks = <&rcc TIM17_K>;
729			clock-names = "int";
730			dmas = <&dmamux1 111 0x400 0x1>,
731			       <&dmamux1 112 0x400 0x1>;
732			dma-names = "ch1", "up";
733			status = "disabled";
734
735			pwm {
736				compatible = "st,stm32-pwm";
737				#pwm-cells = <3>;
738				status = "disabled";
739			};
740
741			timer@16 {
742				compatible = "st,stm32h7-timer-trigger";
743				reg = <16>;
744				status = "disabled";
745			};
746		};
747
748		spi5: spi@44009000 {
749			#address-cells = <1>;
750			#size-cells = <0>;
751			compatible = "st,stm32h7-spi";
752			reg = <0x44009000 0x400>;
753			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
754			clocks = <&rcc SPI5_K>;
755			resets = <&rcc SPI5_R>;
756			dmas = <&dmamux1 85 0x400 0x05>,
757			       <&dmamux1 86 0x400 0x05>;
758			dma-names = "rx", "tx";
759			status = "disabled";
760		};
761
762		sai1: sai@4400a000 {
763			compatible = "st,stm32h7-sai";
764			#address-cells = <1>;
765			#size-cells = <1>;
766			ranges = <0 0x4400a000 0x400>;
767			reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
768			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
769			resets = <&rcc SAI1_R>;
770			status = "disabled";
771
772			sai1a: audio-controller@4400a004 {
773				#sound-dai-cells = <0>;
774
775				compatible = "st,stm32-sai-sub-a";
776				reg = <0x4 0x1c>;
777				clocks = <&rcc SAI1_K>;
778				clock-names = "sai_ck";
779				dmas = <&dmamux1 87 0x400 0x01>;
780				status = "disabled";
781			};
782
783			sai1b: audio-controller@4400a024 {
784				#sound-dai-cells = <0>;
785				compatible = "st,stm32-sai-sub-b";
786				reg = <0x24 0x1c>;
787				clocks = <&rcc SAI1_K>;
788				clock-names = "sai_ck";
789				dmas = <&dmamux1 88 0x400 0x01>;
790				status = "disabled";
791			};
792		};
793
794		sai2: sai@4400b000 {
795			compatible = "st,stm32h7-sai";
796			#address-cells = <1>;
797			#size-cells = <1>;
798			ranges = <0 0x4400b000 0x400>;
799			reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
800			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
801			resets = <&rcc SAI2_R>;
802			status = "disabled";
803
804			sai2a: audio-controller@4400b004 {
805				#sound-dai-cells = <0>;
806				compatible = "st,stm32-sai-sub-a";
807				reg = <0x4 0x1c>;
808				clocks = <&rcc SAI2_K>;
809				clock-names = "sai_ck";
810				dmas = <&dmamux1 89 0x400 0x01>;
811				status = "disabled";
812			};
813
814			sai2b: audio-controller@4400b024 {
815				#sound-dai-cells = <0>;
816				compatible = "st,stm32-sai-sub-b";
817				reg = <0x24 0x1c>;
818				clocks = <&rcc SAI2_K>;
819				clock-names = "sai_ck";
820				dmas = <&dmamux1 90 0x400 0x01>;
821				status = "disabled";
822			};
823		};
824
825		sai3: sai@4400c000 {
826			compatible = "st,stm32h7-sai";
827			#address-cells = <1>;
828			#size-cells = <1>;
829			ranges = <0 0x4400c000 0x400>;
830			reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
831			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
832			resets = <&rcc SAI3_R>;
833			status = "disabled";
834
835			sai3a: audio-controller@4400c004 {
836				#sound-dai-cells = <0>;
837				compatible = "st,stm32-sai-sub-a";
838				reg = <0x04 0x1c>;
839				clocks = <&rcc SAI3_K>;
840				clock-names = "sai_ck";
841				dmas = <&dmamux1 113 0x400 0x01>;
842				status = "disabled";
843			};
844
845			sai3b: audio-controller@4400c024 {
846				#sound-dai-cells = <0>;
847				compatible = "st,stm32-sai-sub-b";
848				reg = <0x24 0x1c>;
849				clocks = <&rcc SAI3_K>;
850				clock-names = "sai_ck";
851				dmas = <&dmamux1 114 0x400 0x01>;
852				status = "disabled";
853			};
854		};
855
856		dfsdm: dfsdm@4400d000 {
857			compatible = "st,stm32mp1-dfsdm";
858			reg = <0x4400d000 0x800>;
859			clocks = <&rcc DFSDM_K>;
860			clock-names = "dfsdm";
861			#address-cells = <1>;
862			#size-cells = <0>;
863			status = "disabled";
864
865			dfsdm0: filter@0 {
866				compatible = "st,stm32-dfsdm-adc";
867				#io-channel-cells = <1>;
868				reg = <0>;
869				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
870				dmas = <&dmamux1 101 0x400 0x01>;
871				dma-names = "rx";
872				status = "disabled";
873			};
874
875			dfsdm1: filter@1 {
876				compatible = "st,stm32-dfsdm-adc";
877				#io-channel-cells = <1>;
878				reg = <1>;
879				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
880				dmas = <&dmamux1 102 0x400 0x01>;
881				dma-names = "rx";
882				status = "disabled";
883			};
884
885			dfsdm2: filter@2 {
886				compatible = "st,stm32-dfsdm-adc";
887				#io-channel-cells = <1>;
888				reg = <2>;
889				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
890				dmas = <&dmamux1 103 0x400 0x01>;
891				dma-names = "rx";
892				status = "disabled";
893			};
894
895			dfsdm3: filter@3 {
896				compatible = "st,stm32-dfsdm-adc";
897				#io-channel-cells = <1>;
898				reg = <3>;
899				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
900				dmas = <&dmamux1 104 0x400 0x01>;
901				dma-names = "rx";
902				status = "disabled";
903			};
904
905			dfsdm4: filter@4 {
906				compatible = "st,stm32-dfsdm-adc";
907				#io-channel-cells = <1>;
908				reg = <4>;
909				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
910				dmas = <&dmamux1 91 0x400 0x01>;
911				dma-names = "rx";
912				status = "disabled";
913			};
914
915			dfsdm5: filter@5 {
916				compatible = "st,stm32-dfsdm-adc";
917				#io-channel-cells = <1>;
918				reg = <5>;
919				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
920				dmas = <&dmamux1 92 0x400 0x01>;
921				dma-names = "rx";
922				status = "disabled";
923			};
924		};
925
926		m_can1: can@4400e000 {
927			compatible = "bosch,m_can";
928			reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
929			reg-names = "m_can", "message_ram";
930			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
931				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
932			interrupt-names = "int0", "int1";
933			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
934			clock-names = "hclk", "cclk";
935			bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
936			status = "disabled";
937		};
938
939		m_can2: can@4400f000 {
940			compatible = "bosch,m_can";
941			reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
942			reg-names = "m_can", "message_ram";
943			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
944				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
945			interrupt-names = "int0", "int1";
946			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
947			clock-names = "hclk", "cclk";
948			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
949			status = "disabled";
950		};
951
952		dma1: dma@48000000 {
953			compatible = "st,stm32-dma";
954			reg = <0x48000000 0x400>;
955			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
956				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
957				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
958				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
959				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
960				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
961				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
962				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
963			clocks = <&rcc DMA1>;
964			#dma-cells = <4>;
965			st,mem2mem;
966			dma-requests = <8>;
967		};
968
969		dma2: dma@48001000 {
970			compatible = "st,stm32-dma";
971			reg = <0x48001000 0x400>;
972			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
973				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
974				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
975				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
976				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
977				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
978				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
979				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
980			clocks = <&rcc DMA2>;
981			#dma-cells = <4>;
982			st,mem2mem;
983			dma-requests = <8>;
984		};
985
986		dmamux1: dma-router@48002000 {
987			compatible = "st,stm32h7-dmamux";
988			reg = <0x48002000 0x1c>;
989			#dma-cells = <3>;
990			dma-requests = <128>;
991			dma-masters = <&dma1 &dma2>;
992			dma-channels = <16>;
993			clocks = <&rcc DMAMUX>;
994		};
995
996		adc: adc@48003000 {
997			compatible = "st,stm32mp1-adc-core";
998			reg = <0x48003000 0x400>;
999			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1000				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1001			clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1002			clock-names = "bus", "adc";
1003			interrupt-controller;
1004			st,syscfg = <&syscfg>;
1005			#interrupt-cells = <1>;
1006			#address-cells = <1>;
1007			#size-cells = <0>;
1008			status = "disabled";
1009
1010			adc1: adc@0 {
1011				compatible = "st,stm32mp1-adc";
1012				#io-channel-cells = <1>;
1013				reg = <0x0>;
1014				interrupt-parent = <&adc>;
1015				interrupts = <0>;
1016				dmas = <&dmamux1 9 0x400 0x01>;
1017				dma-names = "rx";
1018				status = "disabled";
1019			};
1020
1021			adc2: adc@100 {
1022				compatible = "st,stm32mp1-adc";
1023				#io-channel-cells = <1>;
1024				reg = <0x100>;
1025				interrupt-parent = <&adc>;
1026				interrupts = <1>;
1027				dmas = <&dmamux1 10 0x400 0x01>;
1028				dma-names = "rx";
1029				status = "disabled";
1030			};
1031		};
1032
1033		usbotg_hs: usb-otg@49000000 {
1034			compatible = "snps,dwc2";
1035			reg = <0x49000000 0x10000>;
1036			clocks = <&rcc USBO_K>;
1037			clock-names = "otg";
1038			resets = <&rcc USBO_R>;
1039			reset-names = "dwc2";
1040			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1041			g-rx-fifo-size = <256>;
1042			g-np-tx-fifo-size = <32>;
1043			g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
1044			dr_mode = "otg";
1045			status = "disabled";
1046		};
1047
1048		ipcc: mailbox@4c001000 {
1049			compatible = "st,stm32mp1-ipcc";
1050			#mbox-cells = <1>;
1051			reg = <0x4c001000 0x400>;
1052			st,proc-id = <0>;
1053			interrupts-extended =
1054				<&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1055				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1056				<&exti 61 1>;
1057			interrupt-names = "rx", "tx", "wakeup";
1058			clocks = <&rcc IPCC>;
1059			wakeup-source;
1060			status = "disabled";
1061		};
1062
1063		dcmi: dcmi@4c006000 {
1064			compatible = "st,stm32-dcmi";
1065			reg = <0x4c006000 0x400>;
1066			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1067			resets = <&rcc CAMITF_R>;
1068			clocks = <&rcc DCMI>;
1069			clock-names = "mclk";
1070			dmas = <&dmamux1 75 0x400 0x0d>;
1071			dma-names = "tx";
1072			status = "disabled";
1073		};
1074
1075		rcc: rcc@50000000 {
1076			compatible = "st,stm32mp1-rcc", "syscon";
1077			reg = <0x50000000 0x1000>;
1078			#clock-cells = <1>;
1079			#reset-cells = <1>;
1080		};
1081
1082		exti: interrupt-controller@5000d000 {
1083			compatible = "st,stm32mp1-exti", "syscon";
1084			interrupt-controller;
1085			#interrupt-cells = <2>;
1086			reg = <0x5000d000 0x400>;
1087		};
1088
1089		syscfg: syscon@50020000 {
1090			compatible = "st,stm32mp157-syscfg", "syscon";
1091			reg = <0x50020000 0x400>;
1092			clocks = <&rcc SYSCFG>;
1093		};
1094
1095		lptimer2: timer@50021000 {
1096			#address-cells = <1>;
1097			#size-cells = <0>;
1098			compatible = "st,stm32-lptimer";
1099			reg = <0x50021000 0x400>;
1100			clocks = <&rcc LPTIM2_K>;
1101			clock-names = "mux";
1102			status = "disabled";
1103
1104			pwm {
1105				compatible = "st,stm32-pwm-lp";
1106				#pwm-cells = <3>;
1107				status = "disabled";
1108			};
1109
1110			trigger@1 {
1111				compatible = "st,stm32-lptimer-trigger";
1112				reg = <1>;
1113				status = "disabled";
1114			};
1115
1116			counter {
1117				compatible = "st,stm32-lptimer-counter";
1118				status = "disabled";
1119			};
1120		};
1121
1122		lptimer3: timer@50022000 {
1123			#address-cells = <1>;
1124			#size-cells = <0>;
1125			compatible = "st,stm32-lptimer";
1126			reg = <0x50022000 0x400>;
1127			clocks = <&rcc LPTIM3_K>;
1128			clock-names = "mux";
1129			status = "disabled";
1130
1131			pwm {
1132				compatible = "st,stm32-pwm-lp";
1133				#pwm-cells = <3>;
1134				status = "disabled";
1135			};
1136
1137			trigger@2 {
1138				compatible = "st,stm32-lptimer-trigger";
1139				reg = <2>;
1140				status = "disabled";
1141			};
1142		};
1143
1144		lptimer4: timer@50023000 {
1145			compatible = "st,stm32-lptimer";
1146			reg = <0x50023000 0x400>;
1147			clocks = <&rcc LPTIM4_K>;
1148			clock-names = "mux";
1149			status = "disabled";
1150
1151			pwm {
1152				compatible = "st,stm32-pwm-lp";
1153				#pwm-cells = <3>;
1154				status = "disabled";
1155			};
1156		};
1157
1158		lptimer5: timer@50024000 {
1159			compatible = "st,stm32-lptimer";
1160			reg = <0x50024000 0x400>;
1161			clocks = <&rcc LPTIM5_K>;
1162			clock-names = "mux";
1163			status = "disabled";
1164
1165			pwm {
1166				compatible = "st,stm32-pwm-lp";
1167				#pwm-cells = <3>;
1168				status = "disabled";
1169			};
1170		};
1171
1172		vrefbuf: vrefbuf@50025000 {
1173			compatible = "st,stm32-vrefbuf";
1174			reg = <0x50025000 0x8>;
1175			regulator-min-microvolt = <1500000>;
1176			regulator-max-microvolt = <2500000>;
1177			clocks = <&rcc VREF>;
1178			status = "disabled";
1179		};
1180
1181		sai4: sai@50027000 {
1182			compatible = "st,stm32h7-sai";
1183			#address-cells = <1>;
1184			#size-cells = <1>;
1185			ranges = <0 0x50027000 0x400>;
1186			reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1187			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1188			resets = <&rcc SAI4_R>;
1189			status = "disabled";
1190
1191			sai4a: audio-controller@50027004 {
1192				#sound-dai-cells = <0>;
1193				compatible = "st,stm32-sai-sub-a";
1194				reg = <0x04 0x1c>;
1195				clocks = <&rcc SAI4_K>;
1196				clock-names = "sai_ck";
1197				dmas = <&dmamux1 99 0x400 0x01>;
1198				status = "disabled";
1199			};
1200
1201			sai4b: audio-controller@50027024 {
1202				#sound-dai-cells = <0>;
1203				compatible = "st,stm32-sai-sub-b";
1204				reg = <0x24 0x1c>;
1205				clocks = <&rcc SAI4_K>;
1206				clock-names = "sai_ck";
1207				dmas = <&dmamux1 100 0x400 0x01>;
1208				status = "disabled";
1209			};
1210		};
1211
1212		dts: thermal@50028000 {
1213			compatible = "st,stm32-thermal";
1214			reg = <0x50028000 0x100>;
1215			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1216			clocks = <&rcc TMPSENS>;
1217			clock-names = "pclk";
1218			#thermal-sensor-cells = <0>;
1219			status = "disabled";
1220		};
1221
1222		cryp1: cryp@54001000 {
1223			compatible = "st,stm32mp1-cryp";
1224			reg = <0x54001000 0x400>;
1225			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1226			clocks = <&rcc CRYP1>;
1227			resets = <&rcc CRYP1_R>;
1228			status = "disabled";
1229		};
1230
1231		hash1: hash@54002000 {
1232			compatible = "st,stm32f756-hash";
1233			reg = <0x54002000 0x400>;
1234			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1235			clocks = <&rcc HASH1>;
1236			resets = <&rcc HASH1_R>;
1237			dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1238			dma-names = "in";
1239			dma-maxburst = <2>;
1240			status = "disabled";
1241		};
1242
1243		rng1: rng@54003000 {
1244			compatible = "st,stm32-rng";
1245			reg = <0x54003000 0x400>;
1246			clocks = <&rcc RNG1_K>;
1247			resets = <&rcc RNG1_R>;
1248			status = "disabled";
1249		};
1250
1251		mdma1: dma@58000000 {
1252			compatible = "st,stm32h7-mdma";
1253			reg = <0x58000000 0x1000>;
1254			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1255			clocks = <&rcc MDMA>;
1256			#dma-cells = <5>;
1257			dma-channels = <32>;
1258			dma-requests = <48>;
1259		};
1260
1261		fmc: nand-controller@58002000 {
1262			compatible = "st,stm32mp15-fmc2";
1263			reg = <0x58002000 0x1000>,
1264			      <0x80000000 0x1000>,
1265			      <0x88010000 0x1000>,
1266			      <0x88020000 0x1000>,
1267			      <0x81000000 0x1000>,
1268			      <0x89010000 0x1000>,
1269			      <0x89020000 0x1000>;
1270			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1271			dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
1272			       <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
1273			       <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
1274			dma-names = "tx", "rx", "ecc";
1275			clocks = <&rcc FMC_K>;
1276			resets = <&rcc FMC_R>;
1277			status = "disabled";
1278		};
1279
1280		qspi: spi@58003000 {
1281			compatible = "st,stm32f469-qspi";
1282			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1283			reg-names = "qspi", "qspi_mm";
1284			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1285			dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
1286			       <&mdma1 22 0x10 0x100008 0x0 0x0>;
1287			dma-names = "tx", "rx";
1288			clocks = <&rcc QSPI_K>;
1289			resets = <&rcc QSPI_R>;
1290			status = "disabled";
1291		};
1292
1293		sdmmc1: sdmmc@58005000 {
1294			compatible = "arm,pl18x", "arm,primecell";
1295			arm,primecell-periphid = <0x10153180>;
1296			reg = <0x58005000 0x1000>;
1297			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1298			interrupt-names	= "cmd_irq";
1299			clocks = <&rcc SDMMC1_K>;
1300			clock-names = "apb_pclk";
1301			resets = <&rcc SDMMC1_R>;
1302			cap-sd-highspeed;
1303			cap-mmc-highspeed;
1304			max-frequency = <120000000>;
1305		};
1306
1307		crc1: crc@58009000 {
1308			compatible = "st,stm32f7-crc";
1309			reg = <0x58009000 0x400>;
1310			clocks = <&rcc CRC1>;
1311			status = "disabled";
1312		};
1313
1314		stmmac_axi_config_0: stmmac-axi-config {
1315			snps,wr_osr_lmt = <0x7>;
1316			snps,rd_osr_lmt = <0x7>;
1317			snps,blen = <0 0 0 0 16 8 4>;
1318		};
1319
1320		ethernet0: ethernet@5800a000 {
1321			compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1322			reg = <0x5800a000 0x2000>;
1323			reg-names = "stmmaceth";
1324			interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1325			interrupt-names = "macirq";
1326			clock-names = "stmmaceth",
1327				      "mac-clk-tx",
1328				      "mac-clk-rx",
1329				      "ethstp",
1330				      "syscfg-clk";
1331			clocks = <&rcc ETHMAC>,
1332				 <&rcc ETHTX>,
1333				 <&rcc ETHRX>,
1334				 <&rcc ETHSTP>,
1335				 <&rcc SYSCFG>;
1336			st,syscon = <&syscfg 0x4>;
1337			snps,mixed-burst;
1338			snps,pbl = <2>;
1339			snps,axi-config = <&stmmac_axi_config_0>;
1340			snps,tso;
1341			status = "disabled";
1342		};
1343
1344		usbh_ohci: usbh-ohci@5800c000 {
1345			compatible = "generic-ohci";
1346			reg = <0x5800c000 0x1000>;
1347			clocks = <&rcc USBH>;
1348			resets = <&rcc USBH_R>;
1349			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1350			status = "disabled";
1351		};
1352
1353		usbh_ehci: usbh-ehci@5800d000 {
1354			compatible = "generic-ehci";
1355			reg = <0x5800d000 0x1000>;
1356			clocks = <&rcc USBH>;
1357			resets = <&rcc USBH_R>;
1358			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1359			companion = <&usbh_ohci>;
1360			status = "disabled";
1361		};
1362
1363		gpu: gpu@59000000 {
1364			compatible = "vivante,gc";
1365			reg = <0x59000000 0x800>;
1366			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1367			clocks = <&rcc GPU>, <&rcc GPU_K>;
1368			clock-names = "bus" ,"core";
1369			resets = <&rcc GPU_R>;
1370			status = "disabled";
1371		};
1372
1373		dsi: dsi@5a000000 {
1374			compatible = "st,stm32-dsi";
1375			reg = <0x5a000000 0x800>;
1376			clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
1377			clock-names = "pclk", "ref", "px_clk";
1378			resets = <&rcc DSI_R>;
1379			reset-names = "apb";
1380			status = "disabled";
1381		};
1382
1383		ltdc: display-controller@5a001000 {
1384			compatible = "st,stm32-ltdc";
1385			reg = <0x5a001000 0x400>;
1386			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1387				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1388			clocks = <&rcc LTDC_PX>;
1389			clock-names = "lcd";
1390			resets = <&rcc LTDC_R>;
1391			status = "disabled";
1392		};
1393
1394		iwdg2: watchdog@5a002000 {
1395			compatible = "st,stm32mp1-iwdg";
1396			reg = <0x5a002000 0x400>;
1397			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1398			clock-names = "pclk", "lsi";
1399			status = "disabled";
1400		};
1401
1402		usbphyc: usbphyc@5a006000 {
1403			#address-cells = <1>;
1404			#size-cells = <0>;
1405			compatible = "st,stm32mp1-usbphyc";
1406			reg = <0x5a006000 0x1000>;
1407			clocks = <&rcc USBPHY_K>;
1408			resets = <&rcc USBPHY_R>;
1409			status = "disabled";
1410
1411			usbphyc_port0: usb-phy@0 {
1412				#phy-cells = <0>;
1413				reg = <0>;
1414			};
1415
1416			usbphyc_port1: usb-phy@1 {
1417				#phy-cells = <1>;
1418				reg = <1>;
1419			};
1420		};
1421
1422		usart1: serial@5c000000 {
1423			compatible = "st,stm32h7-uart";
1424			reg = <0x5c000000 0x400>;
1425			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1426			clocks = <&rcc USART1_K>;
1427			status = "disabled";
1428		};
1429
1430		spi6: spi@5c001000 {
1431			#address-cells = <1>;
1432			#size-cells = <0>;
1433			compatible = "st,stm32h7-spi";
1434			reg = <0x5c001000 0x400>;
1435			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1436			clocks = <&rcc SPI6_K>;
1437			resets = <&rcc SPI6_R>;
1438			dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1439			       <&mdma1 35 0x0 0x40002 0x0 0x0>;
1440			dma-names = "rx", "tx";
1441			status = "disabled";
1442		};
1443
1444		i2c4: i2c@5c002000 {
1445			compatible = "st,stm32f7-i2c";
1446			reg = <0x5c002000 0x400>;
1447			interrupt-names = "event", "error";
1448			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1449				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1450			clocks = <&rcc I2C4_K>;
1451			resets = <&rcc I2C4_R>;
1452			#address-cells = <1>;
1453			#size-cells = <0>;
1454			status = "disabled";
1455		};
1456
1457		rtc: rtc@5c004000 {
1458			compatible = "st,stm32mp1-rtc";
1459			reg = <0x5c004000 0x400>;
1460			clocks = <&rcc RTCAPB>, <&rcc RTC>;
1461			clock-names = "pclk", "rtc_ck";
1462			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1463			status = "disabled";
1464		};
1465
1466		bsec: nvmem@5c005000 {
1467			compatible = "st,stm32mp15-bsec";
1468			reg = <0x5c005000 0x400>;
1469			#address-cells = <1>;
1470			#size-cells = <1>;
1471			ts_cal1: calib@5c {
1472				reg = <0x5c 0x2>;
1473			};
1474			ts_cal2: calib@5e {
1475				reg = <0x5e 0x2>;
1476			};
1477		};
1478
1479		i2c6: i2c@5c009000 {
1480			compatible = "st,stm32f7-i2c";
1481			reg = <0x5c009000 0x400>;
1482			interrupt-names = "event", "error";
1483			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1484				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1485			clocks = <&rcc I2C6_K>;
1486			resets = <&rcc I2C6_R>;
1487			#address-cells = <1>;
1488			#size-cells = <0>;
1489			status = "disabled";
1490		};
1491	};
1492
1493	mlahb {
1494		compatible = "simple-bus";
1495		#address-cells = <1>;
1496		#size-cells = <1>;
1497		dma-ranges = <0x00000000 0x38000000 0x10000>,
1498			     <0x10000000 0x10000000 0x60000>,
1499			     <0x30000000 0x30000000 0x60000>;
1500
1501		m4_rproc: m4@10000000 {
1502			compatible = "st,stm32mp1-m4";
1503			reg = <0x10000000 0x40000>,
1504			      <0x30000000 0x40000>,
1505			      <0x38000000 0x10000>;
1506			resets = <&rcc MCU_R>;
1507			st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1508			st,syscfg-tz = <&rcc 0x000 0x1>;
1509			status = "disabled";
1510		};
1511	};
1512};
1513