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/Linux-v6.1/Documentation/devicetree/bindings/spi/
Dmediatek,spi-mt65xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Bus controller for MediaTek ARM SoCs
10 - Leilk Liu <leilk.liu@mediatek.com>
13 - $ref: "/schemas/spi/spi-controller.yaml#"
18 - items:
19 - enum:
20 - mediatek,mt7629-spi
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Dnvidia,tegra114-spi.txt1 NVIDIA Tegra114 SPI controller.
4 - compatible : For Tegra114, must contain "nvidia,tegra114-spi".
5 Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
7 - reg: Should contain SPI registers location and length.
8 - interrupts: Should contain SPI interrupts.
9 - clock-names : Must include the following entries:
10 - spi
11 - resets : Must contain an entry for each entry in reset-names.
13 - reset-names : Must include the following entries:
14 - spi
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/Linux-v6.1/drivers/spi/
Dspi-ar934x.c1 // SPDX-License-Identifier: GPL-2.0
3 // SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
7 // Based on spi-mt7621.c:
9 // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
10 // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
12 #include <linux/clk.h>
18 #include <linux/spi/spi.h>
20 #define DRIVER_NAME "spi-ar934x"
46 struct clk *clk; member
52 int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1; in ar934x_spi_clk_div()
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Dspi-sifive.c1 // SPDX-License-Identifier: GPL-2.0
5 // SiFive SPI controller driver (master mode only)
10 #include <linux/clk.h>
15 #include <linux/spi/spi.h>
38 #define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
39 #define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
93 struct clk *clk; /* bus clock */ member
96 struct completion done; /* wake-up from interrupt */
99 static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value) in sifive_spi_write() argument
101 iowrite32(value, spi->regs + offset); in sifive_spi_write()
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Dspi-ath79.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
5 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
7 * This driver has been based on the spi-gpio.c:
17 #include <linux/spi/spi.h>
18 #include <linux/spi/spi-mem.h>
19 #include <linux/spi/spi_bitbang.h>
21 #include <linux/clk.h>
24 #define DRV_NAME "ath79-spi"
30 #define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
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Dspi-bcm63xx-hsspi.c2 * Broadcom BCM63XX High Speed SPI Controller driver
4 * Copyright 2000-2010 Broadcom Corporation
5 * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
13 #include <linux/clk.h>
17 #include <linux/dma-mapping.h>
20 #include <linux/spi/spi.h>
98 #define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
105 struct clk *clk; member
106 struct clk *pll_clk;
119 mutex_lock(&bs->bus_mutex); in bcm63xx_hsspi_set_cs()
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Dspi-mpc512x-psc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC512x PSC in SPI mode driver.
7 * Hongjun Chen <hong-jun.chen@freescale.com>
23 #include <linux/clk.h>
24 #include <linux/spi/spi.h>
39 switch (mps->type) { \
41 struct mpc52xx_psc __iomem *psc = mps->psc; \
42 __ret = &psc->regname; \
46 struct mpc5125_psc __iomem *psc = mps->psc; \
47 __ret = &psc->regname; \
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Dspi-microchip-core.c1 // SPDX-License-Identifier: (GPL-2.0)
3 * Microchip CoreSPI SPI controller driver
5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
12 #include <linux/clk.h>
21 #include <linux/spi/spi.h>
101 struct clk *clk; member
104 u32 clk_gen; /* divider for spi output clock generated by the controller */
112 static inline u32 mchp_corespi_read(struct mchp_corespi *spi, unsigned int reg) in mchp_corespi_read() argument
114 return readl(spi->regs + reg); in mchp_corespi_read()
117 static inline void mchp_corespi_write(struct mchp_corespi *spi, unsigned int reg, u32 val) in mchp_corespi_write() argument
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Dspi-s3c24xx.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2009 Simtec Electronics
13 #include <linux/clk.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/spi_bitbang.h>
20 #include <linux/spi/s3c24xx.h>
21 #include <linux/spi/s3c24xx-fiq.h>
26 #include "spi-s3c24xx-regs.h"
29 * struct s3c24xx_spi_devstate - per device data
68 struct clk *clk; member
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Dspi-meson-spifc.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Driver for Amlogic Meson SPI flash controller (SPIFC)
8 #include <linux/clk.h>
18 #include <linux/spi/spi.h>
56 #define USER_UC_MASK ((BIT(5) - 1) << 27)
70 * @master: the SPI master
72 * @clk: input clock of the built-in baud rate generator
78 struct clk *clk; member
90 * meson_spifc_wait_ready() - wait for the current operation to terminate
91 * @spifc: the Meson SPI device
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Dspi-dw-mmio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Memory-mapped interface driver for DW SPI Core
8 #include <linux/clk.h>
13 #include <linux/spi/spi.h>
24 #include "spi-dw.h"
30 struct clk *clk; member
31 struct clk *pclk;
57 * The Designware SPI controller (referred to as master in the documentation)
60 * the SPI boot controller registers. the final chip select is an OR gate
61 * between the Designware SPI controller and the SPI boot controller.
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Dspi-orion.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell Orion SPI controller driver
6 * Copyright (C) 2007-2008 Marvell Ltd.
14 #include <linux/spi/spi.h>
20 #include <linux/clk.h>
74 * have both is for managing the armada-370-spi case with old
96 struct clk *clk; member
97 struct clk *axi_clk;
111 return orion_spi->base + reg; in spi_reg()
136 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) in orion_spi_baudrate_set() argument
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Dspi-armada-3700.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell Armada-3700 SPI controller driver
8 * Author: Romain Perier <romain.perier@free-electrons.com>
11 #include <linux/clk.h>
23 #include <linux/spi/spi.h>
31 /* SPI Register Offest */
105 struct clk *clk; member
119 return readl(a3700_spi->base + offset); in spireg_read()
124 writel(data, a3700_spi->base + offset); in spireg_write()
172 /* RX during address reception uses 4-pin */ in a3700_spi_pin_mode_set()
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Dspi-at91-usart.c1 // SPDX-License-Identifier: GPL-2.0
3 // Driver for AT91 USART Controllers as SPI
9 #include <linux/clk.h>
12 #include <linux/dma-direction.h>
22 #include <linux/spi/spi.h>
70 readl_relaxed((port)->regs + US_##reg)
72 writel_relaxed((value), (port)->regs + US_##reg)
75 readb_relaxed((port)->regs + US_##reg)
77 writeb_relaxed((value), (port)->regs + US_##reg)
84 struct clk *clk; member
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Dspi-dw-bt1.c1 // SPDX-License-Identifier: GPL-2.0-only
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
12 #include <linux/clk.h>
24 #include <linux/spi/spi-mem.h>
25 #include <linux/spi/spi.h>
27 #include "spi-dw.h"
34 struct clk *clk; member
52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create()
54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create()
55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create()
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Dspi-st-ssc4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014 STMicroelectronics Limited
9 * SPI master mode controller driver, used in STMicroelectronics devices.
12 #include <linux/clk.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/spi_bitbang.h>
54 /* SSC SPI Controller */
56 struct clk *clk; member
59 /* SSC SPI current transaction */
74 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo()
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Dspi-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Freescale MXS SPI master driver
15 // Based on code from U-Boot bootloader by:
18 // Based on spi-stmp.c, which is:
28 #include <linux/dma-mapping.h>
31 #include <linux/clk.h>
39 #include <linux/spi/spi.h>
40 #include <linux/spi/mxs-spi.h>
41 #include <trace/events/spi.h>
43 #define DRIVER_NAME "mxs-spi"
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Dspi-bcm63xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Broadcom BCM63xx SPI controller support
5 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
10 #include <linux/clk.h>
16 #include <linux/spi/spi.h>
23 /* BCM 6338/6348 SPI core */
25 #define SPI_6348_CMD 0x00 /* 16-bits register */
34 #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
41 /* BCM 3368/6358/6262/6368 SPI core */
43 #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
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Dspi-jcore.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * J-Core SPI controller driver
5 * Copyright (C) 2012-2016 Smart Energy Instruments, Inc.
16 #include <linux/spi/spi.h>
17 #include <linux/clk.h>
52 } while (--timeout); in jcore_spi_wait()
54 return -EBUSY; in jcore_spi_wait()
59 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_program()
62 dev_err(hw->master->dev.parent, in jcore_spi_program()
65 writel(hw->cs_reg | hw->speed_reg, ctrl_reg); in jcore_spi_program()
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Dspi-mt7621.c1 // SPDX-License-Identifier: GPL-2.0
3 // spi-mt7621.c -- MediaTek MT7621 SPI controller driver
6 // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
7 // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
9 // Some parts are based on spi-orion.c:
11 // Copyright (C) 2007-2008 Marvell Ltd.
13 #include <linux/clk.h>
19 #include <linux/spi/spi.h>
21 #define DRIVER_NAME "spi-mt7621"
61 static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi) in spidev_to_mt7621_spi() argument
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Dspi-rb4xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI controller driver for the Mikrotik RB4xx boards
15 #include <linux/clk.h>
16 #include <linux/spi/spi.h>
19 #include <asm/mach-ath79/ar71xx_regs.h>
23 struct clk *clk; member
28 return __raw_readl(rbspi->base + reg); in rb4xx_read()
33 __raw_writel(value, rbspi->base + reg); in rb4xx_write()
52 for (i = 7; i >= 0; i--) in do_spi_byte()
81 static void rb4xx_set_cs(struct spi_device *spi, bool enable) in rb4xx_set_cs() argument
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/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
24 mpp0 0 gpio, nand(io2), spi(cs)
25 mpp1 1 gpo, nand(io3), spi(mosi)
26 mpp2 2 gpo, nand(io4), spi(sck)
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/Linux-v6.1/drivers/iio/frequency/
Dadf4350.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ADF4350/ADF4351 SPI Wideband Synthesizer driver
5 * Copyright 2012-2013 Analog Devices Inc.
15 #include <linux/spi/spi.h>
21 #include <linux/clk.h>
35 struct spi_device *spi; member
39 struct clk *clk; member
53 * writes. The device is configured via a sequence of SPI writes,
78 for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) { in adf4350_sync_config()
79 if ((st->regs_hw[i] != st->regs[i]) || in adf4350_sync_config()
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/Linux-v6.1/drivers/iio/adc/
Dad9467.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Analog Devices AD9467 SPI ADC driver
5 * Copyright 2012-2020 Analog Devices Inc.
12 #include <linux/spi/spi.h>
22 #include <linux/clk.h>
24 #include <linux/iio/adc/adi-axi-adc.h>
27 * ADI High-Speed ADC common spi interface registers
28 * See Application-Note AN-877:
29 * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf
80 * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC
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/Linux-v6.1/drivers/net/can/spi/
Dhi311x.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* CAN bus driver for Holt HI3110 CAN Controller with SPI Interface
12 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
13 * - Simon Kallweit, intefo AG
19 #include <linux/clk.h>
35 #include <linux/spi/spi.h>
147 struct spi_device *spi; member
150 struct mutex hi3110_lock; /* SPI device lock */
172 struct clk *clk; member
179 if (priv->tx_skb || priv->tx_busy) in hi3110_clean()
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