1 // SPDX-License-Identifier: GPL-2.0-only
3  * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
5  * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
7  * This driver has been based on the spi-gpio.c:
17 #include <linux/spi/spi.h>
18 #include <linux/spi/spi-mem.h>
19 #include <linux/spi/spi_bitbang.h>
21 #include <linux/clk.h>
24 #define DRV_NAME	"ath79-spi"
30 #define AR71XX_SPI_REG_CTRL		0x04	/* SPI Control */
31 #define AR71XX_SPI_REG_IOC		0x08	/* SPI I/O Control */
37 #define AR71XX_SPI_IOC_CLK		BIT(8)	/* CLK pin */
45 	struct clk		*clk;  member
51 	return ioread32(sp->base + reg);  in ath79_spi_rr()
56 	iowrite32(val, sp->base + reg);  in ath79_spi_wr()
59 static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)  in ath79_spidev_to_sp()  argument
61 	return spi_master_get_devdata(spi->master);  in ath79_spidev_to_sp()
66 	if (nsecs > sp->rrw_delay)  in ath79_spi_delay()
67 		ndelay(nsecs - sp->rrw_delay);  in ath79_spi_delay()
70 static void ath79_spi_chipselect(struct spi_device *spi, int is_active)  in ath79_spi_chipselect()  argument
72 	struct ath79_spi *sp = ath79_spidev_to_sp(spi);  in ath79_spi_chipselect()
73 	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;  in ath79_spi_chipselect()
74 	u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);  in ath79_spi_chipselect()
77 		sp->ioc_base |= cs_bit;  in ath79_spi_chipselect()
79 		sp->ioc_base &= ~cs_bit;  in ath79_spi_chipselect()
81 	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);  in ath79_spi_chipselect()
90 	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);  in ath79_spi_enable()
91 	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);  in ath79_spi_enable()
93 	/* clear clk and mosi in the base state */  in ath79_spi_enable()
94 	sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK);  in ath79_spi_enable()
103 	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);  in ath79_spi_disable()
108 static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,  in ath79_spi_txrx_mode0()  argument
111 	struct ath79_spi *sp = ath79_spidev_to_sp(spi);  in ath79_spi_txrx_mode0()
112 	u32 ioc = sp->ioc_base;  in ath79_spi_txrx_mode0()
115 	for (word <<= (32 - bits); likely(bits); bits--) {  in ath79_spi_txrx_mode0()
140 	struct ath79_spi *sp = ath79_spidev_to_sp(mem->spi);  in ath79_exec_mem_op()
143 	if (mem->spi->chip_select || mem->spi->cs_gpiod)  in ath79_exec_mem_op()
144 		return -ENOTSUPP;  in ath79_exec_mem_op()
146 	/* Only use for fast-read op. */  in ath79_exec_mem_op()
147 	if (op->cmd.opcode != 0x0b || op->data.dir != SPI_MEM_DATA_IN ||  in ath79_exec_mem_op()
148 	    op->addr.nbytes != 3 || op->dummy.nbytes != 1)  in ath79_exec_mem_op()
149 		return -ENOTSUPP;  in ath79_exec_mem_op()
154 	memcpy_fromio(op->data.buf.in, sp->base + op->addr.val, op->data.nbytes);  in ath79_exec_mem_op()
160 	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);  in ath79_exec_mem_op()
176 	master = spi_alloc_master(&pdev->dev, sizeof(*sp));  in ath79_spi_probe()
178 		dev_err(&pdev->dev, "failed to allocate spi master\n");  in ath79_spi_probe()
179 		return -ENOMEM;  in ath79_spi_probe()
183 	master->dev.of_node = pdev->dev.of_node;  in ath79_spi_probe()
186 	master->use_gpio_descriptors = true;  in ath79_spi_probe()
187 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);  in ath79_spi_probe()
188 	master->flags = SPI_MASTER_GPIO_SS;  in ath79_spi_probe()
189 	master->num_chipselect = 3;  in ath79_spi_probe()
190 	master->mem_ops = &ath79_mem_ops;  in ath79_spi_probe()
192 	sp->bitbang.master = master;  in ath79_spi_probe()
193 	sp->bitbang.chipselect = ath79_spi_chipselect;  in ath79_spi_probe()
194 	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;  in ath79_spi_probe()
195 	sp->bitbang.flags = SPI_CS_HIGH;  in ath79_spi_probe()
197 	sp->base = devm_platform_ioremap_resource(pdev, 0);  in ath79_spi_probe()
198 	if (IS_ERR(sp->base)) {  in ath79_spi_probe()
199 		ret = PTR_ERR(sp->base);  in ath79_spi_probe()
203 	sp->clk = devm_clk_get(&pdev->dev, "ahb");  in ath79_spi_probe()
204 	if (IS_ERR(sp->clk)) {  in ath79_spi_probe()
205 		ret = PTR_ERR(sp->clk);  in ath79_spi_probe()
209 	ret = clk_prepare_enable(sp->clk);  in ath79_spi_probe()
213 	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);  in ath79_spi_probe()
215 		ret = -EINVAL;  in ath79_spi_probe()
219 	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;  in ath79_spi_probe()
220 	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",  in ath79_spi_probe()
221 		sp->rrw_delay);  in ath79_spi_probe()
224 	ret = spi_bitbang_start(&sp->bitbang);  in ath79_spi_probe()
233 	clk_disable_unprepare(sp->clk);  in ath79_spi_probe()
235 	spi_master_put(sp->bitbang.master);  in ath79_spi_probe()
244 	spi_bitbang_stop(&sp->bitbang);  in ath79_spi_remove()
246 	clk_disable_unprepare(sp->clk);  in ath79_spi_remove()
247 	spi_master_put(sp->bitbang.master);  in ath79_spi_remove()
258 	{ .compatible = "qca,ar7100-spi", },
274 MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");