1 // SPDX-License-Identifier: GPL-2.0-only
3  * Memory-mapped interface driver for DW SPI Core
8 #include <linux/clk.h>
13 #include <linux/spi/spi.h>
24 #include "spi-dw.h"
30 	struct clk     *clk;  member
31 	struct clk     *pclk;
57  * The Designware SPI controller (referred to as master in the documentation)
60  * the SPI boot controller registers. the final chip select is an OR gate
61  * between the Designware SPI controller and the SPI boot controller.
63 static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)  in dw_spi_mscc_set_cs()  argument
65 	struct dw_spi *dws = spi_master_get_devdata(spi->master);  in dw_spi_mscc_set_cs()
67 	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;  in dw_spi_mscc_set_cs()
68 	u32 cs = spi->chip_select;  in dw_spi_mscc_set_cs()
76 		writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);  in dw_spi_mscc_set_cs()
79 	dw_spi_set_cs(spi, enable);  in dw_spi_mscc_set_cs()
88 	dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);  in dw_spi_mscc_init()
90 		return -ENOMEM;  in dw_spi_mscc_init()
92 	dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1);  in dw_spi_mscc_init()
93 	if (IS_ERR(dwsmscc->spi_mst)) {  in dw_spi_mscc_init()
94 		dev_err(&pdev->dev, "SPI_MST region map failed\n");  in dw_spi_mscc_init()
95 		return PTR_ERR(dwsmscc->spi_mst);  in dw_spi_mscc_init()
98 	dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);  in dw_spi_mscc_init()
99 	if (IS_ERR(dwsmscc->syscon))  in dw_spi_mscc_init()
100 		return PTR_ERR(dwsmscc->syscon);  in dw_spi_mscc_init()
103 	writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);  in dw_spi_mscc_init()
106 	regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,  in dw_spi_mscc_init()
110 	dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;  in dw_spi_mscc_init()
111 	dwsmmio->priv = dwsmscc;  in dw_spi_mscc_init()
119 	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",  in dw_spi_mscc_ocelot_init()
126 	return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",  in dw_spi_mscc_jaguar2_init()
131  * The Designware SPI controller (referred to as master in the
136 static void dw_spi_sparx5_set_cs(struct spi_device *spi, bool enable)  in dw_spi_sparx5_set_cs()  argument
138 	struct dw_spi *dws = spi_master_get_devdata(spi->master);  in dw_spi_sparx5_set_cs()
140 	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;  in dw_spi_sparx5_set_cs()
141 	u8 cs = spi->chip_select;  in dw_spi_sparx5_set_cs()
145 		regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 1);  in dw_spi_sparx5_set_cs()
147 		regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~BIT(cs));  in dw_spi_sparx5_set_cs()
152 		regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~0);  in dw_spi_sparx5_set_cs()
156 		regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 0);  in dw_spi_sparx5_set_cs()
159 	dw_spi_set_cs(spi, enable);  in dw_spi_sparx5_set_cs()
165 	const char *syscon_name = "microchip,sparx5-cpu-syscon";  in dw_spi_mscc_sparx5_init()
166 	struct device *dev = &pdev->dev;  in dw_spi_mscc_sparx5_init()
171 		return -EOPNOTSUPP;  in dw_spi_mscc_sparx5_init()
176 		return -ENOMEM;  in dw_spi_mscc_sparx5_init()
178 	dwsmscc->syscon =  in dw_spi_mscc_sparx5_init()
180 	if (IS_ERR(dwsmscc->syscon)) {  in dw_spi_mscc_sparx5_init()
182 		return PTR_ERR(dwsmscc->syscon);  in dw_spi_mscc_sparx5_init()
185 	dwsmmio->dws.set_cs = dw_spi_sparx5_set_cs;  in dw_spi_mscc_sparx5_init()
186 	dwsmmio->priv = dwsmscc;  in dw_spi_mscc_sparx5_init()
194 	dwsmmio->dws.caps = DW_SPI_CAP_CS_OVERRIDE;  in dw_spi_alpine_init()
202 	dw_spi_dma_setup_generic(&dwsmmio->dws);  in dw_spi_pssi_init()
210 	dwsmmio->dws.ip = DW_HSSI_ID;  in dw_spi_hssi_init()
212 	dw_spi_dma_setup_generic(&dwsmmio->dws);  in dw_spi_hssi_init()
220 	dwsmmio->dws.ip = DW_HSSI_ID;  in dw_spi_intel_init()
229 	 * The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is  in dw_spi_canaan_k210_init()
235 	dwsmmio->dws.fifo_len = 31;  in dw_spi_canaan_k210_init()
250 	dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),  in dw_spi_mmio_probe()
253 		return -ENOMEM;  in dw_spi_mmio_probe()
255 	dws = &dwsmmio->dws;  in dw_spi_mmio_probe()
258 	dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);  in dw_spi_mmio_probe()
259 	if (IS_ERR(dws->regs))  in dw_spi_mmio_probe()
260 		return PTR_ERR(dws->regs);  in dw_spi_mmio_probe()
262 	dws->paddr = mem->start;  in dw_spi_mmio_probe()
264 	dws->irq = platform_get_irq(pdev, 0);  in dw_spi_mmio_probe()
265 	if (dws->irq < 0)  in dw_spi_mmio_probe()
266 		return dws->irq; /* -ENXIO */  in dw_spi_mmio_probe()
268 	dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);  in dw_spi_mmio_probe()
269 	if (IS_ERR(dwsmmio->clk))  in dw_spi_mmio_probe()
270 		return PTR_ERR(dwsmmio->clk);  in dw_spi_mmio_probe()
271 	ret = clk_prepare_enable(dwsmmio->clk);  in dw_spi_mmio_probe()
276 	dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");  in dw_spi_mmio_probe()
277 	if (IS_ERR(dwsmmio->pclk)) {  in dw_spi_mmio_probe()
278 		ret = PTR_ERR(dwsmmio->pclk);  in dw_spi_mmio_probe()
281 	ret = clk_prepare_enable(dwsmmio->pclk);  in dw_spi_mmio_probe()
286 	dwsmmio->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");  in dw_spi_mmio_probe()
287 	if (IS_ERR(dwsmmio->rstc)) {  in dw_spi_mmio_probe()
288 		ret = PTR_ERR(dwsmmio->rstc);  in dw_spi_mmio_probe()
291 	reset_control_deassert(dwsmmio->rstc);  in dw_spi_mmio_probe()
293 	dws->bus_num = pdev->id;  in dw_spi_mmio_probe()
295 	dws->max_freq = clk_get_rate(dwsmmio->clk);  in dw_spi_mmio_probe()
297 	device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);  in dw_spi_mmio_probe()
301 	device_property_read_u32(&pdev->dev, "num-cs", &num_cs);  in dw_spi_mmio_probe()
303 	dws->num_cs = num_cs;  in dw_spi_mmio_probe()
305 	init_func = device_get_match_data(&pdev->dev);  in dw_spi_mmio_probe()
312 	pm_runtime_enable(&pdev->dev);  in dw_spi_mmio_probe()
314 	ret = dw_spi_add_host(&pdev->dev, dws);  in dw_spi_mmio_probe()
322 	pm_runtime_disable(&pdev->dev);  in dw_spi_mmio_probe()
323 	clk_disable_unprepare(dwsmmio->pclk);  in dw_spi_mmio_probe()
325 	clk_disable_unprepare(dwsmmio->clk);  in dw_spi_mmio_probe()
326 	reset_control_assert(dwsmmio->rstc);  in dw_spi_mmio_probe()
335 	dw_spi_remove_host(&dwsmmio->dws);  in dw_spi_mmio_remove()
336 	pm_runtime_disable(&pdev->dev);  in dw_spi_mmio_remove()
337 	clk_disable_unprepare(dwsmmio->pclk);  in dw_spi_mmio_remove()
338 	clk_disable_unprepare(dwsmmio->clk);  in dw_spi_mmio_remove()
339 	reset_control_assert(dwsmmio->rstc);  in dw_spi_mmio_remove()
345 	{ .compatible = "snps,dw-apb-ssi", .data = dw_spi_pssi_init},
346 	{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
347 	{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
348 	{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
349 	{ .compatible = "renesas,rzn1-spi", .data = dw_spi_pssi_init},
350 	{ .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_hssi_init},
351 	{ .compatible = "intel,keembay-ssi", .data = dw_spi_intel_init},
352 	{ .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init},
353 	{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
354 	{ .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
378 MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
379 MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");