1 // SPDX-License-Identifier: GPL-2.0
3 // SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
7 // Based on spi-mt7621.c:
9 // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
10 // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
12 #include <linux/clk.h>
18 #include <linux/spi/spi.h>
20 #define DRIVER_NAME "spi-ar934x"
46 	struct clk *clk;  member
52 	int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1;  in ar934x_spi_clk_div()
57 		return -EINVAL;  in ar934x_spi_clk_div()
62 static int ar934x_spi_setup(struct spi_device *spi)  in ar934x_spi_setup()  argument
64 	struct ar934x_spi *sp = spi_controller_get_devdata(spi->master);  in ar934x_spi_setup()
66 	if ((spi->max_speed_hz == 0) ||  in ar934x_spi_setup()
67 	    (spi->max_speed_hz > (sp->clk_freq / 2))) {  in ar934x_spi_setup()
68 		spi->max_speed_hz = sp->clk_freq / 2;  in ar934x_spi_setup()
69 	} else if (spi->max_speed_hz < (sp->clk_freq / 128)) {  in ar934x_spi_setup()
70 		dev_err(&spi->dev, "spi clock is too low\n");  in ar934x_spi_setup()
71 		return -EINVAL;  in ar934x_spi_setup()
82 	struct spi_device *spi = m->spi;  in ar934x_spi_transfer_one_message()  local
91 	m->actual_length = 0;  in ar934x_spi_transfer_one_message()
92 	list_for_each_entry(t, &m->transfers, transfer_list) {  in ar934x_spi_transfer_one_message()
93 		if (t->bits_per_word >= 8 && t->bits_per_word < 32)  in ar934x_spi_transfer_one_message()
94 			bpw = t->bits_per_word >> 3;  in ar934x_spi_transfer_one_message()
98 		if (t->speed_hz)  in ar934x_spi_transfer_one_message()
99 			div = ar934x_spi_clk_div(sp, t->speed_hz);  in ar934x_spi_transfer_one_message()
101 			div = ar934x_spi_clk_div(sp, spi->max_speed_hz);  in ar934x_spi_transfer_one_message()
103 			stat = -EIO;  in ar934x_spi_transfer_one_message()
107 		reg = ioread32(sp->base + AR934X_SPI_REG_CTRL);  in ar934x_spi_transfer_one_message()
110 		iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);  in ar934x_spi_transfer_one_message()
111 		iowrite32(0, sp->base + AR934X_SPI_DATAOUT);  in ar934x_spi_transfer_one_message()
113 		for (trx_done = 0; trx_done < t->len; trx_done += bpw) {  in ar934x_spi_transfer_one_message()
114 			trx_cur = t->len - trx_done;  in ar934x_spi_transfer_one_message()
117 			else if (list_is_last(&t->transfer_list, &m->transfers))  in ar934x_spi_transfer_one_message()
120 			if (t->tx_buf) {  in ar934x_spi_transfer_one_message()
121 				tx_buf = t->tx_buf + trx_done;  in ar934x_spi_transfer_one_message()
125 				iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);  in ar934x_spi_transfer_one_message()
128 			reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term,  in ar934x_spi_transfer_one_message()
130 			iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);  in ar934x_spi_transfer_one_message()
132 				sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg,  in ar934x_spi_transfer_one_message()
137 			if (t->rx_buf) {  in ar934x_spi_transfer_one_message()
138 				reg = ioread32(sp->base + AR934X_SPI_DATAIN);  in ar934x_spi_transfer_one_message()
139 				buf = t->rx_buf + trx_done;  in ar934x_spi_transfer_one_message()
141 					buf[trx_cur - i - 1] = reg & 0xff;  in ar934x_spi_transfer_one_message()
145 			spi_delay_exec(&t->word_delay, t);  in ar934x_spi_transfer_one_message()
147 		m->actual_length += t->len;  in ar934x_spi_transfer_one_message()
152 	m->status = stat;  in ar934x_spi_transfer_one_message()
159 	{ .compatible = "qca,ar934x-spi" },
169 	struct clk *clk;  in ar934x_spi_probe()  local
176 	clk = devm_clk_get(&pdev->dev, NULL);  in ar934x_spi_probe()
177 	if (IS_ERR(clk)) {  in ar934x_spi_probe()
178 		dev_err(&pdev->dev, "failed to get clock\n");  in ar934x_spi_probe()
179 		return PTR_ERR(clk);  in ar934x_spi_probe()
182 	ret = clk_prepare_enable(clk);  in ar934x_spi_probe()
186 	ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*sp));  in ar934x_spi_probe()
188 		dev_info(&pdev->dev, "failed to allocate spi controller\n");  in ar934x_spi_probe()
189 		ret = -ENOMEM;  in ar934x_spi_probe()
193 	/* disable flash mapping and expose spi controller registers */  in ar934x_spi_probe()
195 	/* restore pins to default state: CSn=1 DO=CLK=0 */  in ar934x_spi_probe()
198 	ctlr->mode_bits = SPI_LSB_FIRST;  in ar934x_spi_probe()
199 	ctlr->setup = ar934x_spi_setup;  in ar934x_spi_probe()
200 	ctlr->transfer_one_message = ar934x_spi_transfer_one_message;  in ar934x_spi_probe()
201 	ctlr->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(24) |  in ar934x_spi_probe()
203 	ctlr->dev.of_node = pdev->dev.of_node;  in ar934x_spi_probe()
204 	ctlr->num_chipselect = 3;  in ar934x_spi_probe()
206 	dev_set_drvdata(&pdev->dev, ctlr);  in ar934x_spi_probe()
209 	sp->base = base;  in ar934x_spi_probe()
210 	sp->clk = clk;  in ar934x_spi_probe()
211 	sp->clk_freq = clk_get_rate(clk);  in ar934x_spi_probe()
212 	sp->ctlr = ctlr;  in ar934x_spi_probe()
219 	clk_disable_unprepare(clk);  in ar934x_spi_probe()
228 	ctlr = dev_get_drvdata(&pdev->dev);  in ar934x_spi_remove()
232 	clk_disable_unprepare(sp->clk);  in ar934x_spi_remove()
248 MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx");