1 // SPDX-License-Identifier: GPL-2.0-only
3  * J-Core SPI controller driver
5  * Copyright (C) 2012-2016 Smart Energy Instruments, Inc.
16 #include <linux/spi/spi.h>
17 #include <linux/clk.h>
52 	} while (--timeout);  in jcore_spi_wait()
54 	return -EBUSY;  in jcore_spi_wait()
59 	void __iomem *ctrl_reg = hw->base + CTRL_REG;  in jcore_spi_program()
62 		dev_err(hw->master->dev.parent,  in jcore_spi_program()
65 	writel(hw->cs_reg | hw->speed_reg, ctrl_reg);  in jcore_spi_program()
68 static void jcore_spi_chipsel(struct spi_device *spi, bool value)  in jcore_spi_chipsel()  argument
70 	struct jcore_spi *hw = spi_master_get_devdata(spi->master);  in jcore_spi_chipsel()
71 	u32 csbit = 1U << (2 * spi->chip_select);  in jcore_spi_chipsel()
73 	dev_dbg(hw->master->dev.parent, "chipselect %d\n", spi->chip_select);  in jcore_spi_chipsel()
76 		hw->cs_reg |= csbit;  in jcore_spi_chipsel()
78 		hw->cs_reg &= ~csbit;  in jcore_spi_chipsel()
85 	if (speed == hw->speed_hz)  in jcore_spi_baudrate()
87 	hw->speed_hz = speed;  in jcore_spi_baudrate()
88 	if (speed >= hw->clock_freq / 2)  in jcore_spi_baudrate()
89 		hw->speed_reg = 0;  in jcore_spi_baudrate()
91 		hw->speed_reg = ((hw->clock_freq / 2 / speed) - 1) << 27;  in jcore_spi_baudrate()
93 	dev_dbg(hw->master->dev.parent, "speed=%d reg=0x%x\n",  in jcore_spi_baudrate()
94 		speed, hw->speed_reg);  in jcore_spi_baudrate()
97 static int jcore_spi_txrx(struct spi_master *master, struct spi_device *spi,  in jcore_spi_txrx()  argument
102 	void __iomem *ctrl_reg = hw->base + CTRL_REG;  in jcore_spi_txrx()
103 	void __iomem *data_reg = hw->base + DATA_REG;  in jcore_spi_txrx()
112 	jcore_spi_baudrate(hw, t->speed_hz);  in jcore_spi_txrx()
114 	xmit = hw->cs_reg | hw->speed_reg | JCORE_SPI_CTRL_XMIT;  in jcore_spi_txrx()
115 	tx = t->tx_buf;  in jcore_spi_txrx()
116 	rx = t->rx_buf;  in jcore_spi_txrx()
117 	len = t->len;  in jcore_spi_txrx()
136 		return -EREMOTEIO;  in jcore_spi_txrx()
143 	struct device_node *node = pdev->dev.of_node;  in jcore_spi_probe()
148 	struct clk *clk;  in jcore_spi_probe()  local
149 	int err = -ENODEV;  in jcore_spi_probe()
151 	master = spi_alloc_master(&pdev->dev, sizeof(struct jcore_spi));  in jcore_spi_probe()
156 	master->num_chipselect = 3;  in jcore_spi_probe()
157 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;  in jcore_spi_probe()
158 	master->transfer_one = jcore_spi_txrx;  in jcore_spi_probe()
159 	master->set_cs = jcore_spi_chipsel;  in jcore_spi_probe()
160 	master->dev.of_node = node;  in jcore_spi_probe()
161 	master->bus_num = pdev->id;  in jcore_spi_probe()
164 	hw->master = master;  in jcore_spi_probe()
171 	if (!devm_request_mem_region(&pdev->dev, res->start,  in jcore_spi_probe()
172 				     resource_size(res), pdev->name))  in jcore_spi_probe()
174 	hw->base = devm_ioremap(&pdev->dev, res->start,  in jcore_spi_probe()
176 	if (!hw->base)  in jcore_spi_probe()
180 	 * The SPI clock rate controlled via a configurable clock divider  in jcore_spi_probe()
182 	 * most suitable for obtaining standard SPI clock rates, but some  in jcore_spi_probe()
188 	clk = devm_clk_get(&pdev->dev, "ref_clk");  in jcore_spi_probe()
189 	if (!IS_ERR(clk)) {  in jcore_spi_probe()
190 		if (clk_prepare_enable(clk) == 0) {  in jcore_spi_probe()
191 			clock_freq = clk_get_rate(clk);  in jcore_spi_probe()
192 			clk_disable_unprepare(clk);  in jcore_spi_probe()
194 			dev_warn(&pdev->dev, "could not enable ref_clk\n");  in jcore_spi_probe()
196 	hw->clock_freq = clock_freq;  in jcore_spi_probe()
199 	hw->cs_reg = JCORE_SPI_CTRL_CS_BITS;  in jcore_spi_probe()
202 	/* Register our spi controller */  in jcore_spi_probe()
203 	err = devm_spi_register_master(&pdev->dev, master);  in jcore_spi_probe()
210 	err = -EBUSY;  in jcore_spi_probe()
232 MODULE_DESCRIPTION("J-Core SPI driver");