Home
last modified time | relevance | path

Searched +full:plic +full:- +full:1 (Results 1 – 22 of 22) sorted by relevance

/Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
[all …]
Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
21 entry, though external interrupt controllers (like the PLIC, for example) will
23 a PLIC interrupt property will typically list the HLICs for all present HARTs
[all …]
/Linux-v6.1/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
20 i-cache-block-size = <64>;
21 i-cache-sets = <128>;
[all …]
Dmpfs-icicle-kit-fabric.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
5 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
9 compatible = "microchip,corepwm-rtl-v4";
11 microchip,sync-update-mask = /bits/ 32 <0>;
12 #pwm-cells = <2>;
18 compatible = "microchip,corei2c-rtl-v7";
20 #address-cells = <1>;
21 #size-cells = <0>;
23 interrupt-parent = <&plic>;
[all …]
Dmpfs-polarberry-fabric.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2022 Microchip Technology Inc */
5 fabric_clk3: fabric-clk3 {
6 compatible = "fixed-clock";
7 #clock-cells = <0>;
8 clock-frequency = <62500000>;
11 fabric_clk1: fabric-clk1 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <125000000>;
[all …]
Dmpfs-m100pfs-fabric.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 fabric_clk3: fabric-clk3 {
6 compatible = "fixed-clock";
7 #clock-cells = <0>;
8 clock-frequency = <62500000>;
11 fabric_clk1: fabric-clk1 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <125000000>;
18 compatible = "microchip,pcie-host-1.0";
[all …]
Dmpfs-sev-kit-fabric.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 fabric_clk3: fabric-clk3 {
6 compatible = "fixed-clock";
7 #clock-cells = <0>;
8 clock-frequency = <0>;
11 fabric_clk1: fabric-clk1 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <125000000>;
18 compatible = "microchip,pcie-host-1.0";
[all …]
/Linux-v6.1/drivers/irqchip/
Dirq-sifive-plic.c1 // SPDX-License-Identifier: GPL-2.0
6 #define pr_fmt(fmt) "plic: " fmt
23 * This driver implements a version of the RISC-V PLIC with the actual layout
26 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
28 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
29 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
92 u32 hwirq_mask = 1 << (hwirq % 32); in __plic_toggle()
102 raw_spin_lock(&handler->enable_lock); in plic_toggle()
103 __plic_toggle(handler->enable_base, hwirq, enable); in plic_toggle()
104 raw_spin_unlock(&handler->enable_lock); in plic_toggle()
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
22 default 1
118 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
126 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
213 bool "J-Core integrated AIC" if COMPILE_TEST
217 Support for the J-Core integrated AIC.
228 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
231 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
236 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
286 tristate "TS-4800 IRQ controller"
[all …]
/Linux-v6.1/arch/riscv/boot/dts/starfive/
Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/net/can/
Dmicrochip,mpfs-can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/microchip,mpfs-can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Conor Dooley <conor.dooley@microchip.com>
14 - $ref: can-controller.yaml#
18 const: microchip,mpfs-can
21 maxItems: 1
24 maxItems: 1
27 maxItems: 1
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/spi/
Dmicrochip,mpfs-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Conor Dooley <conor.dooley@microchip.com>
17 - $ref: spi-controller.yaml#
22 - items:
23 - const: microchip,mpfs-qspi
24 - const: microchip,coreqspi-rtl-v2
25 - const: microchip,coreqspi-rtl-v2 #FPGA QSPI
[all …]
Dspi-sifive.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: "spi-controller.yaml#"
20 - enum:
21 - sifive,fu540-c000-spi
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/usb/
Dmicrochip,mpfs-musb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/microchip,mpfs-musb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: usb-drd.yaml#
13 - Conor Dooley <conor.dooley@microchip.com>
18 - microchip,mpfs-musb
23 maxItems: 1
29 interrupt-names:
31 - const: dma
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/i2c/
Dmicrochip,corei2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - items:
19 - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
20 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
21 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
24 maxItems: 1
[all …]
/Linux-v6.1/arch/m68k/include/asm/
Dm5272sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5272sim.h -- ColdFire 5272 System Integration Module support.
31 #define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */
68 #define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */
69 #define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */
70 #define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */
100 #define MCF_IRQ_EINT1 65 /* External Interrupt 1 */
104 #define MCF_IRQ_TIMER1 69 /* Timer 1 */
109 #define MCF_IRQ_UART1 74 /* UART 1 */
110 #define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/gpio/
Dsifive,gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Walmsley <paul.walmsley@sifive.com>
15 - enum:
16 - sifive,fu540-c000-gpio
17 - sifive,fu740-c000-gpio
18 - canaan,k210-gpiohs
19 - const: sifive,gpio0
22 maxItems: 1
[all …]
Dmicrochip,mpfs-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Conor Dooley <conor.dooley@microchip.com>
15 - enum:
16 - microchip,mpfs-gpio
19 maxItems: 1
24 minItems: 1
27 interrupt-controller: true
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pwm/
Dpwm-sifive.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
20 numbers can be found here -
22 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
25 - $ref: pwm.yaml#
30 - enum:
[all …]
/Linux-v6.1/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
[all …]
Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
[all …]
/Linux-v6.1/arch/riscv/boot/dts/canaan/
Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
28 * Since this is a non-ratified draft specification, the kernel does not
[all …]