Lines Matching +full:plic +full:- +full:1
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
30 i-cache-size = <16384>;
31 next-level-cache = <&ccache>;
35 cpu0_intc: interrupt-controller {
36 #interrupt-cells = <1>;
37 compatible = "riscv,cpu-intc";
38 interrupt-controller;
41 cpu1: cpu@1 {
43 d-cache-block-size = <64>;
44 d-cache-sets = <64>;
45 d-cache-size = <32768>;
46 d-tlb-sets = <1>;
47 d-tlb-size = <40>;
49 i-cache-block-size = <64>;
50 i-cache-sets = <128>;
51 i-cache-size = <32768>;
52 i-tlb-sets = <1>;
53 i-tlb-size = <40>;
54 mmu-type = "riscv,sv39";
55 next-level-cache = <&ccache>;
58 tlb-split;
59 cpu1_intc: interrupt-controller {
60 #interrupt-cells = <1>;
61 compatible = "riscv,cpu-intc";
62 interrupt-controller;
67 d-cache-block-size = <64>;
68 d-cache-sets = <64>;
69 d-cache-size = <32768>;
70 d-tlb-sets = <1>;
71 d-tlb-size = <40>;
73 i-cache-block-size = <64>;
74 i-cache-sets = <128>;
75 i-cache-size = <32768>;
76 i-tlb-sets = <1>;
77 i-tlb-size = <40>;
78 mmu-type = "riscv,sv39";
79 next-level-cache = <&ccache>;
82 tlb-split;
83 cpu2_intc: interrupt-controller {
84 #interrupt-cells = <1>;
85 compatible = "riscv,cpu-intc";
86 interrupt-controller;
91 d-cache-block-size = <64>;
92 d-cache-sets = <64>;
93 d-cache-size = <32768>;
94 d-tlb-sets = <1>;
95 d-tlb-size = <40>;
97 i-cache-block-size = <64>;
98 i-cache-sets = <128>;
99 i-cache-size = <32768>;
100 i-tlb-sets = <1>;
101 i-tlb-size = <40>;
102 mmu-type = "riscv,sv39";
103 next-level-cache = <&ccache>;
106 tlb-split;
107 cpu3_intc: interrupt-controller {
108 #interrupt-cells = <1>;
109 compatible = "riscv,cpu-intc";
110 interrupt-controller;
115 d-cache-block-size = <64>;
116 d-cache-sets = <64>;
117 d-cache-size = <32768>;
118 d-tlb-sets = <1>;
119 d-tlb-size = <40>;
121 i-cache-block-size = <64>;
122 i-cache-sets = <128>;
123 i-cache-size = <32768>;
124 i-tlb-sets = <1>;
125 i-tlb-size = <40>;
126 mmu-type = "riscv,sv39";
127 next-level-cache = <&ccache>;
130 tlb-split;
131 cpu4_intc: interrupt-controller {
132 #interrupt-cells = <1>;
133 compatible = "riscv,cpu-intc";
134 interrupt-controller;
138 cpu-map {
163 #address-cells = <2>;
164 #size-cells = <2>;
165 compatible = "simple-bus";
167 plic0: interrupt-controller@c000000 {
168 #interrupt-cells = <1>;
169 #address-cells = <0>;
170 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
173 interrupt-controller;
174 interrupts-extended =
181 prci: clock-controller@10000000 {
182 compatible = "sifive,fu740-c000-prci";
185 #clock-cells = <1>;
186 #reset-cells = <1>;
189 compatible = "sifive,fu740-c000-uart", "sifive,uart0";
191 interrupt-parent = <&plic0>;
197 compatible = "sifive,fu740-c000-uart", "sifive,uart0";
199 interrupt-parent = <&plic0>;
205 compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
207 interrupt-parent = <&plic0>;
210 reg-shift = <2>;
211 reg-io-width = <1>;
212 #address-cells = <1>;
213 #size-cells = <0>;
217 compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
219 interrupt-parent = <&plic0>;
222 reg-shift = <2>;
223 reg-io-width = <1>;
224 #address-cells = <1>;
225 #size-cells = <0>;
229 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
232 interrupt-parent = <&plic0>;
235 #address-cells = <1>;
236 #size-cells = <0>;
240 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
243 interrupt-parent = <&plic0>;
246 #address-cells = <1>;
247 #size-cells = <0>;
251 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
253 interrupt-parent = <&plic0>;
256 #address-cells = <1>;
257 #size-cells = <0>;
261 compatible = "sifive,fu540-c000-gem";
262 interrupt-parent = <&plic0>;
266 local-mac-address = [00 00 00 00 00 00];
267 clock-names = "pclk", "hclk";
270 #address-cells = <1>;
271 #size-cells = <0>;
275 compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
277 interrupt-parent = <&plic0>;
280 #pwm-cells = <3>;
284 compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
286 interrupt-parent = <&plic0>;
289 #pwm-cells = <3>;
292 ccache: cache-controller@2010000 {
293 compatible = "sifive,fu740-c000-ccache", "cache";
294 cache-block-size = <64>;
295 cache-level = <2>;
296 cache-sets = <2048>;
297 cache-size = <2097152>;
298 cache-unified;
299 interrupt-parent = <&plic0>;
304 compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
305 interrupt-parent = <&plic0>;
310 gpio-controller;
311 #gpio-cells = <2>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
318 compatible = "sifive,fu740-pcie";
319 #address-cells = <3>;
320 #size-cells = <2>;
321 #interrupt-cells = <1>;
325 reg-names = "dbi", "config", "mgmt";
327 dma-coherent;
328 bus-range = <0x0 0xff>;
333 num-lanes = <0x8>;
335 interrupt-names = "msi", "inta", "intb", "intc", "intd";
336 interrupt-parent = <&plic0>;
337 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
338 interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
342 clock-names = "pcie_aux";
344 pwren-gpios = <&gpio 5 0>;
345 reset-gpios = <&gpio 8 0>;