Lines Matching +full:plic +full:- +full:1
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
30 i-cache-size = <16384>;
34 cpu0_intc: interrupt-controller {
35 #interrupt-cells = <1>;
36 compatible = "riscv,cpu-intc";
37 interrupt-controller;
40 cpu1: cpu@1 {
41 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
42 d-cache-block-size = <64>;
43 d-cache-sets = <64>;
44 d-cache-size = <32768>;
45 d-tlb-sets = <1>;
46 d-tlb-size = <32>;
48 i-cache-block-size = <64>;
49 i-cache-sets = <64>;
50 i-cache-size = <32768>;
51 i-tlb-sets = <1>;
52 i-tlb-size = <32>;
53 mmu-type = "riscv,sv39";
54 reg = <1>;
56 tlb-split;
57 next-level-cache = <&l2cache>;
58 cpu1_intc: interrupt-controller {
59 #interrupt-cells = <1>;
60 compatible = "riscv,cpu-intc";
61 interrupt-controller;
65 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
66 d-cache-block-size = <64>;
67 d-cache-sets = <64>;
68 d-cache-size = <32768>;
69 d-tlb-sets = <1>;
70 d-tlb-size = <32>;
72 i-cache-block-size = <64>;
73 i-cache-sets = <64>;
74 i-cache-size = <32768>;
75 i-tlb-sets = <1>;
76 i-tlb-size = <32>;
77 mmu-type = "riscv,sv39";
80 tlb-split;
81 next-level-cache = <&l2cache>;
82 cpu2_intc: interrupt-controller {
83 #interrupt-cells = <1>;
84 compatible = "riscv,cpu-intc";
85 interrupt-controller;
89 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
90 d-cache-block-size = <64>;
91 d-cache-sets = <64>;
92 d-cache-size = <32768>;
93 d-tlb-sets = <1>;
94 d-tlb-size = <32>;
96 i-cache-block-size = <64>;
97 i-cache-sets = <64>;
98 i-cache-size = <32768>;
99 i-tlb-sets = <1>;
100 i-tlb-size = <32>;
101 mmu-type = "riscv,sv39";
104 tlb-split;
105 next-level-cache = <&l2cache>;
106 cpu3_intc: interrupt-controller {
107 #interrupt-cells = <1>;
108 compatible = "riscv,cpu-intc";
109 interrupt-controller;
113 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
114 d-cache-block-size = <64>;
115 d-cache-sets = <64>;
116 d-cache-size = <32768>;
117 d-tlb-sets = <1>;
118 d-tlb-size = <32>;
120 i-cache-block-size = <64>;
121 i-cache-sets = <64>;
122 i-cache-size = <32768>;
123 i-tlb-sets = <1>;
124 i-tlb-size = <32>;
125 mmu-type = "riscv,sv39";
128 tlb-split;
129 next-level-cache = <&l2cache>;
130 cpu4_intc: interrupt-controller {
131 #interrupt-cells = <1>;
132 compatible = "riscv,cpu-intc";
133 interrupt-controller;
137 cpu-map {
162 #address-cells = <2>;
163 #size-cells = <2>;
164 compatible = "simple-bus";
166 plic0: interrupt-controller@c000000 {
167 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
169 #address-cells = <0>;
170 #interrupt-cells = <1>;
171 interrupt-controller;
172 interrupts-extended =
180 prci: clock-controller@10000000 {
181 compatible = "sifive,fu540-c000-prci";
184 #clock-cells = <1>;
187 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
189 interrupt-parent = <&plic0>;
194 dma: dma-controller@3000000 {
195 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
197 interrupt-parent = <&plic0>;
200 dma-channels = <4>;
201 #dma-cells = <1>;
204 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
206 interrupt-parent = <&plic0>;
212 compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
214 interrupt-parent = <&plic0>;
217 reg-shift = <2>;
218 reg-io-width = <1>;
219 #address-cells = <1>;
220 #size-cells = <0>;
224 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
227 interrupt-parent = <&plic0>;
230 #address-cells = <1>;
231 #size-cells = <0>;
235 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
238 interrupt-parent = <&plic0>;
241 #address-cells = <1>;
242 #size-cells = <0>;
246 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
248 interrupt-parent = <&plic0>;
251 #address-cells = <1>;
252 #size-cells = <0>;
256 compatible = "sifive,fu540-c000-gem";
257 interrupt-parent = <&plic0>;
261 local-mac-address = [00 00 00 00 00 00];
262 clock-names = "pclk", "hclk";
265 #address-cells = <1>;
266 #size-cells = <0>;
270 compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
272 interrupt-parent = <&plic0>;
275 #pwm-cells = <3>;
279 compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
281 interrupt-parent = <&plic0>;
284 #pwm-cells = <3>;
287 l2cache: cache-controller@2010000 {
288 compatible = "sifive,fu540-c000-ccache", "cache";
289 cache-block-size = <64>;
290 cache-level = <2>;
291 cache-sets = <1024>;
292 cache-size = <2097152>;
293 cache-unified;
294 interrupt-parent = <&plic0>;
295 interrupts = <1>, <2>, <3>;
299 compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
300 interrupt-parent = <&plic0>;
305 gpio-controller;
306 #gpio-cells = <2>;
307 interrupt-controller;
308 #interrupt-cells = <2>;