Lines Matching +full:plic +full:- +full:1
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
20 i-cache-block-size = <64>;
21 i-cache-sets = <128>;
22 i-cache-size = <16384>;
28 cpu0_intc: interrupt-controller {
29 #interrupt-cells = <1>;
30 compatible = "riscv,cpu-intc";
31 interrupt-controller;
35 cpu1: cpu@1 {
36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
37 d-cache-block-size = <64>;
38 d-cache-sets = <64>;
39 d-cache-size = <32768>;
40 d-tlb-sets = <1>;
41 d-tlb-size = <32>;
43 i-cache-block-size = <64>;
44 i-cache-sets = <64>;
45 i-cache-size = <32768>;
46 i-tlb-sets = <1>;
47 i-tlb-size = <32>;
48 mmu-type = "riscv,sv39";
49 reg = <1>;
52 tlb-split;
53 next-level-cache = <&cctrllr>;
56 cpu1_intc: interrupt-controller {
57 #interrupt-cells = <1>;
58 compatible = "riscv,cpu-intc";
59 interrupt-controller;
64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
65 d-cache-block-size = <64>;
66 d-cache-sets = <64>;
67 d-cache-size = <32768>;
68 d-tlb-sets = <1>;
69 d-tlb-size = <32>;
71 i-cache-block-size = <64>;
72 i-cache-sets = <64>;
73 i-cache-size = <32768>;
74 i-tlb-sets = <1>;
75 i-tlb-size = <32>;
76 mmu-type = "riscv,sv39";
80 tlb-split;
81 next-level-cache = <&cctrllr>;
84 cpu2_intc: interrupt-controller {
85 #interrupt-cells = <1>;
86 compatible = "riscv,cpu-intc";
87 interrupt-controller;
92 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
93 d-cache-block-size = <64>;
94 d-cache-sets = <64>;
95 d-cache-size = <32768>;
96 d-tlb-sets = <1>;
97 d-tlb-size = <32>;
99 i-cache-block-size = <64>;
100 i-cache-sets = <64>;
101 i-cache-size = <32768>;
102 i-tlb-sets = <1>;
103 i-tlb-size = <32>;
104 mmu-type = "riscv,sv39";
108 tlb-split;
109 next-level-cache = <&cctrllr>;
112 cpu3_intc: interrupt-controller {
113 #interrupt-cells = <1>;
114 compatible = "riscv,cpu-intc";
115 interrupt-controller;
120 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
121 d-cache-block-size = <64>;
122 d-cache-sets = <64>;
123 d-cache-size = <32768>;
124 d-tlb-sets = <1>;
125 d-tlb-size = <32>;
127 i-cache-block-size = <64>;
128 i-cache-sets = <64>;
129 i-cache-size = <32768>;
130 i-tlb-sets = <1>;
131 i-tlb-size = <32>;
132 mmu-type = "riscv,sv39";
136 tlb-split;
137 next-level-cache = <&cctrllr>;
139 cpu4_intc: interrupt-controller {
140 #interrupt-cells = <1>;
141 compatible = "riscv,cpu-intc";
142 interrupt-controller;
146 cpu-map {
172 compatible = "fixed-clock";
173 #clock-cells = <0>;
177 compatible = "microchip,mpfs-sys-controller";
182 #address-cells = <2>;
183 #size-cells = <2>;
184 compatible = "simple-bus";
187 cctrllr: cache-controller@2010000 {
188 compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
190 cache-block-size = <64>;
191 cache-level = <2>;
192 cache-sets = <1024>;
193 cache-size = <2097152>;
194 cache-unified;
195 interrupt-parent = <&plic>;
196 interrupts = <1>, <3>, <4>, <2>;
200 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
202 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
209 plic: interrupt-controller@c000000 { label
210 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
212 #address-cells = <0>;
213 #interrupt-cells = <1>;
214 interrupt-controller;
215 interrupts-extended = <&cpu0_intc 11>,
223 pdma: dma-controller@3000000 {
224 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
226 interrupt-parent = <&plic>;
228 dma-channels = <4>;
229 #dma-cells = <1>;
233 compatible = "microchip,mpfs-clkcfg";
236 #clock-cells = <1>;
242 reg-io-width = <4>;
243 reg-shift = <2>;
244 interrupt-parent = <&plic>;
246 current-speed = <115200>;
254 reg-io-width = <4>;
255 reg-shift = <2>;
256 interrupt-parent = <&plic>;
258 current-speed = <115200>;
266 reg-io-width = <4>;
267 reg-shift = <2>;
268 interrupt-parent = <&plic>;
270 current-speed = <115200>;
278 reg-io-width = <4>;
279 reg-shift = <2>;
280 interrupt-parent = <&plic>;
282 current-speed = <115200>;
290 reg-io-width = <4>;
291 reg-shift = <2>;
292 interrupt-parent = <&plic>;
295 current-speed = <115200>;
301 compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
303 interrupt-parent = <&plic>;
306 max-frequency = <200000000>;
311 compatible = "microchip,mpfs-spi";
312 #address-cells = <1>;
313 #size-cells = <0>;
315 interrupt-parent = <&plic>;
322 compatible = "microchip,mpfs-spi";
323 #address-cells = <1>;
324 #size-cells = <0>;
326 interrupt-parent = <&plic>;
333 compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
334 #address-cells = <1>;
335 #size-cells = <0>;
337 interrupt-parent = <&plic>;
344 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
346 #address-cells = <1>;
347 #size-cells = <0>;
348 interrupt-parent = <&plic>;
351 clock-frequency = <100000>;
356 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
358 #address-cells = <1>;
359 #size-cells = <0>;
360 interrupt-parent = <&plic>;
363 clock-frequency = <100000>;
368 compatible = "microchip,mpfs-can";
371 interrupt-parent = <&plic>;
377 compatible = "microchip,mpfs-can";
380 interrupt-parent = <&plic>;
388 #address-cells = <1>;
389 #size-cells = <0>;
390 interrupt-parent = <&plic>;
392 local-mac-address = [00 00 00 00 00 00];
394 clock-names = "pclk", "hclk";
401 #address-cells = <1>;
402 #size-cells = <0>;
403 interrupt-parent = <&plic>;
405 local-mac-address = [00 00 00 00 00 00];
407 clock-names = "pclk", "hclk";
412 compatible = "microchip,mpfs-gpio";
414 interrupt-parent = <&plic>;
415 interrupt-controller;
416 #interrupt-cells = <1>;
418 gpio-controller;
419 #gpio-cells = <2>;
424 compatible = "microchip,mpfs-gpio";
426 interrupt-parent = <&plic>;
427 interrupt-controller;
428 #interrupt-cells = <1>;
430 gpio-controller;
431 #gpio-cells = <2>;
436 compatible = "microchip,mpfs-gpio";
438 interrupt-parent = <&plic>;
439 interrupt-controller;
440 #interrupt-cells = <1>;
442 gpio-controller;
443 #gpio-cells = <2>;
448 compatible = "microchip,mpfs-rtc";
450 interrupt-parent = <&plic>;
453 clock-names = "rtc", "rtcref";
458 compatible = "microchip,mpfs-musb";
460 interrupt-parent = <&plic>;
463 interrupt-names = "dma","mc";
468 compatible = "microchip,mpfs-mailbox";
470 interrupt-parent = <&plic>;
472 #mbox-cells = <1>;