Lines Matching +full:plic +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
24 d-cache-sets = <64>;
25 d-cache-size = <32768>;
26 d-tlb-sets = <1>;
27 d-tlb-size = <32>;
29 i-cache-block-size = <64>;
30 i-cache-sets = <64>;
31 i-cache-size = <32768>;
32 i-tlb-sets = <1>;
33 i-tlb-size = <32>;
34 mmu-type = "riscv,sv39";
36 tlb-split;
38 cpu0_intc: interrupt-controller {
39 compatible = "riscv,cpu-intc";
40 interrupt-controller;
41 #interrupt-cells = <1>;
45 U74_1: cpu@1 {
46 compatible = "sifive,u74-mc", "riscv";
47 reg = <1>;
48 d-cache-block-size = <64>;
49 d-cache-sets = <64>;
50 d-cache-size = <32768>;
51 d-tlb-sets = <1>;
52 d-tlb-size = <32>;
54 i-cache-block-size = <64>;
55 i-cache-sets = <64>;
56 i-cache-size = <32768>;
57 i-tlb-sets = <1>;
58 i-tlb-size = <32>;
59 mmu-type = "riscv,sv39";
61 tlb-split;
63 cpu1_intc: interrupt-controller {
64 compatible = "riscv,cpu-intc";
65 interrupt-controller;
66 #interrupt-cells = <1>;
70 cpu-map {
84 compatible = "fixed-clock";
85 #clock-cells = <0>;
87 clock-frequency = <0>;
91 compatible = "fixed-clock";
92 #clock-cells = <0>;
94 clock-frequency = <0>;
98 compatible = "fixed-clock";
99 #clock-cells = <0>;
101 clock-frequency = <0>;
105 compatible = "fixed-clock";
106 #clock-cells = <0>;
108 clock-frequency = <0>;
112 compatible = "simple-bus";
113 interrupt-parent = <&plic>;
114 #address-cells = <2>;
115 #size-cells = <2>;
119 compatible = "starfive,jh7100-clint", "sifive,clint0";
121 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
125 plic: interrupt-controller@c000000 { label
126 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
128 interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
130 interrupt-controller;
131 #address-cells = <0>;
132 #interrupt-cells = <1>;
136 clkgen: clock-controller@11800000 {
137 compatible = "starfive,jh7100-clkgen";
140 clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
141 #clock-cells = <1>;
144 rstgen: reset-controller@11840000 {
145 compatible = "starfive,jh7100-reset";
147 #reset-cells = <1>;
151 compatible = "snps,designware-i2c";
155 clock-names = "ref", "pclk";
158 #address-cells = <1>;
159 #size-cells = <0>;
164 compatible = "snps,designware-i2c";
168 clock-names = "ref", "pclk";
171 #address-cells = <1>;
172 #size-cells = <0>;
177 compatible = "starfive,jh7100-pinctrl";
180 reg-names = "gpio", "padctl";
184 gpio-controller;
185 #gpio-cells = <2>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
191 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
195 clock-names = "baudclk", "apb_pclk";
198 reg-io-width = <4>;
199 reg-shift = <2>;
204 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
208 clock-names = "baudclk", "apb_pclk";
211 reg-io-width = <4>;
212 reg-shift = <2>;
217 compatible = "snps,designware-i2c";
221 clock-names = "ref", "pclk";
224 #address-cells = <1>;
225 #size-cells = <0>;
230 compatible = "snps,designware-i2c";
234 clock-names = "ref", "pclk";
237 #address-cells = <1>;
238 #size-cells = <0>;