Lines Matching +full:plic +full:- +full:1
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
5 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
9 compatible = "microchip,corepwm-rtl-v4";
11 microchip,sync-update-mask = /bits/ 32 <0>;
12 #pwm-cells = <2>;
18 compatible = "microchip,corei2c-rtl-v7";
20 #address-cells = <1>;
21 #size-cells = <0>;
23 interrupt-parent = <&plic>;
25 clock-frequency = <100000>;
29 fabric_clk3: fabric-clk3 {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <50000000>;
35 fabric_clk1: fabric-clk1 {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <125000000>;
42 compatible = "microchip,pcie-host-1.0";
43 #address-cells = <0x3>;
44 #interrupt-cells = <0x1>;
45 #size-cells = <0x2>;
48 reg-names = "cfg", "apb";
49 bus-range = <0x0 0x7f>;
50 interrupt-parent = <&plic>;
52 interrupt-map = <0 0 0 1 &pcie_intc 0>,
53 <0 0 0 2 &pcie_intc 1>,
56 interrupt-map-mask = <0 0 0 7>;
58 clock-names = "fic1", "fic3";
60 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
61 msi-parent = <&pcie>;
62 msi-controller;
64 pcie_intc: interrupt-controller {
65 #address-cells = <0>;
66 #interrupt-cells = <1>;
67 interrupt-controller;