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/Linux-v6.1/drivers/s390/block/
Ddasd_proc.c1 // SPDX-License-Identifier: GPL-2.0
42 device = dasd_device_from_devindex((unsigned long) v - 1); in dasd_devices_show()
45 if (device->block) in dasd_devices_show()
46 block = device->block; in dasd_devices_show()
52 seq_printf(m, "%s", dev_name(&device->cdev->dev)); in dasd_devices_show()
54 if (device->discipline != NULL) in dasd_devices_show()
55 seq_printf(m, "(%s)", device->discipline->name); in dasd_devices_show()
59 if (block->gdp) in dasd_devices_show()
61 MAJOR(disk_devt(block->gdp)), in dasd_devices_show()
62 MINOR(disk_devt(block->gdp))); in dasd_devices_show()
[all …]
/Linux-v6.1/drivers/clk/mediatek/
Dclk-mt8173.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include "clk-cpumux.h"
12 #include "clk-gate.h"
13 #include "clk-mtk.h"
14 #include "clk-pll.h"
16 #include <dt-bindings/clock/mt8173-clk.h>
37 FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2),
38 FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3),
40 FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2),
41 FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3),
[all …]
Dclk-mt6765.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
15 #include "clk-gate.h"
16 #include "clk-mtk.h"
17 #include "clk-mux.h"
18 #include "clk-pll.h"
20 #include <dt-bindings/clock/mt6765-clk.h>
83 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
84 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
85 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
[all …]
Dclk-mt8135.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <dt-bindings/clock/mt8135-clk.h>
14 #include "clk-gate.h"
15 #include "clk-mtk.h"
16 #include "clk-pll.h"
21 FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
22 FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
23 FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
24 FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
28 FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2),
[all …]
Dclk-mt2712.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include "clk-gate.h"
17 #include "clk-pll.h"
18 #include "clk-mtk.h"
20 #include <dt-bindings/clock/mt2712-clk.h>
40 FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1,
42 FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1,
47 FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1,
49 FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1,
51 FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1,
[all …]
Dclk-mt8516.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "clk-gate.h"
15 #include "clk-mtk.h"
16 #include "clk-pll.h"
18 #include <dt-bindings/clock/mt8516-clk.h>
29 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
30 FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
31 FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
32 FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8),
33 FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16),
[all …]
Dclk-mt8167.c1 // SPDX-License-Identifier: GPL-2.0
15 #include "clk-gate.h"
16 #include "clk-mtk.h"
17 #include "clk-pll.h"
19 #include <dt-bindings/clock/mt8167-clk.h>
33 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
34 FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
35 FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
36 FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8),
37 FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16),
[all …]
Dclk-mt7986-topckgen.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include "clk-mtk.h"
14 #include "clk-gate.h"
15 #include "clk-mux.h"
17 #include <dt-bindings/clock/mt7986-clk.h>
29 FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
30 FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
31 FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
33 FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2),
[all …]
Dclk-mt6797.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
12 #include "clk-gate.h"
13 #include "clk-mtk.h"
14 #include "clk-pll.h"
16 #include <dt-bindings/clock/mt6797-clk.h>
27 FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1),
28 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
29 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
30 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
[all …]
/Linux-v6.1/drivers/clk/mmp/
Dclk-frac.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mmp factor clock operation source file
9 #include <linux/clk-provider.h>
16 * It is M/N clock
19 * numerator/denominator = Fin / (Fout * factor)
27 struct mmp_clk_factor *factor = to_clk_factor(hw); in clk_factor_round_rate() local
31 for (i = 0; i < factor->ftbl_cnt; i++) { in clk_factor_round_rate()
34 rate *= factor->ftbl[i].den; in clk_factor_round_rate()
35 do_div(rate, factor->ftbl[i].num * factor->masks->factor); in clk_factor_round_rate()
40 if ((i == 0) || (i == factor->ftbl_cnt)) { in clk_factor_round_rate()
[all …]
/Linux-v6.1/drivers/iio/afe/
Diio-rescale.c1 // SPDX-License-Identifier: GPL-2.0
33 *val *= rescale->numerator; in rescale_process_scale()
34 if (rescale->denominator == 1) in rescale_process_scale()
36 *val2 = rescale->denominator; in rescale_process_scale()
44 if (!check_mul_overflow(*val, rescale->numerator, &_val) && in rescale_process_scale()
45 !check_mul_overflow(*val2, rescale->denominator, &_val2)) { in rescale_process_scale()
53 tmp = div_s64(tmp, rescale->denominator); in rescale_process_scale()
54 tmp *= rescale->numerator; in rescale_process_scale()
82 * *val = 1 and *val2 = -0.5 yields -1.5 not -0.5. in rescale_process_scale()
86 tmp = (s64)abs(*val) * abs(rescale->numerator); in rescale_process_scale()
[all …]
/Linux-v6.1/drivers/crypto/caam/
Dcaampkc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * caam - Freescale FSL CAAM support for Public Key Cryptography descriptors
18 * caam_priv_key_form - CAAM RSA private key representation
21 * 1. The first representation consists of the pair (n, d), where the
23 * n the RSA modulus
28 * p the first prime factor of the RSA modulus n
29 * q the second prime factor of the RSA modulus n
34 * p the first prime factor of the RSA modulus n
35 * q the second prime factor of the RSA modulus n
50 * caam_rsa_key - CAAM RSA key structure. Keys are allocated in DMA zone.
[all …]
/Linux-v6.1/drivers/media/platform/allegro-dvt/
Dnal-hevc.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 #include <linux/v4l2-controls.h>
60 * struct nal_hevc_vps - Video parameter set
63 * Rec. ITU-T H.265 (02/2018) 7.3.2.1 Video parameter set RBSP syntax
135 * struct nal_hevc_vui_parameters - VUI parameters
137 * C struct representation of the VUI parameters as defined by Rec. ITU-T
198 * struct nal_hevc_sps - Sequence parameter set
201 * Rec. ITU-T H.265 (02/2018) 7.3.2.2 Sequence parameter set RBSP syntax
324 * nal_hevc_profile() - Get profile_idc for v4l2 hevc profile
328 * in Rec. ITU-T H.265 (02/2018) A.3.
[all …]
/Linux-v6.1/fs/btrfs/
Dmisc.h1 /* SPDX-License-Identifier: GPL-2.0 */
35 static inline u64 div_factor(u64 num, int factor) in div_factor() argument
37 if (factor == 10) in div_factor()
39 num *= factor; in div_factor()
43 static inline u64 div_factor_fine(u64 num, int factor) in div_factor_fine() argument
45 if (factor == 100) in div_factor_fine()
47 num *= factor; in div_factor_fine()
52 static inline bool is_power_of_two_u64(u64 n) in is_power_of_two_u64() argument
54 return n != 0 && (n & (n - 1)) == 0; in is_power_of_two_u64()
57 static inline bool has_single_bit_set(u64 n) in has_single_bit_set() argument
[all …]
/Linux-v6.1/drivers/clk/actions/
Dowl-factor.c1 // SPDX-License-Identifier: GPL-2.0+
3 // OWL factor clock driver
6 // Author: David Liu <liuwei@actions-semi.com>
11 #include <linux/clk-provider.h>
14 #include "owl-factor.h"
21 for (clkt = table; clkt->div; clkt++) in _get_table_maxval()
22 if (clkt->val > maxval) in _get_table_maxval()
23 maxval = clkt->val; in _get_table_maxval()
32 for (clkt = table; clkt->div; clkt++) { in _get_table_div_mul()
33 if (clkt->val == val) { in _get_table_div_mul()
[all …]
/Linux-v6.1/tools/testing/selftests/syscall_user_dispatch/
Dsud_benchmark.c1 // SPDX-License-Identifier: GPL-2.0-only
37 * requires some per-architecture support (i.e. knowledge about the
39 * a small trampoline is open-coded for x86_64. Other architectures
65 int factor; variable
77 return (t2.tv_sec - t1.tv_sec) + 1.0e-9 * (t2.tv_nsec - t1.tv_nsec); in one_sysinfo_step()
84 printf("Calibrating test set to last ~%d seconds...\n", CALIBRATE_TO_SECS); in calibrate_set()
88 factor += CALIBRATE_TO_SECS; in calibrate_set()
91 printf("test iterations = %d\n", CALIBRATION_STEP * factor); in calibrate_set()
99 for (i = 0; i < factor; ++i) in perf_syscall()
100 partial += one_sysinfo_step()/(CALIBRATION_STEP*factor); in perf_syscall()
[all …]
/Linux-v6.1/drivers/media/test-drivers/vivid/
Dvivid-vid-out.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * vivid-vid-out.c - video output support functions.
12 #include <linux/v4l2-dv-timings.h>
13 #include <media/v4l2-common.h>
14 #include <media/v4l2-event.h>
15 #include <media/v4l2-dv-timings.h>
16 #include <media/v4l2-rect.h>
18 #include "vivid-core.h"
19 #include "vivid-vid-common.h"
20 #include "vivid-kthread-out.h"
[all …]
/Linux-v6.1/drivers/clk/ti/
Dfixed-factor.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI Fixed Factor Clock
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
23 * of_ti_fixed_factor_clk_setup - Setup function for TI fixed factor clock
26 * Sets up a simple fixed factor clock based on device tree info.
36 if (of_property_read_u32(node, "ti,clock-div", &div)) { in of_ti_fixed_factor_clk_setup()
37 pr_err("%pOFn must have a clock-div property\n", node); in of_ti_fixed_factor_clk_setup()
41 if (of_property_read_u32(node, "ti,clock-mult", &mult)) { in of_ti_fixed_factor_clk_setup()
42 pr_err("%pOFn must have a clock-mult property\n", node); in of_ti_fixed_factor_clk_setup()
[all …]
/Linux-v6.1/drivers/media/platform/ti/vpe/
Dsc.c1 // SPDX-License-Identifier: GPL-2.0-only
23 struct device *dev = &sc->pdev->dev; in sc_dump_regs()
25 #define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, \ in sc_dump_regs()
26 ioread32(sc->base + CFG_##r)) in sc_dump_regs()
28 dev_dbg(dev, "SC Registers @ %pa:\n", &sc->res->start); in sc_dump_regs()
84 idx = HS_LT_9_16_SCALE + sixteenths - 8; in sc_set_hs_coeffs()
99 coeff_h += SC_NUM_TAPS_MEM_ALIGN - SC_H_NUM_TAPS; in sc_set_hs_coeffs()
102 sc->load_coeff_h = true; in sc_set_hs_coeffs()
127 idx = VS_LT_9_16_SCALE + sixteenths - 8; in sc_set_vs_coeffs()
140 coeff_v += SC_NUM_TAPS_MEM_ALIGN - SC_V_NUM_TAPS; in sc_set_vs_coeffs()
[all …]
/Linux-v6.1/tools/testing/selftests/kvm/x86_64/
Dvmx_nested_tsc_scaling_test.c1 // SPDX-License-Identifier: GPL-2.0-only
18 /* L2 is scaled up (from L1's perspective) by this factor */
21 #define TSC_OFFSET_L2 ((uint64_t) -33125236320908)
42 thresh_low = expected - tolerance; in compare_tsc_freq()
69 tsc_freq = tsc_end - tsc_start; in check_tsc_freq()
136 print_skip("Kernel does not use TSC clocksource - assuming that host TSC is not stable"); in stable_tsc_check_supported()
158 * We set L1's scale factor to be a random number from 2 to 10. in main()
159 * Ideally we would do the same for L2's factor but that one is in main()
165 printf("L1's scale down factor is: %"PRIu64"\n", l1_scale_factor); in main()
166 printf("L2's scale up factor is: %llu\n", L2_SCALE_FACTOR); in main()
[all …]
/Linux-v6.1/drivers/clk/
Dclk-fixed-factor.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
41 best_parent = (rate / fix->mult) * fix->div; in clk_factor_round_rate()
45 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
[all …]
/Linux-v6.1/drivers/iio/adc/
Dad7292.c1 // SPDX-License-Identifier: GPL-2.0
91 st->d8[0] = AD7292_RD_FLAG_MSK(addr); in ad7292_spi_reg_read()
93 ret = spi_write_then_read(st->spi, st->d8, 1, &st->d16, 2); in ad7292_spi_reg_read()
97 return be16_to_cpu(st->d16); in ad7292_spi_reg_read()
103 unsigned int shift = 16 - (8 * len); in ad7292_spi_subreg_read()
106 st->d8[0] = AD7292_RD_FLAG_MSK(addr); in ad7292_spi_subreg_read()
107 st->d8[1] = sub_addr; in ad7292_spi_subreg_read()
109 ret = spi_write_then_read(st->spi, st->d8, 2, &st->d16, len); in ad7292_spi_subreg_read()
113 return (be16_to_cpu(st->d16) >> shift); in ad7292_spi_subreg_read()
123 .tx_buf = &st->d8, in ad7292_single_conversion()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/hwmon/
Dti,tmp421.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guenter Roeck <linux@roeck-us.net>
19 - ti,tmp421
20 - ti,tmp422
21 - ti,tmp423
22 - ti,tmp441
23 - ti,tmp442
27 '#address-cells':
[all …]
/Linux-v6.1/drivers/clk/sunxi/
Dclk-factors.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Adjustable factor-based clock implementation
8 #include <linux/clk-provider.h>
16 #include "clk-factors.h"
19 * DOC: basic adjustable factor-based clock
22 * prepare - clk_prepare only ensures that parents are prepared
23 * enable - clk_enable only ensures that parents are enabled
24 * rate - rate is adjustable.
25 * clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
26 * parent - fixed parent. No clk_set_parent support
[all …]
/Linux-v6.1/drivers/gpu/drm/sprd/
Dmegacores_pll.c1 // SPDX-License-Identifier: GPL-2.0
22 #define AVERAGE(a, b) (min(a, b) + abs((b) - (a)) / 2)
34 const unsigned long long factor = 100; in dphy_calc_pll_param() local
38 pll->potential_fvco = pll->freq / khz; in dphy_calc_pll_param()
39 pll->ref_clk = PHY_REF_CLK / khz; in dphy_calc_pll_param()
42 if (pll->potential_fvco >= VCO_BAND_LOW && in dphy_calc_pll_param()
43 pll->potential_fvco <= VCO_BAND_HIGH) { in dphy_calc_pll_param()
44 pll->fvco = pll->potential_fvco; in dphy_calc_pll_param()
45 pll->out_sel = BIT(i); in dphy_calc_pll_param()
48 pll->potential_fvco <<= 1; in dphy_calc_pll_param()
[all …]

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