1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: James Liao <jamesjj.liao@mediatek.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/of.h>
9 #include <linux/of_address.h>
10
11 #include "clk-cpumux.h"
12 #include "clk-gate.h"
13 #include "clk-mtk.h"
14 #include "clk-pll.h"
15
16 #include <dt-bindings/clock/mt8173-clk.h>
17
18 /*
19 * For some clocks, we don't care what their actual rates are. And these
20 * clocks may change their rate on different products or different scenarios.
21 * So we model these clocks' rate as 0, to denote it's not an actual rate.
22 */
23 #define DUMMY_RATE 0
24
25 static DEFINE_SPINLOCK(mt8173_clk_lock);
26
27 static const struct mtk_fixed_clk fixed_clks[] __initconst = {
28 FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", DUMMY_RATE),
29 FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
30 FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", DUMMY_RATE),
31 FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", DUMMY_RATE),
32 FIXED_CLK(CLK_TOP_LVDS_PXL, "lvds_pxl", "lvdspll", DUMMY_RATE),
33 FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", DUMMY_RATE),
34 };
35
36 static const struct mtk_fixed_factor top_divs[] __initconst = {
37 FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2),
38 FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3),
39
40 FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2),
41 FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3),
42 FACTOR(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5),
43 FACTOR(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7),
44
45 FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4),
46 FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3),
47
48 FACTOR(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2),
49 FACTOR(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3),
50 FACTOR(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5),
51 FACTOR(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7),
52 FACTOR(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26),
53
54 FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1),
55 FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
56 FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),
57
58 FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2),
59 FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3),
60
61 FACTOR(CLK_TOP_ARMCA7PLL_D2, "armca7pll_d2", "armca7pll_754m", 1, 1),
62 FACTOR(CLK_TOP_ARMCA7PLL_D3, "armca7pll_d3", "armca7pll_502m", 1, 1),
63
64 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
65 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
66
67 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1),
68 FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2),
69 FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4),
70 FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8),
71 FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16", "clkph_mck_o", 1, 16),
72
73 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
74 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
75 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
76
77 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
78 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
79
80 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
81 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
82 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
83 FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1),
84 FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2),
85 FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4),
86
87 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1),
88 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2),
89 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4),
90 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8),
91 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16),
92 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1),
93 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2),
94 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4),
95 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1),
96 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2),
97 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4),
98 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1),
99 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2),
100 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4),
101
102 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1),
103 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
104 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4),
105 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8),
106 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16),
107
108 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1),
109 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2),
110 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4),
111 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8),
112 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1),
113 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2),
114 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4),
115 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8),
116 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1),
117 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2),
118 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4),
119 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8),
120 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1),
121 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1),
122 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2),
123
124 FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3),
125 FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4),
126
127 FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1),
128 FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll", 1, 2),
129 FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4),
130 };
131
132 static const char * const axi_parents[] __initconst = {
133 "clk26m",
134 "syspll1_d2",
135 "syspll_d5",
136 "syspll1_d4",
137 "univpll_d5",
138 "univpll2_d2",
139 "dmpll_d2",
140 "dmpll_d4"
141 };
142
143 static const char * const mem_parents[] __initconst = {
144 "clk26m",
145 "dmpll_ck"
146 };
147
148 static const char * const ddrphycfg_parents[] __initconst = {
149 "clk26m",
150 "syspll1_d8"
151 };
152
153 static const char * const mm_parents[] __initconst = {
154 "clk26m",
155 "vencpll_d2",
156 "main_h364m",
157 "syspll1_d2",
158 "syspll_d5",
159 "syspll1_d4",
160 "univpll1_d2",
161 "univpll2_d2",
162 "dmpll_d2"
163 };
164
165 static const char * const pwm_parents[] __initconst = {
166 "clk26m",
167 "univpll2_d4",
168 "univpll3_d2",
169 "univpll1_d4"
170 };
171
172 static const char * const vdec_parents[] __initconst = {
173 "clk26m",
174 "vcodecpll_ck",
175 "tvdpll_445p5m",
176 "univpll_d3",
177 "vencpll_d2",
178 "syspll_d3",
179 "univpll1_d2",
180 "mmpll_d2",
181 "dmpll_d2",
182 "dmpll_d4"
183 };
184
185 static const char * const venc_parents[] __initconst = {
186 "clk26m",
187 "vcodecpll_ck",
188 "tvdpll_445p5m",
189 "univpll_d3",
190 "vencpll_d2",
191 "syspll_d3",
192 "univpll1_d2",
193 "univpll2_d2",
194 "dmpll_d2",
195 "dmpll_d4"
196 };
197
198 static const char * const mfg_parents[] __initconst = {
199 "clk26m",
200 "mmpll_ck",
201 "dmpll_ck",
202 "clk26m",
203 "clk26m",
204 "clk26m",
205 "clk26m",
206 "clk26m",
207 "clk26m",
208 "syspll_d3",
209 "syspll1_d2",
210 "syspll_d5",
211 "univpll_d3",
212 "univpll1_d2",
213 "univpll_d5",
214 "univpll2_d2"
215 };
216
217 static const char * const camtg_parents[] __initconst = {
218 "clk26m",
219 "univpll_d26",
220 "univpll2_d2",
221 "syspll3_d2",
222 "syspll3_d4",
223 "univpll1_d4"
224 };
225
226 static const char * const uart_parents[] __initconst = {
227 "clk26m",
228 "univpll2_d8"
229 };
230
231 static const char * const spi_parents[] __initconst = {
232 "clk26m",
233 "syspll3_d2",
234 "syspll1_d4",
235 "syspll4_d2",
236 "univpll3_d2",
237 "univpll2_d4",
238 "univpll1_d8"
239 };
240
241 static const char * const usb20_parents[] __initconst = {
242 "clk26m",
243 "univpll1_d8",
244 "univpll3_d4"
245 };
246
247 static const char * const usb30_parents[] __initconst = {
248 "clk26m",
249 "univpll3_d2",
250 "usb_syspll_125m",
251 "univpll2_d4"
252 };
253
254 static const char * const msdc50_0_h_parents[] __initconst = {
255 "clk26m",
256 "syspll1_d2",
257 "syspll2_d2",
258 "syspll4_d2",
259 "univpll_d5",
260 "univpll1_d4"
261 };
262
263 static const char * const msdc50_0_parents[] __initconst = {
264 "clk26m",
265 "msdcpll_ck",
266 "msdcpll_d2",
267 "univpll1_d4",
268 "syspll2_d2",
269 "syspll_d7",
270 "msdcpll_d4",
271 "vencpll_d4",
272 "tvdpll_ck",
273 "univpll_d2",
274 "univpll1_d2",
275 "mmpll_ck",
276 "msdcpll2_ck",
277 "msdcpll2_d2",
278 "msdcpll2_d4"
279 };
280
281 static const char * const msdc30_1_parents[] __initconst = {
282 "clk26m",
283 "univpll2_d2",
284 "msdcpll_d4",
285 "univpll1_d4",
286 "syspll2_d2",
287 "syspll_d7",
288 "univpll_d7",
289 "vencpll_d4"
290 };
291
292 static const char * const msdc30_2_parents[] __initconst = {
293 "clk26m",
294 "univpll2_d2",
295 "msdcpll_d4",
296 "univpll1_d4",
297 "syspll2_d2",
298 "syspll_d7",
299 "univpll_d7",
300 "vencpll_d2"
301 };
302
303 static const char * const msdc30_3_parents[] __initconst = {
304 "clk26m",
305 "msdcpll2_ck",
306 "msdcpll2_d2",
307 "univpll2_d2",
308 "msdcpll2_d4",
309 "msdcpll_d4",
310 "univpll1_d4",
311 "syspll2_d2",
312 "syspll_d7",
313 "univpll_d7",
314 "vencpll_d4",
315 "msdcpll_ck",
316 "msdcpll_d2",
317 "msdcpll_d4"
318 };
319
320 static const char * const audio_parents[] __initconst = {
321 "clk26m",
322 "syspll3_d4",
323 "syspll4_d4",
324 "syspll1_d16"
325 };
326
327 static const char * const aud_intbus_parents[] __initconst = {
328 "clk26m",
329 "syspll1_d4",
330 "syspll4_d2",
331 "univpll3_d2",
332 "univpll2_d8",
333 "dmpll_d4",
334 "dmpll_d8"
335 };
336
337 static const char * const pmicspi_parents[] __initconst = {
338 "clk26m",
339 "syspll1_d8",
340 "syspll3_d4",
341 "syspll1_d16",
342 "univpll3_d4",
343 "univpll_d26",
344 "dmpll_d8",
345 "dmpll_d16"
346 };
347
348 static const char * const scp_parents[] __initconst = {
349 "clk26m",
350 "syspll1_d2",
351 "univpll_d5",
352 "syspll_d5",
353 "dmpll_d2",
354 "dmpll_d4"
355 };
356
357 static const char * const atb_parents[] __initconst = {
358 "clk26m",
359 "syspll1_d2",
360 "univpll_d5",
361 "dmpll_d2"
362 };
363
364 static const char * const venc_lt_parents[] __initconst = {
365 "clk26m",
366 "univpll_d3",
367 "vcodecpll_ck",
368 "tvdpll_445p5m",
369 "vencpll_d2",
370 "syspll_d3",
371 "univpll1_d2",
372 "univpll2_d2",
373 "syspll1_d2",
374 "univpll_d5",
375 "vcodecpll_370p5",
376 "dmpll_ck"
377 };
378
379 static const char * const dpi0_parents[] __initconst = {
380 "clk26m",
381 "tvdpll_d2",
382 "tvdpll_d4",
383 "clk26m",
384 "clk26m",
385 "tvdpll_d8",
386 "tvdpll_d16"
387 };
388
389 static const char * const irda_parents[] __initconst = {
390 "clk26m",
391 "univpll2_d4",
392 "syspll2_d4"
393 };
394
395 static const char * const cci400_parents[] __initconst = {
396 "clk26m",
397 "vencpll_ck",
398 "armca7pll_754m",
399 "armca7pll_502m",
400 "univpll_d2",
401 "syspll_d2",
402 "msdcpll_ck",
403 "dmpll_ck"
404 };
405
406 static const char * const aud_1_parents[] __initconst = {
407 "clk26m",
408 "apll1_ck",
409 "univpll2_d4",
410 "univpll2_d8"
411 };
412
413 static const char * const aud_2_parents[] __initconst = {
414 "clk26m",
415 "apll2_ck",
416 "univpll2_d4",
417 "univpll2_d8"
418 };
419
420 static const char * const mem_mfg_in_parents[] __initconst = {
421 "clk26m",
422 "mmpll_ck",
423 "dmpll_ck",
424 "clk26m"
425 };
426
427 static const char * const axi_mfg_in_parents[] __initconst = {
428 "clk26m",
429 "axi_sel",
430 "dmpll_d2"
431 };
432
433 static const char * const scam_parents[] __initconst = {
434 "clk26m",
435 "syspll3_d2",
436 "univpll2_d4",
437 "dmpll_d4"
438 };
439
440 static const char * const spinfi_ifr_parents[] __initconst = {
441 "clk26m",
442 "univpll2_d8",
443 "univpll3_d4",
444 "syspll4_d2",
445 "univpll2_d4",
446 "univpll3_d2",
447 "syspll1_d4",
448 "univpll1_d4"
449 };
450
451 static const char * const hdmi_parents[] __initconst = {
452 "clk26m",
453 "hdmitx_dig_cts",
454 "hdmitxpll_d2",
455 "hdmitxpll_d3"
456 };
457
458 static const char * const dpilvds_parents[] __initconst = {
459 "clk26m",
460 "lvdspll",
461 "lvdspll_d2",
462 "lvdspll_d4",
463 "lvdspll_d8",
464 "fpc_ck"
465 };
466
467 static const char * const msdc50_2_h_parents[] __initconst = {
468 "clk26m",
469 "syspll1_d2",
470 "syspll2_d2",
471 "syspll4_d2",
472 "univpll_d5",
473 "univpll1_d4"
474 };
475
476 static const char * const hdcp_parents[] __initconst = {
477 "clk26m",
478 "syspll4_d2",
479 "syspll3_d4",
480 "univpll2_d4"
481 };
482
483 static const char * const hdcp_24m_parents[] __initconst = {
484 "clk26m",
485 "univpll_d26",
486 "univpll_d52",
487 "univpll2_d8"
488 };
489
490 static const char * const rtc_parents[] __initconst = {
491 "clkrtc_int",
492 "clkrtc_ext",
493 "clk26m",
494 "univpll3_d8"
495 };
496
497 static const char * const i2s0_m_ck_parents[] __initconst = {
498 "apll1_div1",
499 "apll2_div1"
500 };
501
502 static const char * const i2s1_m_ck_parents[] __initconst = {
503 "apll1_div2",
504 "apll2_div2"
505 };
506
507 static const char * const i2s2_m_ck_parents[] __initconst = {
508 "apll1_div3",
509 "apll2_div3"
510 };
511
512 static const char * const i2s3_m_ck_parents[] __initconst = {
513 "apll1_div4",
514 "apll2_div4"
515 };
516
517 static const char * const i2s3_b_ck_parents[] __initconst = {
518 "apll1_div5",
519 "apll2_div5"
520 };
521
522 static const char * const ca53_parents[] __initconst = {
523 "clk26m",
524 "armca7pll",
525 "mainpll",
526 "univpll"
527 };
528
529 static const char * const ca72_parents[] __initconst = {
530 "clk26m",
531 "armca15pll",
532 "mainpll",
533 "univpll"
534 };
535
536 static const struct mtk_composite cpu_muxes[] __initconst = {
537 MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
538 MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2),
539 };
540
541 static const struct mtk_composite top_muxes[] __initconst = {
542 /* CLK_CFG_0 */
543 MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
544 MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1),
545 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),
546 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
547 /* CLK_CFG_1 */
548 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
549 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
550 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23),
551 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31),
552 /* CLK_CFG_2 */
553 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7),
554 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
555 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
556 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31),
557 /* CLK_CFG_3 */
558 MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7),
559 MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 0x0070, 8, 3, 15),
560 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x0070, 16, 4, 23),
561 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x0070, 24, 3, 31),
562 /* CLK_CFG_4 */
563 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x0080, 0, 3, 7),
564 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 0x0080, 8, 4, 15),
565 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0080, 16, 2, 23),
566 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x0080, 24, 3, 31),
567 /* CLK_CFG_5 */
568 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0090, 0, 3, 7 /* 7:5 */),
569 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15),
570 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
571 MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31),
572 /* CLK_CFG_6 */
573 /*
574 * The dpi0_sel clock should not propagate rate changes to its parent
575 * clock so the dpi driver can have full control over PLL and divider.
576 */
577 MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7, 0),
578 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
579 MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23),
580 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
581 /* CLK_CFG_7 */
582 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),
583 MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel", mem_mfg_in_parents, 0x00b0, 8, 2, 15),
584 MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents, 0x00b0, 16, 2, 23),
585 MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31),
586 /* CLK_CFG_12 */
587 MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents, 0x00c0, 0, 3, 7),
588 MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15),
589 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0, 24, 3, 31),
590 /* CLK_CFG_13 */
591 MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7),
592 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15),
593 MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 0x00d0, 16, 2, 23),
594 MUX(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2),
595
596 DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24),
597 DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),
598 DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2", "aud_1_sel", 0x12c, 10, 0x124, 8, 8),
599 DIV_GATE(CLK_TOP_APLL1_DIV3, "apll1_div3", "aud_1_sel", 0x12c, 11, 0x124, 8, 16),
600 DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24),
601 DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5", "apll1_div4", 0x12c, 13, 0x12c, 4, 0),
602
603 DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
604 DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),
605 DIV_GATE(CLK_TOP_APLL2_DIV2, "apll2_div2", "aud_2_sel", 0x12c, 18, 0x128, 8, 8),
606 DIV_GATE(CLK_TOP_APLL2_DIV3, "apll2_div3", "aud_2_sel", 0x12c, 19, 0x128, 8, 16),
607 DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4", "aud_2_sel", 0x12c, 20, 0x128, 8, 24),
608 DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c, 4, 4),
609
610 MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x120, 4, 1),
611 MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 0x120, 5, 1),
612 MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 0x120, 6, 1),
613 MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 0x120, 7, 1),
614 MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1),
615 };
616
617 static const struct mtk_gate_regs infra_cg_regs __initconst = {
618 .set_ofs = 0x0040,
619 .clr_ofs = 0x0044,
620 .sta_ofs = 0x0048,
621 };
622
623 #define GATE_ICG(_id, _name, _parent, _shift) { \
624 .id = _id, \
625 .name = _name, \
626 .parent_name = _parent, \
627 .regs = &infra_cg_regs, \
628 .shift = _shift, \
629 .ops = &mtk_clk_gate_ops_setclr, \
630 }
631
632 static const struct mtk_gate infra_clks[] __initconst = {
633 GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
634 GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1),
635 GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5),
636 GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
637 GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7),
638 GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
639 GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15),
640 GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
641 GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18),
642 GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22),
643 GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23),
644 };
645
646 static const struct mtk_fixed_factor infra_divs[] __initconst = {
647 FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
648 };
649
650 static const struct mtk_gate_regs peri0_cg_regs __initconst = {
651 .set_ofs = 0x0008,
652 .clr_ofs = 0x0010,
653 .sta_ofs = 0x0018,
654 };
655
656 static const struct mtk_gate_regs peri1_cg_regs __initconst = {
657 .set_ofs = 0x000c,
658 .clr_ofs = 0x0014,
659 .sta_ofs = 0x001c,
660 };
661
662 #define GATE_PERI0(_id, _name, _parent, _shift) { \
663 .id = _id, \
664 .name = _name, \
665 .parent_name = _parent, \
666 .regs = &peri0_cg_regs, \
667 .shift = _shift, \
668 .ops = &mtk_clk_gate_ops_setclr, \
669 }
670
671 #define GATE_PERI1(_id, _name, _parent, _shift) { \
672 .id = _id, \
673 .name = _name, \
674 .parent_name = _parent, \
675 .regs = &peri1_cg_regs, \
676 .shift = _shift, \
677 .ops = &mtk_clk_gate_ops_setclr, \
678 }
679
680 static const struct mtk_gate peri_gates[] __initconst = {
681 /* PERI0 */
682 GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0),
683 GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1),
684 GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
685 GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
686 GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
687 GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
688 GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
689 GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
690 GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
691 GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9),
692 GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10),
693 GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11),
694 GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12),
695 GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13),
696 GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14),
697 GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15),
698 GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16),
699 GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17),
700 GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18),
701 GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
702 GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
703 GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),
704 GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22),
705 GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23),
706 GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24),
707 GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25),
708 GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26),
709 GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27),
710 GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28),
711 GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29),
712 GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30),
713 GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31),
714 /* PERI1 */
715 GATE_PERI1(CLK_PERI_SPI, "peri_spi", "spi_sel", 0),
716 GATE_PERI1(CLK_PERI_IRRX, "peri_irrx", "spi_sel", 1),
717 GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2),
718 };
719
720 static const char * const uart_ck_sel_parents[] __initconst = {
721 "clk26m",
722 "uart_sel",
723 };
724
725 static const struct mtk_composite peri_clks[] __initconst = {
726 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
727 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
728 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
729 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
730 };
731
732 static const struct mtk_gate_regs cg_regs_4_8_0 __initconst = {
733 .set_ofs = 0x0004,
734 .clr_ofs = 0x0008,
735 .sta_ofs = 0x0000,
736 };
737
738 #define GATE_IMG(_id, _name, _parent, _shift) { \
739 .id = _id, \
740 .name = _name, \
741 .parent_name = _parent, \
742 .regs = &cg_regs_4_8_0, \
743 .shift = _shift, \
744 .ops = &mtk_clk_gate_ops_setclr, \
745 }
746
747 static const struct mtk_gate img_clks[] __initconst = {
748 GATE_IMG(CLK_IMG_LARB2_SMI, "img_larb2_smi", "mm_sel", 0),
749 GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "mm_sel", 5),
750 GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "mm_sel", 6),
751 GATE_IMG(CLK_IMG_SEN_TG, "img_sen_tg", "camtg_sel", 7),
752 GATE_IMG(CLK_IMG_SEN_CAM, "img_sen_cam", "mm_sel", 8),
753 GATE_IMG(CLK_IMG_CAM_SV, "img_cam_sv", "mm_sel", 9),
754 GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11),
755 };
756
757 static const struct mtk_gate_regs vdec0_cg_regs __initconst = {
758 .set_ofs = 0x0000,
759 .clr_ofs = 0x0004,
760 .sta_ofs = 0x0000,
761 };
762
763 static const struct mtk_gate_regs vdec1_cg_regs __initconst = {
764 .set_ofs = 0x0008,
765 .clr_ofs = 0x000c,
766 .sta_ofs = 0x0008,
767 };
768
769 #define GATE_VDEC0(_id, _name, _parent, _shift) { \
770 .id = _id, \
771 .name = _name, \
772 .parent_name = _parent, \
773 .regs = &vdec0_cg_regs, \
774 .shift = _shift, \
775 .ops = &mtk_clk_gate_ops_setclr_inv, \
776 }
777
778 #define GATE_VDEC1(_id, _name, _parent, _shift) { \
779 .id = _id, \
780 .name = _name, \
781 .parent_name = _parent, \
782 .regs = &vdec1_cg_regs, \
783 .shift = _shift, \
784 .ops = &mtk_clk_gate_ops_setclr_inv, \
785 }
786
787 static const struct mtk_gate vdec_clks[] __initconst = {
788 GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
789 GATE_VDEC1(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", 0),
790 };
791
792 #define GATE_VENC(_id, _name, _parent, _shift) { \
793 .id = _id, \
794 .name = _name, \
795 .parent_name = _parent, \
796 .regs = &cg_regs_4_8_0, \
797 .shift = _shift, \
798 .ops = &mtk_clk_gate_ops_setclr_inv, \
799 }
800
801 static const struct mtk_gate venc_clks[] __initconst = {
802 GATE_VENC(CLK_VENC_CKE0, "venc_cke0", "mm_sel", 0),
803 GATE_VENC(CLK_VENC_CKE1, "venc_cke1", "venc_sel", 4),
804 GATE_VENC(CLK_VENC_CKE2, "venc_cke2", "venc_sel", 8),
805 GATE_VENC(CLK_VENC_CKE3, "venc_cke3", "venc_sel", 12),
806 };
807
808 #define GATE_VENCLT(_id, _name, _parent, _shift) { \
809 .id = _id, \
810 .name = _name, \
811 .parent_name = _parent, \
812 .regs = &cg_regs_4_8_0, \
813 .shift = _shift, \
814 .ops = &mtk_clk_gate_ops_setclr_inv, \
815 }
816
817 static const struct mtk_gate venclt_clks[] __initconst = {
818 GATE_VENCLT(CLK_VENCLT_CKE0, "venclt_cke0", "mm_sel", 0),
819 GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
820 };
821
822 static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
823 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
824
825 static const struct mtk_clk_rst_desc clk_rst_desc[] = {
826 /* infrasys */
827 {
828 .version = MTK_RST_SIMPLE,
829 .rst_bank_ofs = infrasys_rst_ofs,
830 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
831 },
832 /* pericfg */
833 {
834 .version = MTK_RST_SIMPLE,
835 .rst_bank_ofs = pericfg_rst_ofs,
836 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
837 }
838 };
839
840 static struct clk_hw_onecell_data *mt8173_top_clk_data __initdata;
841 static struct clk_hw_onecell_data *mt8173_pll_clk_data __initdata;
842
mtk_clk_enable_critical(void)843 static void __init mtk_clk_enable_critical(void)
844 {
845 if (!mt8173_top_clk_data || !mt8173_pll_clk_data)
846 return;
847
848 clk_prepare_enable(mt8173_pll_clk_data->hws[CLK_APMIXED_ARMCA15PLL]->clk);
849 clk_prepare_enable(mt8173_pll_clk_data->hws[CLK_APMIXED_ARMCA7PLL]->clk);
850 clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_MEM_SEL]->clk);
851 clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);
852 clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_CCI400_SEL]->clk);
853 clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_RTC_SEL]->clk);
854 }
855
mtk_topckgen_init(struct device_node * node)856 static void __init mtk_topckgen_init(struct device_node *node)
857 {
858 struct clk_hw_onecell_data *clk_data;
859 void __iomem *base;
860 int r;
861
862 base = of_iomap(node, 0);
863 if (!base) {
864 pr_err("%s(): ioremap failed\n", __func__);
865 return;
866 }
867
868 mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
869
870 mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data);
871 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
872 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
873 &mt8173_clk_lock, clk_data);
874
875 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
876 if (r)
877 pr_err("%s(): could not register clock provider: %d\n",
878 __func__, r);
879
880 mtk_clk_enable_critical();
881 }
882 CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init);
883
mtk_infrasys_init(struct device_node * node)884 static void __init mtk_infrasys_init(struct device_node *node)
885 {
886 struct clk_hw_onecell_data *clk_data;
887 int r;
888
889 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
890
891 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
892 clk_data);
893 mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
894
895 mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
896 clk_data);
897
898 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
899 if (r)
900 pr_err("%s(): could not register clock provider: %d\n",
901 __func__, r);
902
903 mtk_register_reset_controller(node, &clk_rst_desc[0]);
904 }
905 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
906
mtk_pericfg_init(struct device_node * node)907 static void __init mtk_pericfg_init(struct device_node *node)
908 {
909 struct clk_hw_onecell_data *clk_data;
910 int r;
911 void __iomem *base;
912
913 base = of_iomap(node, 0);
914 if (!base) {
915 pr_err("%s(): ioremap failed\n", __func__);
916 return;
917 }
918
919 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
920
921 mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
922 clk_data);
923 mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
924 &mt8173_clk_lock, clk_data);
925
926 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
927 if (r)
928 pr_err("%s(): could not register clock provider: %d\n",
929 __func__, r);
930
931 mtk_register_reset_controller(node, &clk_rst_desc[1]);
932 }
933 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
934
935 struct mtk_clk_usb {
936 int id;
937 const char *name;
938 const char *parent;
939 u32 reg_ofs;
940 };
941
942 #define APMIXED_USB(_id, _name, _parent, _reg_ofs) { \
943 .id = _id, \
944 .name = _name, \
945 .parent = _parent, \
946 .reg_ofs = _reg_ofs, \
947 }
948
949 static const struct mtk_clk_usb apmixed_usb[] __initconst = {
950 APMIXED_USB(CLK_APMIXED_REF2USB_TX, "ref2usb_tx", "clk26m", 0x8),
951 };
952
953 #define MT8173_PLL_FMAX (3000UL * MHZ)
954
955 #define CON0_MT8173_RST_BAR BIT(24)
956
957 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
958 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
959 _pcw_shift, _div_table) { \
960 .id = _id, \
961 .name = _name, \
962 .reg = _reg, \
963 .pwr_reg = _pwr_reg, \
964 .en_mask = _en_mask, \
965 .flags = _flags, \
966 .rst_bar_mask = CON0_MT8173_RST_BAR, \
967 .fmax = MT8173_PLL_FMAX, \
968 .pcwbits = _pcwbits, \
969 .pd_reg = _pd_reg, \
970 .pd_shift = _pd_shift, \
971 .tuner_reg = _tuner_reg, \
972 .pcw_reg = _pcw_reg, \
973 .pcw_shift = _pcw_shift, \
974 .div_table = _div_table, \
975 }
976
977 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
978 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
979 _pcw_shift) \
980 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
981 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
982 NULL)
983
984 static const struct mtk_pll_div_table mmpll_div_table[] = {
985 { .div = 0, .freq = MT8173_PLL_FMAX },
986 { .div = 1, .freq = 1000000000 },
987 { .div = 2, .freq = 702000000 },
988 { .div = 3, .freq = 253500000 },
989 { .div = 4, .freq = 126750000 },
990 { } /* sentinel */
991 };
992
993 static const struct mtk_pll_data plls[] = {
994 PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, 0, 21, 0x204, 24, 0x0, 0x204, 0),
995 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, 0, 21, 0x214, 24, 0x0, 0x214, 0),
996 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
997 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
998 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table),
999 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
1000 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
1001 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
1002 PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),
1003 PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0, 0, 21, 0x290, 4, 0x0, 0x294, 0),
1004 PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
1005 PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
1006 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
1007 PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
1008 };
1009
mtk_apmixedsys_init(struct device_node * node)1010 static void __init mtk_apmixedsys_init(struct device_node *node)
1011 {
1012 struct clk_hw_onecell_data *clk_data;
1013 void __iomem *base;
1014 struct clk_hw *hw;
1015 int r, i;
1016
1017 base = of_iomap(node, 0);
1018 if (!base) {
1019 pr_err("%s(): ioremap failed\n", __func__);
1020 return;
1021 }
1022
1023 mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1024 if (!clk_data) {
1025 iounmap(base);
1026 return;
1027 }
1028
1029 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1030
1031 for (i = 0; i < ARRAY_SIZE(apmixed_usb); i++) {
1032 const struct mtk_clk_usb *cku = &apmixed_usb[i];
1033
1034 hw = mtk_clk_register_ref2usb_tx(cku->name, cku->parent, base + cku->reg_ofs);
1035 if (IS_ERR(hw)) {
1036 pr_err("Failed to register clk %s: %ld\n", cku->name, PTR_ERR(hw));
1037 continue;
1038 }
1039
1040 clk_data->hws[cku->id] = hw;
1041 }
1042
1043 hw = clk_hw_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
1044 base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,
1045 NULL);
1046 clk_data->hws[CLK_APMIXED_HDMI_REF] = hw;
1047
1048 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1049 if (r)
1050 pr_err("%s(): could not register clock provider: %d\n",
1051 __func__, r);
1052
1053 mtk_clk_enable_critical();
1054 }
1055 CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
1056 mtk_apmixedsys_init);
1057
mtk_imgsys_init(struct device_node * node)1058 static void __init mtk_imgsys_init(struct device_node *node)
1059 {
1060 struct clk_hw_onecell_data *clk_data;
1061 int r;
1062
1063 clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
1064
1065 mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
1066 clk_data);
1067
1068 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1069
1070 if (r)
1071 pr_err("%s(): could not register clock provider: %d\n",
1072 __func__, r);
1073 }
1074 CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init);
1075
mtk_vdecsys_init(struct device_node * node)1076 static void __init mtk_vdecsys_init(struct device_node *node)
1077 {
1078 struct clk_hw_onecell_data *clk_data;
1079 int r;
1080
1081 clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
1082
1083 mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
1084 clk_data);
1085
1086 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1087 if (r)
1088 pr_err("%s(): could not register clock provider: %d\n",
1089 __func__, r);
1090 }
1091 CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8173-vdecsys", mtk_vdecsys_init);
1092
mtk_vencsys_init(struct device_node * node)1093 static void __init mtk_vencsys_init(struct device_node *node)
1094 {
1095 struct clk_hw_onecell_data *clk_data;
1096 int r;
1097
1098 clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
1099
1100 mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
1101 clk_data);
1102
1103 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1104 if (r)
1105 pr_err("%s(): could not register clock provider: %d\n",
1106 __func__, r);
1107 }
1108 CLK_OF_DECLARE(mtk_vencsys, "mediatek,mt8173-vencsys", mtk_vencsys_init);
1109
mtk_vencltsys_init(struct device_node * node)1110 static void __init mtk_vencltsys_init(struct device_node *node)
1111 {
1112 struct clk_hw_onecell_data *clk_data;
1113 int r;
1114
1115 clk_data = mtk_alloc_clk_data(CLK_VENCLT_NR_CLK);
1116
1117 mtk_clk_register_gates(node, venclt_clks, ARRAY_SIZE(venclt_clks),
1118 clk_data);
1119
1120 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1121 if (r)
1122 pr_err("%s(): could not register clock provider: %d\n",
1123 __func__, r);
1124 }
1125 CLK_OF_DECLARE(mtk_vencltsys, "mediatek,mt8173-vencltsys", mtk_vencltsys_init);
1126
