1 // SPDX-License-Identifier: GPL-2.0-only
16 #include "clk-gate.h"
17 #include "clk-pll.h"
18 #include "clk-mtk.h"
20 #include <dt-bindings/clock/mt2712-clk.h>
40 	FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1,
42 	FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1,
47 	FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1,
49 	FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1,
51 	FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1,
53 	FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1,
55 	FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1,
57 	FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
59 	FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1,
61 	FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1,
63 	FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1,
65 	FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1,
67 	FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1,
69 	FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1,
71 	FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1,
73 	FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1,
75 	FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
77 	FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1,
79 	FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1,
81 	FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1,
83 	FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1,
85 	FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1,
87 	FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1,
89 	FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1,
91 	FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1,
93 	FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1,
95 	FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1,
97 	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
99 	FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1,
101 	FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1,
103 	FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1,
105 	FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1,
107 	FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1,
109 	FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
111 	FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1,
113 	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1,
115 	FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1,
117 	FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1,
119 	FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1,
121 	FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1,
123 	FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1,
125 	FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1,
127 	FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1,
129 	FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1,
131 	FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1,
133 	FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1,
135 	FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1,
137 	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1,
139 	FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1,
141 	FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1,
143 	FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1,
145 	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1,
147 	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1,
149 	FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1,
151 	FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1,
153 	FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1,
155 	FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1,
157 	FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1,
159 	FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1,
161 	FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1,
163 	FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1,
165 	FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1,
167 	FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1,
169 	FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1,
171 	FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1,
173 	FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1,
175 	FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1,
177 	FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1,
179 	FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1,
181 	FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1,
183 	FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1,
185 	FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1,
187 	FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1,
189 	FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1,
191 	FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
193 	FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1,
195 	FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1,
197 	FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1,
199 	FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1,
201 	FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1,
203 	FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1,
205 	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1,
207 	FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1,
209 	FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1,
211 	FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1,
213 	FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1,
215 	FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1,
217 	FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1,
219 	FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1,
929 		9, 2, -1, CLK_IS_CRITICAL),
932 		9, 2, -1, CLK_IS_CRITICAL),
935 		9, 2, -1, CLK_IS_CRITICAL),
1283 	struct device_node *node = pdev->dev.of_node;  in clk_mt2712_apmixed_probe()
1292 		pr_err("%s(): could not register clock provider: %d\n",  in clk_mt2712_apmixed_probe()
1308 			top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);  in clk_mt2712_top_init_early()
1316 		pr_err("%s(): could not register clock provider: %d\n",  in clk_mt2712_top_init_early()
1320 CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen",
1326 	struct device_node *node = pdev->dev.of_node;  in clk_mt2712_top_probe()
1331 		pr_err("%s(): ioremap failed\n", __func__);  in clk_mt2712_top_probe()
1339 			if (top_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))  in clk_mt2712_top_probe()
1340 				top_clk_data->hws[i] = ERR_PTR(-ENOENT);  in clk_mt2712_top_probe()
1359 		pr_err("%s(): could not register clock provider: %d\n",  in clk_mt2712_top_probe()
1369 	struct device_node *node = pdev->dev.of_node;  in clk_mt2712_infra_probe()
1379 		pr_err("%s(): could not register clock provider: %d\n",  in clk_mt2712_infra_probe()
1382 	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);  in clk_mt2712_infra_probe()
1391 	struct device_node *node = pdev->dev.of_node;  in clk_mt2712_peri_probe()
1401 		pr_err("%s(): could not register clock provider: %d\n",  in clk_mt2712_peri_probe()
1404 	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);  in clk_mt2712_peri_probe()
1413 	struct device_node *node = pdev->dev.of_node;  in clk_mt2712_mcu_probe()
1418 		pr_err("%s(): ioremap failed\n", __func__);  in clk_mt2712_mcu_probe()
1430 		pr_err("%s(): could not register clock provider: %d\n",  in clk_mt2712_mcu_probe()
1438 		.compatible = "mediatek,mt2712-apmixedsys",
1441 		.compatible = "mediatek,mt2712-topckgen",
1444 		.compatible = "mediatek,mt2712-infracfg",
1447 		.compatible = "mediatek,mt2712-pericfg",
1450 		.compatible = "mediatek,mt2712-mcucfg",
1462 	clk_probe = of_device_get_match_data(&pdev->dev);  in clk_mt2712_probe()
1464 		return -EINVAL;  in clk_mt2712_probe()
1468 		dev_err(&pdev->dev,  in clk_mt2712_probe()
1469 			"could not register clock provider: %s: %d\n",  in clk_mt2712_probe()
1470 			pdev->name, r);  in clk_mt2712_probe()
1478 		.name = "clk-mt2712",