1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: James Liao <jamesjj.liao@mediatek.com>
5 * Fabien Parent <fparent@baylibre.com>
6 */
7
8 #include <linux/delay.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/slab.h>
12 #include <linux/mfd/syscon.h>
13
14 #include "clk-gate.h"
15 #include "clk-mtk.h"
16 #include "clk-pll.h"
17
18 #include <dt-bindings/clock/mt8516-clk.h>
19
20 static DEFINE_SPINLOCK(mt8516_clk_lock);
21
22 static const struct mtk_fixed_clk fixed_clks[] __initconst = {
23 FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
24 FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000),
25 FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000),
26 };
27
28 static const struct mtk_fixed_factor top_divs[] __initconst = {
29 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
30 FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
31 FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
32 FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8),
33 FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16),
34 FACTOR(CLK_TOP_MAINPLL_D11, "mainpll_d11", "mainpll", 1, 11),
35 FACTOR(CLK_TOP_MAINPLL_D22, "mainpll_d22", "mainpll", 1, 22),
36 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
37 FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
38 FACTOR(CLK_TOP_MAINPLL_D12, "mainpll_d12", "mainpll", 1, 12),
39 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
40 FACTOR(CLK_TOP_MAINPLL_D10, "mainpll_d10", "mainpll", 1, 10),
41 FACTOR(CLK_TOP_MAINPLL_D20, "mainpll_d20", "mainpll", 1, 20),
42 FACTOR(CLK_TOP_MAINPLL_D40, "mainpll_d40", "mainpll", 1, 40),
43 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
44 FACTOR(CLK_TOP_MAINPLL_D14, "mainpll_d14", "mainpll", 1, 14),
45 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
46 FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
47 FACTOR(CLK_TOP_UNIVPLL_D8, "univpll_d8", "univpll", 1, 8),
48 FACTOR(CLK_TOP_UNIVPLL_D16, "univpll_d16", "univpll", 1, 16),
49 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
50 FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
51 FACTOR(CLK_TOP_UNIVPLL_D12, "univpll_d12", "univpll", 1, 12),
52 FACTOR(CLK_TOP_UNIVPLL_D24, "univpll_d24", "univpll", 1, 24),
53 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
54 FACTOR(CLK_TOP_UNIVPLL_D20, "univpll_d20", "univpll", 1, 20),
55 FACTOR(CLK_TOP_MMPLL380M, "mmpll380m", "mmpll", 1, 1),
56 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
57 FACTOR(CLK_TOP_MMPLL_200M, "mmpll_200m", "mmpll", 1, 3),
58 FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
59 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
60 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
61 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "rg_apll1_d2_en", 1, 2),
62 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "rg_apll1_d4_en", 1, 2),
63 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
64 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
65 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
66 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "rg_apll2_d4_en", 1, 2),
67 FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1),
68 FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
69 FACTOR(CLK_TOP_AHB_INFRA_D2, "ahb_infra_d2", "ahb_infra_sel", 1, 2),
70 FACTOR(CLK_TOP_NFI1X, "nfi1x_ck", "nfi2x_pad_sel", 1, 2),
71 FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2),
72 };
73
74 static const char * const uart0_parents[] __initconst = {
75 "clk26m_ck",
76 "univpll_d24"
77 };
78
79 static const char * const ahb_infra_parents[] __initconst = {
80 "clk_null",
81 "clk26m_ck",
82 "mainpll_d11",
83 "clk_null",
84 "mainpll_d12",
85 "clk_null",
86 "clk_null",
87 "clk_null",
88 "clk_null",
89 "clk_null",
90 "clk_null",
91 "clk_null",
92 "mainpll_d10"
93 };
94
95 static const char * const msdc0_parents[] __initconst = {
96 "clk26m_ck",
97 "univpll_d6",
98 "mainpll_d8",
99 "univpll_d8",
100 "mainpll_d16",
101 "mmpll_200m",
102 "mainpll_d12",
103 "mmpll_d2"
104 };
105
106 static const char * const uart1_parents[] __initconst = {
107 "clk26m_ck",
108 "univpll_d24"
109 };
110
111 static const char * const msdc1_parents[] __initconst = {
112 "clk26m_ck",
113 "univpll_d6",
114 "mainpll_d8",
115 "univpll_d8",
116 "mainpll_d16",
117 "mmpll_200m",
118 "mainpll_d12",
119 "mmpll_d2"
120 };
121
122 static const char * const pmicspi_parents[] __initconst = {
123 "univpll_d20",
124 "usb_phy48m_ck",
125 "univpll_d16",
126 "clk26m_ck"
127 };
128
129 static const char * const qaxi_aud26m_parents[] __initconst = {
130 "clk26m_ck",
131 "ahb_infra_sel"
132 };
133
134 static const char * const aud_intbus_parents[] __initconst = {
135 "clk_null",
136 "clk26m_ck",
137 "mainpll_d22",
138 "clk_null",
139 "mainpll_d11"
140 };
141
142 static const char * const nfi2x_pad_parents[] __initconst = {
143 "clk_null",
144 "clk_null",
145 "clk_null",
146 "clk_null",
147 "clk_null",
148 "clk_null",
149 "clk_null",
150 "clk_null",
151 "clk26m_ck",
152 "clk_null",
153 "clk_null",
154 "clk_null",
155 "clk_null",
156 "clk_null",
157 "clk_null",
158 "clk_null",
159 "clk_null",
160 "mainpll_d12",
161 "mainpll_d8",
162 "clk_null",
163 "mainpll_d6",
164 "clk_null",
165 "clk_null",
166 "clk_null",
167 "clk_null",
168 "clk_null",
169 "clk_null",
170 "clk_null",
171 "clk_null",
172 "clk_null",
173 "clk_null",
174 "clk_null",
175 "mainpll_d4",
176 "clk_null",
177 "clk_null",
178 "clk_null",
179 "clk_null",
180 "clk_null",
181 "clk_null",
182 "clk_null",
183 "clk_null",
184 "clk_null",
185 "clk_null",
186 "clk_null",
187 "clk_null",
188 "clk_null",
189 "clk_null",
190 "clk_null",
191 "clk_null",
192 "clk_null",
193 "clk_null",
194 "clk_null",
195 "clk_null",
196 "clk_null",
197 "clk_null",
198 "clk_null",
199 "clk_null",
200 "clk_null",
201 "clk_null",
202 "clk_null",
203 "clk_null",
204 "clk_null",
205 "clk_null",
206 "clk_null",
207 "clk_null",
208 "clk_null",
209 "clk_null",
210 "clk_null",
211 "clk_null",
212 "clk_null",
213 "clk_null",
214 "clk_null",
215 "clk_null",
216 "clk_null",
217 "clk_null",
218 "clk_null",
219 "clk_null",
220 "clk_null",
221 "clk_null",
222 "clk_null",
223 "clk_null",
224 "mainpll_d10",
225 "mainpll_d7",
226 "clk_null",
227 "mainpll_d5"
228 };
229
230 static const char * const nfi1x_pad_parents[] __initconst = {
231 "ahb_infra_sel",
232 "nfi1x_ck"
233 };
234
235 static const char * const usb_78m_parents[] __initconst = {
236 "clk_null",
237 "clk26m_ck",
238 "univpll_d16",
239 "clk_null",
240 "mainpll_d20"
241 };
242
243 static const char * const spinor_parents[] __initconst = {
244 "clk26m_d2",
245 "clk26m_ck",
246 "mainpll_d40",
247 "univpll_d24",
248 "univpll_d20",
249 "mainpll_d20",
250 "mainpll_d16",
251 "univpll_d12"
252 };
253
254 static const char * const msdc2_parents[] __initconst = {
255 "clk26m_ck",
256 "univpll_d6",
257 "mainpll_d8",
258 "univpll_d8",
259 "mainpll_d16",
260 "mmpll_200m",
261 "mainpll_d12",
262 "mmpll_d2"
263 };
264
265 static const char * const eth_parents[] __initconst = {
266 "clk26m_ck",
267 "mainpll_d40",
268 "univpll_d24",
269 "univpll_d20",
270 "mainpll_d20"
271 };
272
273 static const char * const aud1_parents[] __initconst = {
274 "clk26m_ck",
275 "apll1_ck"
276 };
277
278 static const char * const aud2_parents[] __initconst = {
279 "clk26m_ck",
280 "apll2_ck"
281 };
282
283 static const char * const aud_engen1_parents[] __initconst = {
284 "clk26m_ck",
285 "rg_apll1_d2_en",
286 "rg_apll1_d4_en",
287 "rg_apll1_d8_en"
288 };
289
290 static const char * const aud_engen2_parents[] __initconst = {
291 "clk26m_ck",
292 "rg_apll2_d2_en",
293 "rg_apll2_d4_en",
294 "rg_apll2_d8_en"
295 };
296
297 static const char * const i2c_parents[] __initconst = {
298 "clk26m_ck",
299 "univpll_d20",
300 "univpll_d16",
301 "univpll_d12"
302 };
303
304 static const char * const aud_i2s0_m_parents[] __initconst = {
305 "rg_aud1",
306 "rg_aud2"
307 };
308
309 static const char * const pwm_parents[] __initconst = {
310 "clk26m_ck",
311 "univpll_d12"
312 };
313
314 static const char * const spi_parents[] __initconst = {
315 "clk26m_ck",
316 "univpll_d12",
317 "univpll_d8",
318 "univpll_d6"
319 };
320
321 static const char * const aud_spdifin_parents[] __initconst = {
322 "clk26m_ck",
323 "univpll_d2"
324 };
325
326 static const char * const uart2_parents[] __initconst = {
327 "clk26m_ck",
328 "univpll_d24"
329 };
330
331 static const char * const bsi_parents[] __initconst = {
332 "clk26m_ck",
333 "mainpll_d10",
334 "mainpll_d12",
335 "mainpll_d20"
336 };
337
338 static const char * const dbg_atclk_parents[] __initconst = {
339 "clk_null",
340 "clk26m_ck",
341 "mainpll_d5",
342 "clk_null",
343 "univpll_d5"
344 };
345
346 static const char * const csw_nfiecc_parents[] __initconst = {
347 "clk_null",
348 "mainpll_d7",
349 "mainpll_d6",
350 "clk_null",
351 "mainpll_d5"
352 };
353
354 static const char * const nfiecc_parents[] __initconst = {
355 "clk_null",
356 "nfi2x_pad_sel",
357 "mainpll_d4",
358 "clk_null",
359 "csw_nfiecc_sel"
360 };
361
362 static struct mtk_composite top_muxes[] __initdata = {
363 /* CLK_MUX_SEL0 */
364 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
365 0x000, 0, 1),
366 MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
367 0x000, 4, 4),
368 MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
369 0x000, 11, 3),
370 MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
371 0x000, 19, 1),
372 MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
373 0x000, 20, 3),
374 MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
375 0x000, 24, 2),
376 MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
377 0x000, 26, 1),
378 MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
379 0x000, 27, 3),
380 /* CLK_MUX_SEL1 */
381 MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
382 0x004, 0, 7),
383 MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
384 0x004, 7, 1),
385 MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents,
386 0x004, 20, 3),
387 /* CLK_MUX_SEL8 */
388 MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents,
389 0x040, 0, 3),
390 MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents,
391 0x040, 3, 3),
392 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
393 0x040, 6, 3),
394 MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
395 0x040, 22, 1),
396 MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
397 0x040, 23, 1),
398 MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
399 0x040, 24, 2),
400 MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
401 0x040, 26, 2),
402 MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
403 0x040, 28, 2),
404 /* CLK_SEL_9 */
405 MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents,
406 0x044, 12, 1),
407 MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents,
408 0x044, 13, 1),
409 MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents,
410 0x044, 14, 1),
411 MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents,
412 0x044, 15, 1),
413 MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents,
414 0x044, 16, 1),
415 MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents,
416 0x044, 17, 1),
417 MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents,
418 0x044, 18, 1),
419 /* CLK_MUX_SEL13 */
420 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
421 0x07c, 0, 1),
422 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
423 0x07c, 1, 2),
424 MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents,
425 0x07c, 3, 1),
426 MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents,
427 0x07c, 4, 1),
428 MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents,
429 0x07c, 5, 2),
430 MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents,
431 0x07c, 7, 3),
432 MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents,
433 0x07c, 10, 3),
434 MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
435 0x07c, 13, 3),
436 };
437
438 static const char * const ifr_mux1_parents[] __initconst = {
439 "clk26m_ck",
440 "armpll",
441 "univpll",
442 "mainpll_d2"
443 };
444
445 static const char * const ifr_eth_25m_parents[] __initconst = {
446 "eth_d2_ck",
447 "rg_eth"
448 };
449
450 static const char * const ifr_i2c0_parents[] __initconst = {
451 "ahb_infra_d2",
452 "rg_i2c"
453 };
454
455 static const struct mtk_composite ifr_muxes[] __initconst = {
456 MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
457 2, 2),
458 MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
459 0, 1),
460 MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
461 1, 1),
462 MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
463 2, 1),
464 MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,
465 3, 1),
466 };
467
468 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
469 .id = _id, \
470 .name = _name, \
471 .parent_name = _parent, \
472 .div_reg = _reg, \
473 .div_shift = _shift, \
474 .div_width = _width, \
475 }
476
477 static const struct mtk_clk_divider top_adj_divs[] = {
478 DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",
479 0x0048, 0, 8),
480 DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel",
481 0x0048, 8, 8),
482 DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
483 0x0048, 16, 8),
484 DIV_ADJ(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "aud_i2s3_m_sel",
485 0x0048, 24, 8),
486 DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel",
487 0x004c, 0, 8),
488 DIV_ADJ(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_div4",
489 0x004c, 8, 8),
490 DIV_ADJ(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "aud_i2s5_m_sel",
491 0x004c, 16, 8),
492 DIV_ADJ(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_div5",
493 0x004c, 24, 8),
494 DIV_ADJ(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "aud_spdif_b_sel",
495 0x0078, 0, 8),
496 };
497
498 static const struct mtk_gate_regs top1_cg_regs = {
499 .set_ofs = 0x54,
500 .clr_ofs = 0x84,
501 .sta_ofs = 0x24,
502 };
503
504 static const struct mtk_gate_regs top2_cg_regs = {
505 .set_ofs = 0x6c,
506 .clr_ofs = 0x9c,
507 .sta_ofs = 0x3c,
508 };
509
510 static const struct mtk_gate_regs top3_cg_regs = {
511 .set_ofs = 0xa0,
512 .clr_ofs = 0xb0,
513 .sta_ofs = 0x70,
514 };
515
516 static const struct mtk_gate_regs top4_cg_regs = {
517 .set_ofs = 0xa4,
518 .clr_ofs = 0xb4,
519 .sta_ofs = 0x74,
520 };
521
522 static const struct mtk_gate_regs top5_cg_regs = {
523 .set_ofs = 0x44,
524 .clr_ofs = 0x44,
525 .sta_ofs = 0x44,
526 };
527
528 #define GATE_TOP1(_id, _name, _parent, _shift) { \
529 .id = _id, \
530 .name = _name, \
531 .parent_name = _parent, \
532 .regs = &top1_cg_regs, \
533 .shift = _shift, \
534 .ops = &mtk_clk_gate_ops_setclr, \
535 }
536
537 #define GATE_TOP2(_id, _name, _parent, _shift) { \
538 .id = _id, \
539 .name = _name, \
540 .parent_name = _parent, \
541 .regs = &top2_cg_regs, \
542 .shift = _shift, \
543 .ops = &mtk_clk_gate_ops_setclr, \
544 }
545
546 #define GATE_TOP2_I(_id, _name, _parent, _shift) { \
547 .id = _id, \
548 .name = _name, \
549 .parent_name = _parent, \
550 .regs = &top2_cg_regs, \
551 .shift = _shift, \
552 .ops = &mtk_clk_gate_ops_setclr_inv, \
553 }
554
555 #define GATE_TOP3(_id, _name, _parent, _shift) { \
556 .id = _id, \
557 .name = _name, \
558 .parent_name = _parent, \
559 .regs = &top3_cg_regs, \
560 .shift = _shift, \
561 .ops = &mtk_clk_gate_ops_setclr, \
562 }
563
564 #define GATE_TOP4_I(_id, _name, _parent, _shift) { \
565 .id = _id, \
566 .name = _name, \
567 .parent_name = _parent, \
568 .regs = &top4_cg_regs, \
569 .shift = _shift, \
570 .ops = &mtk_clk_gate_ops_setclr_inv, \
571 }
572
573 #define GATE_TOP5(_id, _name, _parent, _shift) { \
574 .id = _id, \
575 .name = _name, \
576 .parent_name = _parent, \
577 .regs = &top5_cg_regs, \
578 .shift = _shift, \
579 .ops = &mtk_clk_gate_ops_no_setclr, \
580 }
581
582 static const struct mtk_gate top_clks[] __initconst = {
583 /* TOP1 */
584 GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1),
585 GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),
586 GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3),
587 GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4),
588 GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5),
589 GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6),
590 GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7),
591 GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8),
592 GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9),
593 GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10),
594 GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11),
595 GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12),
596 GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13),
597 GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14),
598 GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15),
599 GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16),
600 GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17),
601 GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18),
602 GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19),
603 GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20),
604 GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21),
605 GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22),
606 GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23),
607 GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24),
608 GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25),
609 GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27),
610 GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28),
611 GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29),
612 GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30),
613 GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31),
614 /* TOP2 */
615 GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
616 GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
617 GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
618 GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
619 GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
620 GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
621 GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
622 GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
623 GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
624 GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
625 GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
626 GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
627 GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
628 GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
629 GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
630 15),
631 GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
632 GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
633 GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
634 GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
635 GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
636 GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
637 GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
638 GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
639 GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, "msdc0_infra", "msdc0", 28),
640 GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, "msdc1_infra", "msdc1", 29),
641 GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, "msdc2_infra", "rg_msdc2", 30),
642 GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),
643 /* TOP3 */
644 GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0),
645 GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1),
646 GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2),
647 GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8),
648 GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9),
649 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10),
650 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11),
651 GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12),
652 GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13),
653 GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel",
654 14),
655 GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15),
656 GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16),
657 GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17),
658 GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18),
659 /* TOP4 */
660 GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, "rg_apll1_d2_en", "apll1_d2", 8),
661 GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, "rg_apll1_d4_en", "apll1_d4", 9),
662 GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, "rg_apll1_d8_en", "apll1_d8", 10),
663 GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, "rg_apll2_d2_en", "apll2_d2", 11),
664 GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, "rg_apll2_d4_en", "apll2_d4", 12),
665 GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, "rg_apll2_d8_en", "apll2_d8", 13),
666 /* TOP5 */
667 GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
668 GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1),
669 GATE_TOP5(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll12_ck_div2", 2),
670 GATE_TOP5(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll12_ck_div3", 3),
671 GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
672 GATE_TOP5(CLK_TOP_APLL12_DIV4B, "apll12_div4b", "apll12_ck_div4b", 5),
673 GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
674 GATE_TOP5(CLK_TOP_APLL12_DIV5B, "apll12_div5b", "apll12_ck_div5b", 7),
675 GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8),
676 };
677
mtk_topckgen_init(struct device_node * node)678 static void __init mtk_topckgen_init(struct device_node *node)
679 {
680 struct clk_hw_onecell_data *clk_data;
681 int r;
682 void __iomem *base;
683
684 base = of_iomap(node, 0);
685 if (!base) {
686 pr_err("%s(): ioremap failed\n", __func__);
687 return;
688 }
689
690 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
691
692 mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
693 clk_data);
694 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data);
695
696 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
697 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
698 &mt8516_clk_lock, clk_data);
699 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
700 base, &mt8516_clk_lock, clk_data);
701
702 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
703 if (r)
704 pr_err("%s(): could not register clock provider: %d\n",
705 __func__, r);
706 }
707 CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8516-topckgen", mtk_topckgen_init);
708
mtk_infracfg_init(struct device_node * node)709 static void __init mtk_infracfg_init(struct device_node *node)
710 {
711 struct clk_hw_onecell_data *clk_data;
712 int r;
713 void __iomem *base;
714
715 base = of_iomap(node, 0);
716 if (!base) {
717 pr_err("%s(): ioremap failed\n", __func__);
718 return;
719 }
720
721 clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
722
723 mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base,
724 &mt8516_clk_lock, clk_data);
725
726 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
727 if (r)
728 pr_err("%s(): could not register clock provider: %d\n",
729 __func__, r);
730 }
731 CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8516-infracfg", mtk_infracfg_init);
732
733 #define MT8516_PLL_FMAX (1502UL * MHZ)
734
735 #define CON0_MT8516_RST_BAR BIT(27)
736
737 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
738 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
739 _pcw_shift, _div_table) { \
740 .id = _id, \
741 .name = _name, \
742 .reg = _reg, \
743 .pwr_reg = _pwr_reg, \
744 .en_mask = _en_mask, \
745 .flags = _flags, \
746 .rst_bar_mask = CON0_MT8516_RST_BAR, \
747 .fmax = MT8516_PLL_FMAX, \
748 .pcwbits = _pcwbits, \
749 .pd_reg = _pd_reg, \
750 .pd_shift = _pd_shift, \
751 .tuner_reg = _tuner_reg, \
752 .pcw_reg = _pcw_reg, \
753 .pcw_shift = _pcw_shift, \
754 .div_table = _div_table, \
755 }
756
757 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
758 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
759 _pcw_shift) \
760 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
761 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
762 NULL)
763
764 static const struct mtk_pll_div_table mmpll_div_table[] = {
765 { .div = 0, .freq = MT8516_PLL_FMAX },
766 { .div = 1, .freq = 1000000000 },
767 { .div = 2, .freq = 604500000 },
768 { .div = 3, .freq = 253500000 },
769 { .div = 4, .freq = 126750000 },
770 { } /* sentinel */
771 };
772
773 static const struct mtk_pll_data plls[] = {
774 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0,
775 21, 0x0104, 24, 0, 0x0104, 0),
776 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0,
777 HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
778 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000,
779 HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
780 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0,
781 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
782 PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0,
783 31, 0x0180, 1, 0x0194, 0x0184, 0),
784 PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0,
785 31, 0x01A0, 1, 0x01B4, 0x01A4, 0),
786 };
787
mtk_apmixedsys_init(struct device_node * node)788 static void __init mtk_apmixedsys_init(struct device_node *node)
789 {
790 struct clk_hw_onecell_data *clk_data;
791 void __iomem *base;
792 int r;
793
794 base = of_iomap(node, 0);
795 if (!base) {
796 pr_err("%s(): ioremap failed\n", __func__);
797 return;
798 }
799
800 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
801
802 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
803
804 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
805 if (r)
806 pr_err("%s(): could not register clock provider: %d\n",
807 __func__, r);
808
809 }
810 CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8516-apmixedsys",
811 mtk_apmixedsys_init);
812
