Lines Matching +full:n +full:- +full:factor

1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include "clk-mtk.h"
14 #include "clk-gate.h"
15 #include "clk-mux.h"
17 #include <dt-bindings/clock/mt7986-clk.h>
29 	FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
30 	FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
31 	FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
33 	FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2),
34 	FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4),
35 	FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8),
36 	FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16),
37 	FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6),
39 	FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2),
40 	FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4),
41 	FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8),
42 	FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16),
43 	FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24),
44 	FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30),
46 	FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4),
48 	FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4),
49 	FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5),
50 	FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10),
51 	FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20),
52 	FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16),
53 	FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32),
55 	FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4),
56 	FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8),
57 	FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2),
59 	FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1,
287 	struct device_node *node = pdev->dev.of_node;  in clk_mt7986_topckgen_probe()
295 		pr_err("%s(): ioremap failed\n", __func__);  in clk_mt7986_topckgen_probe()
296 		return -ENOMEM;  in clk_mt7986_topckgen_probe()
301 		return -ENOMEM;  in clk_mt7986_topckgen_probe()
309 	clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);  in clk_mt7986_topckgen_probe()
310 	clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk);  in clk_mt7986_topckgen_probe()
311 	clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk);  in clk_mt7986_topckgen_probe()
312 	clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk);  in clk_mt7986_topckgen_probe()
313 	clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk);  in clk_mt7986_topckgen_probe()
314 	clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk);  in clk_mt7986_topckgen_probe()
319 		pr_err("%s(): could not register clock provider: %d\n",  in clk_mt7986_topckgen_probe()
331 	{ .compatible = "mediatek,mt7986-topckgen", },
338 		.name = "clk-mt7986-topckgen",