1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Copyright (c) 2020 BayLibre, SAS
5 * Author: James Liao <jamesjj.liao@mediatek.com>
6 * Fabien Parent <fparent@baylibre.com>
7 */
8
9 #include <linux/delay.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/slab.h>
13 #include <linux/mfd/syscon.h>
14
15 #include "clk-gate.h"
16 #include "clk-mtk.h"
17 #include "clk-pll.h"
18
19 #include <dt-bindings/clock/mt8167-clk.h>
20
21 static DEFINE_SPINLOCK(mt8167_clk_lock);
22
23 static const struct mtk_fixed_clk fixed_clks[] __initconst = {
24 FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
25 FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000),
26 FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000),
27 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m", 75000000),
28 FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", "clk26m", 75000000),
29 FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m", 52500000),
30 };
31
32 static const struct mtk_fixed_factor top_divs[] __initconst = {
33 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
34 FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
35 FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
36 FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8),
37 FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16),
38 FACTOR(CLK_TOP_MAINPLL_D11, "mainpll_d11", "mainpll", 1, 11),
39 FACTOR(CLK_TOP_MAINPLL_D22, "mainpll_d22", "mainpll", 1, 22),
40 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
41 FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
42 FACTOR(CLK_TOP_MAINPLL_D12, "mainpll_d12", "mainpll", 1, 12),
43 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
44 FACTOR(CLK_TOP_MAINPLL_D10, "mainpll_d10", "mainpll", 1, 10),
45 FACTOR(CLK_TOP_MAINPLL_D20, "mainpll_d20", "mainpll", 1, 20),
46 FACTOR(CLK_TOP_MAINPLL_D40, "mainpll_d40", "mainpll", 1, 40),
47 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
48 FACTOR(CLK_TOP_MAINPLL_D14, "mainpll_d14", "mainpll", 1, 14),
49 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
50 FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
51 FACTOR(CLK_TOP_UNIVPLL_D8, "univpll_d8", "univpll", 1, 8),
52 FACTOR(CLK_TOP_UNIVPLL_D16, "univpll_d16", "univpll", 1, 16),
53 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
54 FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
55 FACTOR(CLK_TOP_UNIVPLL_D12, "univpll_d12", "univpll", 1, 12),
56 FACTOR(CLK_TOP_UNIVPLL_D24, "univpll_d24", "univpll", 1, 24),
57 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
58 FACTOR(CLK_TOP_UNIVPLL_D20, "univpll_d20", "univpll", 1, 20),
59 FACTOR(CLK_TOP_MMPLL380M, "mmpll380m", "mmpll", 1, 1),
60 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
61 FACTOR(CLK_TOP_MMPLL_200M, "mmpll_200m", "mmpll", 1, 3),
62 FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, 1),
63 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
64 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
65 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
66 FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
67 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
68 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
69 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "rg_apll1_d2_en", 1, 2),
70 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "rg_apll1_d4_en", 1, 2),
71 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
72 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
73 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
74 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "rg_apll2_d4_en", 1, 2),
75 FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1),
76 FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
77 FACTOR(CLK_TOP_MIPI_26M, "mipi_26m", "clk26m", 1, 1),
78 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
79 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
80 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
81 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8),
82 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16),
83 FACTOR(CLK_TOP_AHB_INFRA_D2, "ahb_infra_d2", "ahb_infra_sel", 1, 2),
84 FACTOR(CLK_TOP_NFI1X, "nfi1x_ck", "nfi2x_pad_sel", 1, 2),
85 FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2),
86 };
87
88 static const char * const uart0_parents[] __initconst = {
89 "clk26m_ck",
90 "univpll_d24"
91 };
92
93 static const char * const gfmux_emi1x_parents[] __initconst = {
94 "clk26m_ck",
95 "dmpll_ck"
96 };
97
98 static const char * const emi_ddrphy_parents[] __initconst = {
99 "gfmux_emi1x_sel",
100 "gfmux_emi1x_sel"
101 };
102
103 static const char * const ahb_infra_parents[] __initconst = {
104 "clk_null",
105 "clk26m_ck",
106 "mainpll_d11",
107 "clk_null",
108 "mainpll_d12",
109 "clk_null",
110 "clk_null",
111 "clk_null",
112 "clk_null",
113 "clk_null",
114 "clk_null",
115 "clk_null",
116 "mainpll_d10"
117 };
118
119 static const char * const csw_mux_mfg_parents[] __initconst = {
120 "clk_null",
121 "clk_null",
122 "univpll_d3",
123 "univpll_d2",
124 "clk26m_ck",
125 "mainpll_d4",
126 "univpll_d24",
127 "mmpll380m"
128 };
129
130 static const char * const msdc0_parents[] __initconst = {
131 "clk26m_ck",
132 "univpll_d6",
133 "mainpll_d8",
134 "univpll_d8",
135 "mainpll_d16",
136 "mmpll_200m",
137 "mainpll_d12",
138 "mmpll_d2"
139 };
140
141 static const char * const camtg_mm_parents[] __initconst = {
142 "clk_null",
143 "clk26m_ck",
144 "usb_phy48m_ck",
145 "clk_null",
146 "univpll_d6"
147 };
148
149 static const char * const pwm_mm_parents[] __initconst = {
150 "clk26m_ck",
151 "univpll_d12"
152 };
153
154 static const char * const uart1_parents[] __initconst = {
155 "clk26m_ck",
156 "univpll_d24"
157 };
158
159 static const char * const msdc1_parents[] __initconst = {
160 "clk26m_ck",
161 "univpll_d6",
162 "mainpll_d8",
163 "univpll_d8",
164 "mainpll_d16",
165 "mmpll_200m",
166 "mainpll_d12",
167 "mmpll_d2"
168 };
169
170 static const char * const spm_52m_parents[] __initconst = {
171 "clk26m_ck",
172 "univpll_d24"
173 };
174
175 static const char * const pmicspi_parents[] __initconst = {
176 "univpll_d20",
177 "usb_phy48m_ck",
178 "univpll_d16",
179 "clk26m_ck"
180 };
181
182 static const char * const qaxi_aud26m_parents[] __initconst = {
183 "clk26m_ck",
184 "ahb_infra_sel"
185 };
186
187 static const char * const aud_intbus_parents[] __initconst = {
188 "clk_null",
189 "clk26m_ck",
190 "mainpll_d22",
191 "clk_null",
192 "mainpll_d11"
193 };
194
195 static const char * const nfi2x_pad_parents[] __initconst = {
196 "clk_null",
197 "clk_null",
198 "clk_null",
199 "clk_null",
200 "clk_null",
201 "clk_null",
202 "clk_null",
203 "clk_null",
204 "clk26m_ck",
205 "clk_null",
206 "clk_null",
207 "clk_null",
208 "clk_null",
209 "clk_null",
210 "clk_null",
211 "clk_null",
212 "clk_null",
213 "mainpll_d12",
214 "mainpll_d8",
215 "clk_null",
216 "mainpll_d6",
217 "clk_null",
218 "clk_null",
219 "clk_null",
220 "clk_null",
221 "clk_null",
222 "clk_null",
223 "clk_null",
224 "clk_null",
225 "clk_null",
226 "clk_null",
227 "clk_null",
228 "mainpll_d4",
229 "clk_null",
230 "clk_null",
231 "clk_null",
232 "clk_null",
233 "clk_null",
234 "clk_null",
235 "clk_null",
236 "clk_null",
237 "clk_null",
238 "clk_null",
239 "clk_null",
240 "clk_null",
241 "clk_null",
242 "clk_null",
243 "clk_null",
244 "clk_null",
245 "clk_null",
246 "clk_null",
247 "clk_null",
248 "clk_null",
249 "clk_null",
250 "clk_null",
251 "clk_null",
252 "clk_null",
253 "clk_null",
254 "clk_null",
255 "clk_null",
256 "clk_null",
257 "clk_null",
258 "clk_null",
259 "clk_null",
260 "clk_null",
261 "clk_null",
262 "clk_null",
263 "clk_null",
264 "clk_null",
265 "clk_null",
266 "clk_null",
267 "clk_null",
268 "clk_null",
269 "clk_null",
270 "clk_null",
271 "clk_null",
272 "clk_null",
273 "clk_null",
274 "clk_null",
275 "clk_null",
276 "clk_null",
277 "mainpll_d10",
278 "mainpll_d7",
279 "clk_null",
280 "mainpll_d5"
281 };
282
283 static const char * const nfi1x_pad_parents[] __initconst = {
284 "ahb_infra_sel",
285 "nfi1x_ck"
286 };
287
288 static const char * const mfg_mm_parents[] __initconst = {
289 "clk_null",
290 "clk_null",
291 "clk_null",
292 "clk_null",
293 "clk_null",
294 "clk_null",
295 "clk_null",
296 "clk_null",
297 "csw_mux_mfg_sel",
298 "clk_null",
299 "clk_null",
300 "clk_null",
301 "clk_null",
302 "clk_null",
303 "clk_null",
304 "clk_null",
305 "mainpll_d3",
306 "clk_null",
307 "clk_null",
308 "clk_null",
309 "clk_null",
310 "clk_null",
311 "clk_null",
312 "clk_null",
313 "clk_null",
314 "clk_null",
315 "clk_null",
316 "clk_null",
317 "clk_null",
318 "clk_null",
319 "clk_null",
320 "clk_null",
321 "clk_null",
322 "mainpll_d5",
323 "mainpll_d7",
324 "clk_null",
325 "mainpll_d14"
326 };
327
328 static const char * const ddrphycfg_parents[] __initconst = {
329 "clk26m_ck",
330 "mainpll_d16"
331 };
332
333 static const char * const smi_mm_parents[] __initconst = {
334 "clk26m_ck",
335 "clk_null",
336 "clk_null",
337 "clk_null",
338 "clk_null",
339 "clk_null",
340 "clk_null",
341 "clk_null",
342 "clk_null",
343 "univpll_d4",
344 "mainpll_d7",
345 "clk_null",
346 "mainpll_d14"
347 };
348
349 static const char * const usb_78m_parents[] __initconst = {
350 "clk_null",
351 "clk26m_ck",
352 "univpll_d16",
353 "clk_null",
354 "mainpll_d20"
355 };
356
357 static const char * const scam_mm_parents[] __initconst = {
358 "clk_null",
359 "clk26m_ck",
360 "mainpll_d14",
361 "clk_null",
362 "mainpll_d12"
363 };
364
365 static const char * const spinor_parents[] __initconst = {
366 "clk26m_d2",
367 "clk26m_ck",
368 "mainpll_d40",
369 "univpll_d24",
370 "univpll_d20",
371 "mainpll_d20",
372 "mainpll_d16",
373 "univpll_d12"
374 };
375
376 static const char * const msdc2_parents[] __initconst = {
377 "clk26m_ck",
378 "univpll_d6",
379 "mainpll_d8",
380 "univpll_d8",
381 "mainpll_d16",
382 "mmpll_200m",
383 "mainpll_d12",
384 "mmpll_d2"
385 };
386
387 static const char * const eth_parents[] __initconst = {
388 "clk26m_ck",
389 "mainpll_d40",
390 "univpll_d24",
391 "univpll_d20",
392 "mainpll_d20"
393 };
394
395 static const char * const vdec_mm_parents[] __initconst = {
396 "clk26m_ck",
397 "univpll_d4",
398 "mainpll_d4",
399 "univpll_d5",
400 "univpll_d6",
401 "mainpll_d6"
402 };
403
404 static const char * const dpi0_mm_parents[] __initconst = {
405 "clk26m_ck",
406 "lvdspll_ck",
407 "lvdspll_d2",
408 "lvdspll_d4",
409 "lvdspll_d8"
410 };
411
412 static const char * const dpi1_mm_parents[] __initconst = {
413 "clk26m_ck",
414 "tvdpll_d2",
415 "tvdpll_d4",
416 "tvdpll_d8",
417 "tvdpll_d16"
418 };
419
420 static const char * const axi_mfg_in_parents[] __initconst = {
421 "clk26m_ck",
422 "mainpll_d11",
423 "univpll_d24",
424 "mmpll380m"
425 };
426
427 static const char * const slow_mfg_parents[] __initconst = {
428 "clk26m_ck",
429 "univpll_d12",
430 "univpll_d24"
431 };
432
433 static const char * const aud1_parents[] __initconst = {
434 "clk26m_ck",
435 "apll1_ck"
436 };
437
438 static const char * const aud2_parents[] __initconst = {
439 "clk26m_ck",
440 "apll2_ck"
441 };
442
443 static const char * const aud_engen1_parents[] __initconst = {
444 "clk26m_ck",
445 "rg_apll1_d2_en",
446 "rg_apll1_d4_en",
447 "rg_apll1_d8_en"
448 };
449
450 static const char * const aud_engen2_parents[] __initconst = {
451 "clk26m_ck",
452 "rg_apll2_d2_en",
453 "rg_apll2_d4_en",
454 "rg_apll2_d8_en"
455 };
456
457 static const char * const i2c_parents[] __initconst = {
458 "clk26m_ck",
459 "univpll_d20",
460 "univpll_d16",
461 "univpll_d12"
462 };
463
464 static const char * const aud_i2s0_m_parents[] __initconst = {
465 "rg_aud1",
466 "rg_aud2"
467 };
468
469 static const char * const pwm_parents[] __initconst = {
470 "clk26m_ck",
471 "univpll_d12"
472 };
473
474 static const char * const spi_parents[] __initconst = {
475 "clk26m_ck",
476 "univpll_d12",
477 "univpll_d8",
478 "univpll_d6"
479 };
480
481 static const char * const aud_spdifin_parents[] __initconst = {
482 "clk26m_ck",
483 "univpll_d2"
484 };
485
486 static const char * const uart2_parents[] __initconst = {
487 "clk26m_ck",
488 "univpll_d24"
489 };
490
491 static const char * const bsi_parents[] __initconst = {
492 "clk26m_ck",
493 "mainpll_d10",
494 "mainpll_d12",
495 "mainpll_d20"
496 };
497
498 static const char * const dbg_atclk_parents[] __initconst = {
499 "clk_null",
500 "clk26m_ck",
501 "mainpll_d5",
502 "clk_null",
503 "univpll_d5"
504 };
505
506 static const char * const csw_nfiecc_parents[] __initconst = {
507 "clk_null",
508 "mainpll_d7",
509 "mainpll_d6",
510 "clk_null",
511 "mainpll_d5"
512 };
513
514 static const char * const nfiecc_parents[] __initconst = {
515 "clk_null",
516 "nfi2x_pad_sel",
517 "mainpll_d4",
518 "clk_null",
519 "csw_nfiecc_sel"
520 };
521
522 static struct mtk_composite top_muxes[] __initdata = {
523 /* CLK_MUX_SEL0 */
524 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
525 0x000, 0, 1),
526 MUX(CLK_TOP_GFMUX_EMI1X_SEL, "gfmux_emi1x_sel", gfmux_emi1x_parents,
527 0x000, 1, 1),
528 MUX(CLK_TOP_EMI_DDRPHY_SEL, "emi_ddrphy_sel", emi_ddrphy_parents,
529 0x000, 2, 1),
530 MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
531 0x000, 4, 4),
532 MUX(CLK_TOP_CSW_MUX_MFG_SEL, "csw_mux_mfg_sel", csw_mux_mfg_parents,
533 0x000, 8, 3),
534 MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
535 0x000, 11, 3),
536 MUX(CLK_TOP_CAMTG_MM_SEL, "camtg_mm_sel", camtg_mm_parents,
537 0x000, 15, 3),
538 MUX(CLK_TOP_PWM_MM_SEL, "pwm_mm_sel", pwm_mm_parents,
539 0x000, 18, 1),
540 MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
541 0x000, 19, 1),
542 MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
543 0x000, 20, 3),
544 MUX(CLK_TOP_SPM_52M_SEL, "spm_52m_sel", spm_52m_parents,
545 0x000, 23, 1),
546 MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
547 0x000, 24, 2),
548 MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
549 0x000, 26, 1),
550 MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
551 0x000, 27, 3),
552 /* CLK_MUX_SEL1 */
553 MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
554 0x004, 0, 7),
555 MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
556 0x004, 7, 1),
557 MUX(CLK_TOP_MFG_MM_SEL, "mfg_mm_sel", mfg_mm_parents,
558 0x004, 8, 6),
559 MUX(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
560 0x004, 15, 1),
561 MUX(CLK_TOP_SMI_MM_SEL, "smi_mm_sel", smi_mm_parents,
562 0x004, 16, 4),
563 MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents,
564 0x004, 20, 3),
565 MUX(CLK_TOP_SCAM_MM_SEL, "scam_mm_sel", scam_mm_parents,
566 0x004, 23, 3),
567 /* CLK_MUX_SEL8 */
568 MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents,
569 0x040, 0, 3),
570 MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents,
571 0x040, 3, 3),
572 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
573 0x040, 6, 3),
574 MUX(CLK_TOP_VDEC_MM_SEL, "vdec_mm_sel", vdec_mm_parents,
575 0x040, 9, 3),
576 MUX(CLK_TOP_DPI0_MM_SEL, "dpi0_mm_sel", dpi0_mm_parents,
577 0x040, 12, 3),
578 MUX(CLK_TOP_DPI1_MM_SEL, "dpi1_mm_sel", dpi1_mm_parents,
579 0x040, 15, 3),
580 MUX(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents,
581 0x040, 18, 2),
582 MUX(CLK_TOP_SLOW_MFG_SEL, "slow_mfg_sel", slow_mfg_parents,
583 0x040, 20, 2),
584 MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
585 0x040, 22, 1),
586 MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
587 0x040, 23, 1),
588 MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
589 0x040, 24, 2),
590 MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
591 0x040, 26, 2),
592 MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
593 0x040, 28, 2),
594 /* CLK_SEL_9 */
595 MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents,
596 0x044, 12, 1),
597 MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents,
598 0x044, 13, 1),
599 MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents,
600 0x044, 14, 1),
601 MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents,
602 0x044, 15, 1),
603 MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents,
604 0x044, 16, 1),
605 MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents,
606 0x044, 17, 1),
607 MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents,
608 0x044, 18, 1),
609 /* CLK_MUX_SEL13 */
610 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
611 0x07c, 0, 1),
612 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
613 0x07c, 1, 2),
614 MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents,
615 0x07c, 3, 1),
616 MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents,
617 0x07c, 4, 1),
618 MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents,
619 0x07c, 5, 2),
620 MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents,
621 0x07c, 7, 3),
622 MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents,
623 0x07c, 10, 3),
624 MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
625 0x07c, 13, 3),
626 };
627
628 static const char * const ifr_mux1_parents[] __initconst = {
629 "clk26m_ck",
630 "armpll",
631 "univpll",
632 "mainpll_d2"
633 };
634
635 static const char * const ifr_eth_25m_parents[] __initconst = {
636 "eth_d2_ck",
637 "rg_eth"
638 };
639
640 static const char * const ifr_i2c0_parents[] __initconst = {
641 "ahb_infra_d2",
642 "rg_i2c"
643 };
644
645 static const struct mtk_composite ifr_muxes[] __initconst = {
646 MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
647 2, 2),
648 MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
649 0, 1),
650 MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
651 1, 1),
652 MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
653 2, 1),
654 MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,
655 3, 1),
656 };
657
658 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
659 .id = _id, \
660 .name = _name, \
661 .parent_name = _parent, \
662 .div_reg = _reg, \
663 .div_shift = _shift, \
664 .div_width = _width, \
665 }
666
667 static const struct mtk_clk_divider top_adj_divs[] = {
668 DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",
669 0x0048, 0, 8),
670 DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel",
671 0x0048, 8, 8),
672 DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
673 0x0048, 16, 8),
674 DIV_ADJ(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "aud_i2s3_m_sel",
675 0x0048, 24, 8),
676 DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel",
677 0x004c, 0, 8),
678 DIV_ADJ(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_div4",
679 0x004c, 8, 8),
680 DIV_ADJ(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "aud_i2s5_m_sel",
681 0x004c, 16, 8),
682 DIV_ADJ(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_div5",
683 0x004c, 24, 8),
684 DIV_ADJ(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "aud_spdif_b_sel",
685 0x0078, 0, 8),
686 };
687
688 #define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \
689 .id = _id, \
690 .name = _name, \
691 .parent_name = _parent, \
692 .div_reg = _reg, \
693 .div_shift = _shift, \
694 .div_width = _width, \
695 .clk_divider_flags = _flag, \
696 }
697
698 static const struct mtk_clk_divider apmixed_adj_divs[] = {
699 DIV_ADJ_FLAG(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll",
700 0x1c4, 24, 3, CLK_DIVIDER_POWER_OF_TWO),
701 };
702
703 static const struct mtk_gate_regs top0_cg_regs = {
704 .set_ofs = 0x50,
705 .clr_ofs = 0x80,
706 .sta_ofs = 0x20,
707 };
708
709 static const struct mtk_gate_regs top1_cg_regs = {
710 .set_ofs = 0x54,
711 .clr_ofs = 0x84,
712 .sta_ofs = 0x24,
713 };
714
715 static const struct mtk_gate_regs top2_cg_regs = {
716 .set_ofs = 0x6c,
717 .clr_ofs = 0x9c,
718 .sta_ofs = 0x3c,
719 };
720
721 static const struct mtk_gate_regs top3_cg_regs = {
722 .set_ofs = 0xa0,
723 .clr_ofs = 0xb0,
724 .sta_ofs = 0x70,
725 };
726
727 static const struct mtk_gate_regs top4_cg_regs = {
728 .set_ofs = 0xa4,
729 .clr_ofs = 0xb4,
730 .sta_ofs = 0x74,
731 };
732
733 static const struct mtk_gate_regs top5_cg_regs = {
734 .set_ofs = 0x44,
735 .clr_ofs = 0x44,
736 .sta_ofs = 0x44,
737 };
738
739 #define GATE_TOP0(_id, _name, _parent, _shift) { \
740 .id = _id, \
741 .name = _name, \
742 .parent_name = _parent, \
743 .regs = &top0_cg_regs, \
744 .shift = _shift, \
745 .ops = &mtk_clk_gate_ops_setclr, \
746 }
747
748 #define GATE_TOP0_I(_id, _name, _parent, _shift) { \
749 .id = _id, \
750 .name = _name, \
751 .parent_name = _parent, \
752 .regs = &top0_cg_regs, \
753 .shift = _shift, \
754 .ops = &mtk_clk_gate_ops_setclr_inv, \
755 }
756
757 #define GATE_TOP1(_id, _name, _parent, _shift) { \
758 .id = _id, \
759 .name = _name, \
760 .parent_name = _parent, \
761 .regs = &top1_cg_regs, \
762 .shift = _shift, \
763 .ops = &mtk_clk_gate_ops_setclr, \
764 }
765
766 #define GATE_TOP2(_id, _name, _parent, _shift) { \
767 .id = _id, \
768 .name = _name, \
769 .parent_name = _parent, \
770 .regs = &top2_cg_regs, \
771 .shift = _shift, \
772 .ops = &mtk_clk_gate_ops_setclr, \
773 }
774
775 #define GATE_TOP2_I(_id, _name, _parent, _shift) { \
776 .id = _id, \
777 .name = _name, \
778 .parent_name = _parent, \
779 .regs = &top2_cg_regs, \
780 .shift = _shift, \
781 .ops = &mtk_clk_gate_ops_setclr_inv, \
782 }
783
784 #define GATE_TOP3(_id, _name, _parent, _shift) { \
785 .id = _id, \
786 .name = _name, \
787 .parent_name = _parent, \
788 .regs = &top3_cg_regs, \
789 .shift = _shift, \
790 .ops = &mtk_clk_gate_ops_setclr, \
791 }
792
793 #define GATE_TOP4_I(_id, _name, _parent, _shift) { \
794 .id = _id, \
795 .name = _name, \
796 .parent_name = _parent, \
797 .regs = &top4_cg_regs, \
798 .shift = _shift, \
799 .ops = &mtk_clk_gate_ops_setclr_inv, \
800 }
801
802 #define GATE_TOP5(_id, _name, _parent, _shift) { \
803 .id = _id, \
804 .name = _name, \
805 .parent_name = _parent, \
806 .regs = &top5_cg_regs, \
807 .shift = _shift, \
808 .ops = &mtk_clk_gate_ops_no_setclr, \
809 }
810
811 static const struct mtk_gate top_clks[] __initconst = {
812 /* TOP0 */
813 GATE_TOP0(CLK_TOP_PWM_MM, "pwm_mm", "pwm_mm_sel", 0),
814 GATE_TOP0(CLK_TOP_CAM_MM, "cam_mm", "camtg_mm_sel", 1),
815 GATE_TOP0(CLK_TOP_MFG_MM, "mfg_mm", "mfg_mm_sel", 2),
816 GATE_TOP0(CLK_TOP_SPM_52M, "spm_52m", "spm_52m_sel", 3),
817 GATE_TOP0_I(CLK_TOP_MIPI_26M_DBG, "mipi_26m_dbg", "mipi_26m", 4),
818 GATE_TOP0(CLK_TOP_SCAM_MM, "scam_mm", "scam_mm_sel", 5),
819 GATE_TOP0(CLK_TOP_SMI_MM, "smi_mm", "smi_mm_sel", 9),
820 /* TOP1 */
821 GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1),
822 GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),
823 GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3),
824 GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4),
825 GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5),
826 GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6),
827 GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7),
828 GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8),
829 GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9),
830 GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10),
831 GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11),
832 GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12),
833 GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13),
834 GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14),
835 GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15),
836 GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16),
837 GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17),
838 GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18),
839 GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19),
840 GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20),
841 GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21),
842 GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22),
843 GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23),
844 GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24),
845 GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25),
846 GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27),
847 GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28),
848 GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29),
849 GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30),
850 GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31),
851 /* TOP2 */
852 GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
853 GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
854 GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
855 GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
856 GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
857 GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
858 GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
859 GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
860 GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
861 GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
862 GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
863 GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
864 GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
865 GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
866 GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
867 15),
868 GATE_TOP2(CLK_TOP_26M_HDMI_SIFM, "hdmi_sifm_26m", "clk26m_ck", 16),
869 GATE_TOP2(CLK_TOP_26M_CEC, "cec_26m", "clk26m_ck", 17),
870 GATE_TOP2(CLK_TOP_32K_CEC, "cec_32k", "clk32k", 18),
871 GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
872 GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
873 GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
874 GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
875 GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
876 GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
877 GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
878 GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
879 GATE_TOP2(CLK_TOP_GCPU_B, "gcpu_b", "ahb_infra_sel", 27),
880 GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, "msdc0_infra", "msdc0", 28),
881 GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, "msdc1_infra", "msdc1", 29),
882 GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, "msdc2_infra", "rg_msdc2", 30),
883 GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),
884 /* TOP3 */
885 GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0),
886 GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1),
887 GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2),
888 GATE_TOP3(CLK_TOP_RG_VDEC, "rg_vdec", "vdec_mm_sel", 3),
889 GATE_TOP3(CLK_TOP_RG_FDPI0, "rg_fdpi0", "dpi0_mm_sel", 4),
890 GATE_TOP3(CLK_TOP_RG_FDPI1, "rg_fdpi1", "dpi1_mm_sel", 5),
891 GATE_TOP3(CLK_TOP_RG_AXI_MFG, "rg_axi_mfg", "axi_mfg_in_sel", 6),
892 GATE_TOP3(CLK_TOP_RG_SLOW_MFG, "rg_slow_mfg", "slow_mfg_sel", 7),
893 GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8),
894 GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9),
895 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10),
896 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11),
897 GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12),
898 GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13),
899 GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel",
900 14),
901 GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15),
902 GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16),
903 GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17),
904 GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18),
905 /* TOP4 */
906 GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, "rg_apll1_d2_en", "apll1_d2", 8),
907 GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, "rg_apll1_d4_en", "apll1_d4", 9),
908 GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, "rg_apll1_d8_en", "apll1_d8", 10),
909 GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, "rg_apll2_d2_en", "apll2_d2", 11),
910 GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, "rg_apll2_d4_en", "apll2_d4", 12),
911 GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, "rg_apll2_d8_en", "apll2_d8", 13),
912 /* TOP5 */
913 GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
914 GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1),
915 GATE_TOP5(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll12_ck_div2", 2),
916 GATE_TOP5(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll12_ck_div3", 3),
917 GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
918 GATE_TOP5(CLK_TOP_APLL12_DIV4B, "apll12_div4b", "apll12_ck_div4b", 5),
919 GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
920 GATE_TOP5(CLK_TOP_APLL12_DIV5B, "apll12_div5b", "apll12_ck_div5b", 7),
921 GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8),
922 };
923
mtk_topckgen_init(struct device_node * node)924 static void __init mtk_topckgen_init(struct device_node *node)
925 {
926 struct clk_hw_onecell_data *clk_data;
927 int r;
928 void __iomem *base;
929
930 base = of_iomap(node, 0);
931 if (!base) {
932 pr_err("%s(): ioremap failed\n", __func__);
933 return;
934 }
935
936 clk_data = mtk_alloc_clk_data(MT8167_CLK_TOP_NR_CLK);
937
938 mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
939 clk_data);
940 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data);
941
942 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
943 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
944 &mt8167_clk_lock, clk_data);
945 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
946 base, &mt8167_clk_lock, clk_data);
947
948 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
949 if (r)
950 pr_err("%s(): could not register clock provider: %d\n",
951 __func__, r);
952 }
953 CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8167-topckgen", mtk_topckgen_init);
954
mtk_infracfg_init(struct device_node * node)955 static void __init mtk_infracfg_init(struct device_node *node)
956 {
957 struct clk_hw_onecell_data *clk_data;
958 int r;
959 void __iomem *base;
960
961 base = of_iomap(node, 0);
962 if (!base) {
963 pr_err("%s(): ioremap failed\n", __func__);
964 return;
965 }
966
967 clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
968
969 mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base,
970 &mt8167_clk_lock, clk_data);
971
972 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
973 if (r)
974 pr_err("%s(): could not register clock provider: %d\n",
975 __func__, r);
976 }
977 CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8167-infracfg", mtk_infracfg_init);
978
979 #define MT8167_PLL_FMAX (2500UL * MHZ)
980
981 #define CON0_MT8167_RST_BAR BIT(27)
982
983 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
984 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
985 _pcw_shift, _div_table) { \
986 .id = _id, \
987 .name = _name, \
988 .reg = _reg, \
989 .pwr_reg = _pwr_reg, \
990 .en_mask = _en_mask, \
991 .flags = _flags, \
992 .rst_bar_mask = CON0_MT8167_RST_BAR, \
993 .fmax = MT8167_PLL_FMAX, \
994 .pcwbits = _pcwbits, \
995 .pd_reg = _pd_reg, \
996 .pd_shift = _pd_shift, \
997 .tuner_reg = _tuner_reg, \
998 .pcw_reg = _pcw_reg, \
999 .pcw_shift = _pcw_shift, \
1000 .div_table = _div_table, \
1001 }
1002
1003 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
1004 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
1005 _pcw_shift) \
1006 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
1007 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
1008 NULL)
1009
1010 static const struct mtk_pll_div_table mmpll_div_table[] = {
1011 { .div = 0, .freq = MT8167_PLL_FMAX },
1012 { .div = 1, .freq = 1000000000 },
1013 { .div = 2, .freq = 604500000 },
1014 { .div = 3, .freq = 253500000 },
1015 { .div = 4, .freq = 126750000 },
1016 { } /* sentinel */
1017 };
1018
1019 static const struct mtk_pll_data plls[] = {
1020 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0,
1021 21, 0x0104, 24, 0, 0x0104, 0),
1022 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0,
1023 HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
1024 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000,
1025 HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
1026 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0,
1027 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
1028 PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0,
1029 31, 0x0180, 1, 0x0194, 0x0184, 0),
1030 PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0,
1031 31, 0x01A0, 1, 0x01B4, 0x01A4, 0),
1032 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0, 0,
1033 21, 0x01C4, 24, 0, 0x01C4, 0),
1034 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0, 0,
1035 21, 0x01E4, 24, 0, 0x01E4, 0),
1036 };
1037
mtk_apmixedsys_init(struct device_node * node)1038 static void __init mtk_apmixedsys_init(struct device_node *node)
1039 {
1040 struct clk_hw_onecell_data *clk_data;
1041 void __iomem *base;
1042 int r;
1043
1044 base = of_iomap(node, 0);
1045 if (!base) {
1046 pr_err("%s(): ioremap failed\n", __func__);
1047 return;
1048 }
1049
1050 clk_data = mtk_alloc_clk_data(MT8167_CLK_APMIXED_NR_CLK);
1051
1052 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1053 mtk_clk_register_dividers(apmixed_adj_divs, ARRAY_SIZE(apmixed_adj_divs),
1054 base, &mt8167_clk_lock, clk_data);
1055
1056 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1057 if (r)
1058 pr_err("%s(): could not register clock provider: %d\n",
1059 __func__, r);
1060
1061 }
1062 CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8167-apmixedsys",
1063 mtk_apmixedsys_init);
1064
