msi\-cell (full) in projects: Linux-v5.10

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched +full:msi +full:- +full:cell (Results 1 – 25 of 71) sorted by relevance

12 3

/Linux-v5.10/Documentation/devicetree/bindings/mailbox/
D	brcm,iproc-flexrm-mbox.txt	6 FlexRM driver will create a mailbox-controller instance for given FlexRM 10 -------------------- 11 - compatible: Should be "brcm,iproc-flexrm-mbox" 12 - reg: Specifies base physical address and size of the FlexRM 14 - msi-parent: Phandles (and potential Device IDs) to MSI controllers 16 interrupts) to CPU. There is one MSI for each FlexRM ring. 17 Refer devicetree/bindings/interrupt-controller/msi.txt 18 - #mbox-cells: Specifies the number of cells needed to encode a mailbox 21 The 1st cell is the mailbox channel number. 23 The 2nd cell contains MSI completion threshold. This is the [all …]
/Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/
D	arm,gic-v3.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Marc Zyngier <marc.zyngier@arm.com> 15 Software Generated Interrupts (SGI), and Locality-specific Peripheral 19 - $ref: /schemas/interrupt-controller.yaml# 24 - items: 25 - enum: 26 - qcom,msm8996-gic-v3 [all …]`
D	hisilicon,mbigen-v2.txt	6 MBI is kind of msi interrupt only used on Non-PCI devices. 12 Non-pci devices can connect to mbigen and generate the 18 ------------------------------------------- 19 - compatible: Should be "hisilicon,mbigen-v2" 21 - reg: Specifies the base physical address and size of the Mbigen 25 ------------------------------------------ 26 - interrupt controller: Identifies the node as an interrupt controller 28 - msi-parent: Specifies the MSI controller this mbigen use. 29 For more detail information,please refer to the generic msi-parent binding in 30 Documentation/devicetree/bindings/interrupt-controller/msi.txt. [all …]
D	marvell,icu.txt	`2 -------------------------------- 5 responsible for collecting all wired-interrupt sources in the CP and 13 - compatible: Should be "marvell,cp110-icu" 15 - reg: Should contain ICU registers location and length. 22 - compatible: Should be one of: 23 * "marvell,cp110-icu-nsr" 24 * "marvell,cp110-icu-sr" 25 * "marvell,cp110-icu-sei" 26 * "marvell,cp110-icu-rei" 28 - #interrupt-cells: Specifies the number of cells needed to encode an [all …]`
D	arm,gic.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Marc Zyngier <marc.zyngier@arm.com> 22 - $ref: /schemas/interrupt-controller.yaml# 27 - items: 28 - enum: 29 - arm,arm11mp-gic 30 - arm,cortex-a15-gic [all …]`
D	marvell,sei.txt	2 ----------------------------------------------- 15 - compatible: should be one of: 16 * "marvell,ap806-sei" 17 - reg: SEI registers location and length. 18 - interrupts: identifies the parent IRQ that will be triggered. 19 - #interrupt-cells: number of cells to define an SEI wired interrupt 20 coming from the AP, should be 1. The cell is the IRQ 22 - interrupt-controller: identifies the node as an interrupt controller 24 - msi-controller: identifies the node as an MSI controller for the CPs 29 sei: interrupt-controller@3f0200 { [all …]
D	marvell,armada-370-xp-mpic.txt	2 ----------------------------------------------------- 5 - compatible: Should be "marvell,mpic" 6 - interrupt-controller: Identifies the node as an interrupt controller. 7 - msi-controller: Identifies the node as an PCI Message Signaled 9 - #interrupt-cells: The number of cells to define the interrupts. Should be 1. 10 The cell is the IRQ number 12 - reg: Should contain PMIC registers location and length. First pair 13 for the main interrupt registers, second pair for the per-CPU 21 - interrupts: If defined, then it indicates that this MPIC is 24 connected as a slave to the Cortex-A9 GIC. The provided interrupt [all …]
/Linux-v5.10/Documentation/devicetree/bindings/pci/
D	pci-msi.txt	2 relationship between PCI devices and MSI controllers. 18 Requester ID. A mechanism is required to associate a device with both the MSI 22 For generic MSI bindings, see 23 Documentation/devicetree/bindings/interrupt-controller/msi.txt. 30 ------------------- 32 - msi-map: Maps a Requester ID to an MSI controller and associated 33 msi-specifier data. The property is an arbitrary number of tuples of 34 (rid-base,msi-controller,msi-base,length), where: 36 * rid-base is a single cell describing the first RID matched by the entry. 38 * msi-controller is a single phandle to an MSI controller [all …]
D	nvidia,tegra194-pcie.txt	4 and thus inherits all the common properties defined in designware-pcie.txt. 9 - power-domains: A phandle to the node that controls power to the respective 19 "include/dt-bindings/power/tegra194-powergate.h" file. 20 - reg: A list of physical base address and length pairs for each set of 21 controller registers. Must contain an entry for each entry in the reg-names 23 - reg-names: Must include the following entries: 25 "config": As per the definition in designware-pcie.txt 31 - interrupts: A list of interrupt outputs of the controller. Must contain an 32 entry for each entry in the interrupt-names property. 33 - interrupt-names: Must include the following entries: [all …]
D	nvidia,tegra20-pcie.txt	4 - compatible: Must be: 5 - "nvidia,tegra20-pcie": for Tegra20 6 - "nvidia,tegra30-pcie": for Tegra30 7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132 8 - "nvidia,tegra210-pcie": for Tegra210 9 - "nvidia,tegra186-pcie": for Tegra186 10 - power-domains: To ungate power partition by BPMP powergate driver. Must 13 - device_type: Must be "pci" 14 - reg: A list of physical base address and length for each set of controller 15 registers. Must contain an entry for each entry in the reg-names property. [all …]
/Linux-v5.10/arch/powerpc/boot/dts/
D	bluestone.dts	`1 // SPDX-License-Identifier: GPL-2.0-or-later 9 /dts-v1/; 12 #address-cells = <2>; 13 #size-cells = <1>; 16 dcr-parent = <&{/cpus/cpu@0}>; 25 #address-cells = <1>; 26 #size-cells = <0>; 32 clock-frequency = <0>; /* Filled in by U-Boot / 33 timebase-frequency = <0>; / Filled in by U-Boot */ 34 i-cache-line-size = <32>; [all …]`
D	mpc8610_hpcd.dts	`1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright 2007-2008 Freescale Semiconductor Inc. 8 /dts-v1/; 13 #address-cells = <1>; 14 #size-cells = <1>; 25 #address-cells = <1>; 26 #size-cells = <0>; 31 d-cache-line-size = <32>; 32 i-cache-line-size = <32>; 33 d-cache-size = <32768>; // L1 [all …]`
D	mpc8308rdb.dts	`1 // SPDX-License-Identifier: GPL-2.0-or-later 9 /dts-v1/; 13 #address-cells = <1>; 14 #size-cells = <1>; 25 #address-cells = <1>; 26 #size-cells = <0>; 31 d-cache-line-size = <32>; 32 i-cache-line-size = <32>; 33 d-cache-size = <16384>; 34 i-cache-size = <16384>; [all …]`
D	xcalibur1501.dts	`1 // SPDX-License-Identifier: GPL-2.0-only 6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E 9 /dts-v1/; 13 #address-cells = <2>; 14 #size-cells = <2>; 27 #address-cells = <1>; 28 #size-cells = <0>; 33 d-cache-line-size = <32>; // 32 bytes 34 i-cache-line-size = <32>; // 32 bytes 35 d-cache-size = <0x8000>; // L1, 32K [all …]`
D	katmai.dts	`15 /dts-v1/; 18 #address-cells = <2>; 19 #size-cells = <2>; 22 dcr-parent = <&{/cpus/cpu@0}>; 32 #address-cells = <1>; 33 #size-cells = <0>; 39 clock-frequency = <0>; /* Filled in by zImage / 40 timebase-frequency = <0>; / Filled in by zImage */ 41 i-cache-line-size = <32>; 42 d-cache-line-size = <32>; [all …]`
D	redwood.dts	`11 /dts-v1/; 14 #address-cells = <2>; 15 #size-cells = <1>; 18 dcr-parent = <&{/cpus/cpu@0}>; 26 #address-cells = <1>; 27 #size-cells = <0>; 33 clock-frequency = <0>; /* Filled in by U-Boot / 34 timebase-frequency = <0>; / Filled in by U-Boot */ 35 i-cache-line-size = <32>; 36 d-cache-line-size = <32>; [all …]`
D	xpedite5301.dts	`1 // SPDX-License-Identifier: GPL-2.0-only 9 /dts-v1/; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 form-factor = "PMC/XMC"; 16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */ 28 #address-cells = <1>; 29 #size-cells = <0>; 34 d-cache-line-size = <32>; // 32 bytes 35 i-cache-line-size = <32>; // 32 bytes [all …]`
D	xpedite5370.dts	`1 // SPDX-License-Identifier: GPL-2.0-only 6 * XPedite5370 3U VPX single-board computer based on MPC8572E 9 /dts-v1/; 13 #address-cells = <2>; 14 #size-cells = <2>; 26 #address-cells = <1>; 27 #size-cells = <0>; 32 d-cache-line-size = <32>; // 32 bytes 33 i-cache-line-size = <32>; // 32 bytes 34 d-cache-size = <0x8000>; // L1, 32K [all …]`
D	mpc8315erdb.dts	`1 // SPDX-License-Identifier: GPL-2.0-or-later 8 /dts-v1/; 12 #address-cells = <1>; 13 #size-cells = <1>; 26 #address-cells = <1>; 27 #size-cells = <0>; 32 d-cache-line-size = <32>; 33 i-cache-line-size = <32>; 34 d-cache-size = <16384>; 35 i-cache-size = <16384>; [all …]`
D	mpc8308_p1m.dts	`1 // SPDX-License-Identifier: GPL-2.0-or-later 8 /dts-v1/; 12 #address-cells = <1>; 13 #size-cells = <1>; 24 #address-cells = <1>; 25 #size-cells = <0>; 30 d-cache-line-size = <32>; 31 i-cache-line-size = <32>; 32 d-cache-size = <16384>; 33 i-cache-size = <16384>; [all …]`
D	canyonlands.dts	`4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de> 11 /dts-v1/; 14 #address-cells = <2>; 15 #size-cells = <1>; 18 dcr-parent = <&{/cpus/cpu@0}>; 28 #address-cells = <1>; 29 #size-cells = <0>; 35 clock-frequency = <0>; /* Filled in by U-Boot / 36 timebase-frequency = <0>; / Filled in by U-Boot */ 37 i-cache-line-size = <32>; [all …]`
D	kilauea.dts	`4 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de> 11 /dts-v1/; 14 #address-cells = <1>; 15 #size-cells = <1>; 18 dcr-parent = <&{/cpus/cpu@0}>; 28 #address-cells = <1>; 29 #size-cells = <0>; 35 clock-frequency = <0>; /* Filled in by U-Boot / 36 timebase-frequency = <0>; / Filled in by U-Boot */ 37 i-cache-line-size = <32>; [all …]`
D	xpedite5330.dts	`1 // SPDX-License-Identifier: GPL-2.0-only 9 /dts-v1/; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 form-factor = "3U CompactPCI"; 16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash / 29 #address-cells = <1>; 30 #size-cells = <0>; 33 cell-index = <0>; 37 module-present; [all …]`
/Linux-v5.10/kernel/irq/
D	Kconfig	`1 # SPDX-License-Identifier: GPL-2.0-only 54 # Edge style eoi based handler (cell) 63 # Generic irq_domain hw <--> linux irq number translation 87 # Generic MSI interrupt support 91 # Generic MSI hierarchical interrupt domain support 125 out the interrupt descriptors in a more NUMA-friendly way. )`
/Linux-v5.10/drivers/parisc/
D	iosapic.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 3 I/O Sapic Driver - PCI interrupt line support 6 (c) Copyright 1999 Hewlett-Packard Company 14 -------- 21 MSI Message Signaled Interrupt. PCI 2.2 functionality. 28 ------------------------------------- 29 MSI is a write transaction which targets a processor and is similar 33 PA only supports MSI. So I/O subsystems must either natively generate 34 MSIs (e.g. GSC or HP-PB) or convert line based interrupts into MSIs 38 ** MSI allows any I/O device to interrupt any processor. This makes [all …]

12 3