Lines Matching +full:msi +full:- +full:cell
1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 d-cache-size = <16384>;
35 i-cache-size = <16384>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
48 #address-cells = <2>;
49 #size-cells = <1>;
50 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
53 interrupt-parent = <&ipic>;
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "cfi-flash";
68 bank-width = <2>;
69 device-width = <1>;
73 #address-cells = <1>;
74 #size-cells = <1>;
75 compatible = "fsl,mpc8315-fcm-nand",
76 "fsl,elbc-fcm-nand";
79 u-boot@0 {
81 read-only;
94 #address-cells = <1>;
95 #size-cells = <1>;
97 compatible = "fsl,mpc8315-immr", "simple-bus";
100 bus-frequency = <0>;
109 #address-cells = <1>;
110 #size-cells = <0>;
111 cell-index = <0>;
112 compatible = "fsl-i2c";
115 interrupt-parent = <&ipic>;
123 #gpio-cells = <2>;
124 compatible = "fsl,mc9s08qg8-mpc8315erdb",
125 "fsl,mcu-mpc8349emitx";
127 gpio-controller;
132 cell-index = <0>;
136 interrupt-parent = <&ipic>;
141 #address-cells = <1>;
142 #size-cells = <1>;
143 compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
146 interrupt-parent = <&ipic>;
148 cell-index = <0>;
149 dma-channel@0 {
150 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
152 cell-index = <0>;
153 interrupt-parent = <&ipic>;
156 dma-channel@80 {
157 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
159 cell-index = <1>;
160 interrupt-parent = <&ipic>;
163 dma-channel@100 {
164 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
166 cell-index = <2>;
167 interrupt-parent = <&ipic>;
170 dma-channel@180 {
171 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
173 cell-index = <3>;
174 interrupt-parent = <&ipic>;
180 compatible = "fsl-usb2-dr";
182 #address-cells = <1>;
183 #size-cells = <0>;
184 interrupt-parent = <&ipic>;
190 #address-cells = <1>;
191 #size-cells = <1>;
192 cell-index = <0>;
198 local-mac-address = [ 00 00 00 00 00 00 ];
200 interrupt-parent = <&ipic>;
201 tbi-handle = <&tbi0>;
202 phy-handle = < &phy0 >;
203 fsl,magic-packet;
206 #address-cells = <1>;
207 #size-cells = <0>;
208 compatible = "fsl,gianfar-mdio";
211 phy0: ethernet-phy@0 {
212 interrupt-parent = <&ipic>;
217 phy1: ethernet-phy@1 {
218 interrupt-parent = <&ipic>;
223 tbi0: tbi-phy@11 {
225 device_type = "tbi-phy";
231 #address-cells = <1>;
232 #size-cells = <1>;
233 cell-index = <1>;
239 local-mac-address = [ 00 00 00 00 00 00 ];
241 interrupt-parent = <&ipic>;
242 tbi-handle = <&tbi1>;
243 phy-handle = < &phy1 >;
244 fsl,magic-packet;
247 #address-cells = <1>;
248 #size-cells = <0>;
249 compatible = "fsl,gianfar-tbi";
252 tbi1: tbi-phy@11 {
254 device_type = "tbi-phy";
260 cell-index = <0>;
264 clock-frequency = <133333333>;
266 interrupt-parent = <&ipic>;
270 cell-index = <1>;
274 clock-frequency = <133333333>;
276 interrupt-parent = <&ipic>;
285 interrupt-parent = <&ipic>;
286 fsl,num-channels = <4>;
287 fsl,channel-fifo-len = <24>;
288 fsl,exec-units-mask = <0x97c>;
289 fsl,descriptor-types-mask = <0x3a30abf>;
293 compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
295 cell-index = <1>;
297 interrupt-parent = <&ipic>;
301 compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
303 cell-index = <2>;
305 interrupt-parent = <&ipic>;
309 compatible = "fsl,mpc8315-gtm", "fsl,gtm";
312 interrupt-parent = <&ipic>;
313 clock-frequency = <133333333>;
317 compatible = "fsl,mpc8315-gtm", "fsl,gtm";
320 interrupt-parent = <&ipic>;
321 clock-frequency = <133333333>;
325 * interrupts cell = <intr #, sense>
328 * sense == 2: Edge, high-to-low change
330 ipic: interrupt-controller@700 {
331 interrupt-controller;
332 #address-cells = <0>;
333 #interrupt-cells = <2>;
338 ipic-msi@7c0 {
339 compatible = "fsl,ipic-msi";
341 msi-available-ranges = <0 0x100>;
350 interrupt-parent = < &ipic >;
354 compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc",
355 "fsl,mpc8349-pmc";
358 interrupt-parent = <&ipic>;
359 fsl,mpc8313-wakeup-timer = <>m1>;
364 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
365 interrupt-map = <
366 /* IDSEL 0x0E -mini PCI */
372 /* IDSEL 0x0F -mini PCI */
378 /* IDSEL 0x10 - PCI slot */
383 interrupt-parent = <&ipic>;
385 bus-range = <0x0 0x0>;
389 clock-frequency = <66666666>;
390 #interrupt-cells = <1>;
391 #size-cells = <2>;
392 #address-cells = <3>;
395 compatible = "fsl,mpc8349-pci";
400 #address-cells = <3>;
401 #size-cells = <2>;
402 #interrupt-cells = <1>;
404 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
408 bus-range = <0 255>;
409 interrupt-map-mask = <0xf800 0 0 7>;
410 interrupt-map = <0 0 0 1 &ipic 1 8
414 clock-frequency = <0>;
417 #address-cells = <3>;
418 #size-cells = <2>;
431 #address-cells = <3>;
432 #size-cells = <2>;
433 #interrupt-cells = <1>;
435 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
439 bus-range = <0 255>;
440 interrupt-map-mask = <0xf800 0 0 7>;
441 interrupt-map = <0 0 0 1 &ipic 2 8
445 clock-frequency = <0>;
448 #address-cells = <3>;
449 #size-cells = <2>;
462 compatible = "gpio-leds";
466 default-state = "on";
471 linux,default-trigger = "disk-activity";