Lines Matching +full:msi +full:- +full:cell
1 // SPDX-License-Identifier: GPL-2.0-only
6 * XPedite5370 3U VPX single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>; // 32 bytes
33 i-cache-line-size = <32>; // 32 bytes
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
39 next-level-cache = <&L2>;
45 d-cache-line-size = <32>; // 32 bytes
46 i-cache-line-size = <32>; // 32 bytes
47 d-cache-size = <0x8000>; // L1, 32K
48 i-cache-size = <0x8000>; // L1, 32K
49 timebase-frequency = <0>;
50 bus-frequency = <0>;
51 clock-frequency = <0>;
52 next-level-cache = <&L2>;
58 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
62 #address-cells = <2>;
63 #size-cells = <1>;
64 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
67 interrupt-parent = <&mpic>;
74 nor-boot@0,0 {
75 compatible = "amd,s29gl01gp", "cfi-flash";
76 bank-width = <2>;
78 #address-cells = <1>;
79 #size-cells = <1>;
93 label = "Primary U-Boot environment";
97 label = "Primary U-Boot";
99 read-only;
103 nor-alternate@1,0 {
104 compatible = "amd,s29gl01gp", "cfi-flash";
105 bank-width = <2>;
108 #address-cells = <1>;
109 #size-cells = <1>;
123 label = "Secondary U-Boot environment";
127 label = "Secondary U-Boot";
129 read-only;
134 #address-cells = <1>;
135 #size-cells = <1>;
142 compatible = "fsl,mpc8572-fcm-nand",
143 "fsl,elbc-fcm-nand";
145 /* U-Boot should fix this up if chip size > 1 GB */
155 #address-cells = <1>;
156 #size-cells = <1>;
158 compatible = "fsl,mpc8572-immr", "simple-bus";
160 bus-frequency = <0>; // Filled out by uboot.
162 ecm-law@0 {
163 compatible = "fsl,ecm-law";
165 fsl,num-laws = <12>;
169 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
172 interrupt-parent = <&mpic>;
175 memory-controller@2000 {
176 compatible = "fsl,mpc8572-memory-controller";
178 interrupt-parent = <&mpic>;
182 memory-controller@6000 {
183 compatible = "fsl,mpc8572-memory-controller";
185 interrupt-parent = <&mpic>;
189 L2: l2-cache-controller@20000 {
190 compatible = "fsl,mpc8572-l2-cache-controller";
192 cache-line-size = <32>; // 32 bytes
193 cache-size = <0x100000>; // L2, 1M
194 interrupt-parent = <&mpic>;
199 #address-cells = <1>;
200 #size-cells = <0>;
201 cell-index = <0>;
202 compatible = "fsl-i2c";
205 interrupt-parent = <&mpic>;
208 temp-sensor@48 {
213 temp-sensor@4c {
218 cpu-supervisor@51 {
234 pcie-switch@70 {
242 #gpio-cells = <2>;
243 gpio-controller;
250 #gpio-cells = <2>;
251 gpio-controller;
258 #gpio-cells = <2>;
259 gpio-controller;
266 #gpio-cells = <2>;
267 gpio-controller;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 cell-index = <1>;
276 compatible = "fsl-i2c";
279 interrupt-parent = <&mpic>;
284 #address-cells = <1>;
285 #size-cells = <1>;
286 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
289 cell-index = <1>;
290 dma-channel@0 {
291 compatible = "fsl,mpc8572-dma-channel",
292 "fsl,eloplus-dma-channel";
294 cell-index = <0>;
295 interrupt-parent = <&mpic>;
298 dma-channel@80 {
299 compatible = "fsl,mpc8572-dma-channel",
300 "fsl,eloplus-dma-channel";
302 cell-index = <1>;
303 interrupt-parent = <&mpic>;
306 dma-channel@100 {
307 compatible = "fsl,mpc8572-dma-channel",
308 "fsl,eloplus-dma-channel";
310 cell-index = <2>;
311 interrupt-parent = <&mpic>;
314 dma-channel@180 {
315 compatible = "fsl,mpc8572-dma-channel",
316 "fsl,eloplus-dma-channel";
318 cell-index = <3>;
319 interrupt-parent = <&mpic>;
325 #address-cells = <1>;
326 #size-cells = <1>;
327 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
330 cell-index = <0>;
331 dma-channel@0 {
332 compatible = "fsl,mpc8572-dma-channel",
333 "fsl,eloplus-dma-channel";
335 cell-index = <0>;
336 interrupt-parent = <&mpic>;
339 dma-channel@80 {
340 compatible = "fsl,mpc8572-dma-channel",
341 "fsl,eloplus-dma-channel";
343 cell-index = <1>;
344 interrupt-parent = <&mpic>;
347 dma-channel@100 {
348 compatible = "fsl,mpc8572-dma-channel",
349 "fsl,eloplus-dma-channel";
351 cell-index = <2>;
352 interrupt-parent = <&mpic>;
355 dma-channel@180 {
356 compatible = "fsl,mpc8572-dma-channel",
357 "fsl,eloplus-dma-channel";
359 cell-index = <3>;
360 interrupt-parent = <&mpic>;
367 #address-cells = <1>;
368 #size-cells = <1>;
369 cell-index = <0>;
375 local-mac-address = [ 00 00 00 00 00 00 ];
377 interrupt-parent = <&mpic>;
378 tbi-handle = <&tbi0>;
379 phy-handle = <&phy0>;
380 phy-connection-type = "sgmii";
383 #address-cells = <1>;
384 #size-cells = <0>;
385 compatible = "fsl,gianfar-mdio";
388 phy0: ethernet-phy@1 {
389 interrupt-parent = <&mpic>;
393 phy1: ethernet-phy@2 {
394 interrupt-parent = <&mpic>;
398 tbi0: tbi-phy@11 {
400 device_type = "tbi-phy";
407 #address-cells = <1>;
408 #size-cells = <1>;
409 cell-index = <1>;
415 local-mac-address = [ 00 00 00 00 00 00 ];
417 interrupt-parent = <&mpic>;
418 tbi-handle = <&tbi1>;
419 phy-handle = <&phy1>;
420 phy-connection-type = "sgmii";
423 #address-cells = <1>;
424 #size-cells = <0>;
425 compatible = "fsl,gianfar-tbi";
428 tbi1: tbi-phy@11 {
430 device_type = "tbi-phy";
437 cell-index = <0>;
441 clock-frequency = <0>;
443 interrupt-parent = <&mpic>;
448 cell-index = <1>;
452 clock-frequency = <0>;
454 interrupt-parent = <&mpic>;
457 global-utilities@e0000 { //global utilities block
458 compatible = "fsl,mpc8572-guts";
460 fsl,has-rstcr;
463 msi@41600 {
464 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
466 msi-available-ranges = <0 0x100>;
476 interrupt-parent = <&mpic>;
484 interrupt-parent = <&mpic>;
485 fsl,num-channels = <4>;
486 fsl,channel-fifo-len = <24>;
487 fsl,exec-units-mask = <0x9fe>;
488 fsl,descriptor-types-mask = <0x3ab0ebf>;
492 interrupt-controller;
493 #address-cells = <0>;
494 #interrupt-cells = <2>;
496 compatible = "chrp,open-pic";
497 device_type = "open-pic";
501 compatible = "fsl,mpc8572-gpio";
504 interrupt-parent = <&mpic>;
505 #gpio-cells = <2>;
506 gpio-controller;
509 gpio-leds {
510 compatible = "gpio-leds";
515 linux,default-trigger = "heartbeat";
534 /* PME (pattern-matcher) */
536 compatible = "fsl,mpc8572-pme", "pme8572";
539 interrupt-parent = <&mpic>;
543 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
546 interrupt-parent = <&mpic>;
550 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
553 interrupt-parent = <&mpic>;
564 compatible = "fsl,mpc8548-pcie";
566 #interrupt-cells = <1>;
567 #size-cells = <2>;
568 #address-cells = <3>;
570 bus-range = <0 255>;
573 clock-frequency = <33333333>;
574 interrupt-parent = <&mpic>;
576 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
577 interrupt-map = <
586 #size-cells = <2>;
587 #address-cells = <3>;
601 compatible = "fsl,mpc8548-pcie";
603 #interrupt-cells = <1>;
604 #size-cells = <2>;
605 #address-cells = <3>;
607 bus-range = <0 255>;
610 clock-frequency = <33333333>;
611 interrupt-parent = <&mpic>;
613 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
614 interrupt-map = <
623 #size-cells = <2>;
624 #address-cells = <3>;