Lines Matching +full:msi +full:- +full:cell
4 and thus inherits all the common properties defined in designware-pcie.txt.
9 - power-domains: A phandle to the node that controls power to the respective
19 "include/dt-bindings/power/tegra194-powergate.h" file.
20 - reg: A list of physical base address and length pairs for each set of
21 controller registers. Must contain an entry for each entry in the reg-names
23 - reg-names: Must include the following entries:
25 "config": As per the definition in designware-pcie.txt
31 - interrupts: A list of interrupt outputs of the controller. Must contain an
32 entry for each entry in the interrupt-names property.
33 - interrupt-names: Must include the following entries:
35 - clocks: Must contain an entry for each entry in clock-names.
36 See ../clocks/clock-bindings.txt for details.
37 - clock-names: Must include the following entries:
38 - core
39 - resets: Must contain an entry for each entry in reset-names.
41 - reset-names: Must include the following entries:
42 - apb
43 - core
44 - phys: Must contain a phandle to P2U PHY for each entry in phy-names.
45 - phy-names: Must include an entry for each active lane.
46 "p2u-N": where N ranges from 0 to one less than the total number of lanes
47 - nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
48 by controller-id. Following are the controller ids for each controller.
55 - vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
58 - compatible: Tegra19x must contain "nvidia,tegra194-pcie"
59 - device_type: Must be "pci" for RC mode
60 - interrupt-names: Must include the following entries:
61 "msi": The Tegra interrupt that is asserted when an MSI is received
62 - bus-range: Range of bus numbers associated with this controller
63 - #address-cells: Address representation for root ports (must be 3)
64 - cell 0 specifies the bus and device numbers of the root port:
67 - cell 1 denotes the upper 32 address bits and should be 0
68 - cell 2 contains the lower 32 address bits and is used to translate to the
70 - #size-cells: Size representation for root ports (must be 2)
71 - ranges: Describes the translation of addresses for root ports and standard
73 correspond to the address as described for the #address-cells property
76 #size-cells property above.
77 - Entries setup the mapping for the standard I/O, memory and
78 prefetchable PCI regions. The first cell determines the type of region
80 - 0x81000000: I/O memory region
81 - 0x82000000: non-prefetchable memory region
82 - 0xc2000000: prefetchable memory region
85 - #interrupt-cells: Size representation for interrupts (must be 1)
86 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
92 - compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep"
93 - reg-names: Must include the following entries:
95 - reset-gpios: Must contain a phandle to a GPIO controller followed by
100 - pinctrl-names: A list of pinctrl state names.
102 - "default": Configures PCIe I/O for proper operation.
103 - pinctrl-0: phandle for the 'default' state of pin configuration.
105 - supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
106 - nvidia,update-fc-fixup: This is a boolean property and needs to be present to
113 a) speed is Gen-2 and MPS is 256B
114 b) speed is >= Gen-3 with any MPS
115 - nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM
117 - nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be
119 - nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
123 - vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
124 if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
125 in p2972-0000 platform).
126 - vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot
127 if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
128 in p2972-0000 platform).
131 - nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller
134 NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
141 -----------------
144 compatible = "nvidia,tegra194-pcie";
145 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
149 reg-names = "appl", "config", "atu_dma";
151 #address-cells = <3>;
152 #size-cells = <2>;
154 num-lanes = <8>;
155 linux,pci-domain = <0>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
161 clock-names = "core";
165 reset-names = "apb", "core";
168 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
169 interrupt-names = "intr", "msi";
171 #interrupt-cells = <1>;
172 interrupt-map-mask = <0 0 0 0>;
173 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
177 supports-clkreq;
178 nvidia,aspm-cmrt-us = <60>;
179 nvidia,aspm-pwr-on-t-us = <20>;
180 nvidia,aspm-l0s-entrance-latency-us = <3>;
182 bus-range = <0x0 0xff>;
184 … 0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */
187 vddio-pex-ctl-supply = <&vdd_1v8ao>;
188 vpcie3v3-supply = <&vdd_3v3_pcie>;
189 vpcie12v-supply = <&vdd_12v_pcie>;
193 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
197 -----------------
200 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
201 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
206 reg-names = "appl", "atu_dma", "dbi", "addr_space";
208 num-lanes = <8>;
209 num-ib-windows = <2>;
210 num-ob-windows = <8>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
216 clock-names = "core";
220 reset-names = "apb", "core";
223 interrupt-names = "intr";
227 nvidia,aspm-cmrt-us = <60>;
228 nvidia,aspm-pwr-on-t-us = <20>;
229 nvidia,aspm-l0s-entrance-latency-us = <3>;
231 vddio-pex-ctl-supply = <&vdd_1v8ao>;
233 reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
235 nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
242 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
243 "p2u-5", "p2u-6", "p2u-7";