| /Linux-v5.10/arch/mips/boot/dts/loongson/ |
| D | ls7a-pch.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "simple-bus";
6 #address-cells = <2>;
7 #size-cells = <2>;
13 pic: interrupt-controller@10000000 {
14 compatible = "loongson,pch-pic-1.0";
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
18 loongson,pic-base-vec = <0>;
19 #interrupt-cells = <2>;
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| /Linux-v5.10/Documentation/devicetree/bindings/pci/ |
| D | mediatek-pcie.txt | 4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 - device_type: Must be "pci"
11 - reg: Base addresses and lengths of the PCIe subsys and root ports.
12 - reg-names: Names of the above areas to use during resource lookup.
13 - #address-cells: Address representation for root ports (must be 3)
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| D | mvebu-pci.txt | 5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
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| D | xilinx-pcie.txt | 4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
8 - compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
9 - reg: Should contain AXI PCIe registers location and length
10 - device_type: must be "pci"
11 - interrupts: Should contain AXI PCIe interrupt
12 - interrupt-map-mask,
13 interrupt-map: standard PCI properties to define the mapping of the
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| D | ralink,rt3883-pci.txt | 7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
28 The main node must have two child nodes which describes the built-in
29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
35 - interrupt-controller: identifies the node as an interrupt controller
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| D | versatile.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 - $ref: /schemas/pci/pci-bus.yaml#
20 const: arm,versatile-pci
24 - description: Versatile-specific registers
25 - description: Self Config space
26 - description: Config space
31 "#interrupt-cells": true
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| D | intel-gw-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
16 const: intel,lgm-pcie
18 - compatible
23 - const: intel,lgm-pcie
24 - const: snps,dw-pcie
29 "#address-cells":
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| D | xilinx-versal-cpm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
17 const: xlnx,versal-cpm-host-1.00
21 - description: Configuration space region and bridge registers.
22 - description: CPM system level control and status registers.
24 reg-names:
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| D | brcm,iproc-pcie.txt | 4 - compatible:
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
13 PAXB-based root complex is used for external endpoint devices. PAXC-based
15 - reg: base address and length of the PCIe controller I/O register space
16 - #interrupt-cells: set to <1>
17 - interrupt-map-mask and interrupt-map, standard PCI properties to define the
18 mapping of the PCIe interface to interrupt numbers
[all …]
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| D | faraday,ftpci100.txt | 5 plain and dual PCI. The plain version embeds a cascading interrupt controller
7 chips interrupt controller.
14 - compatible: ranging from specific to generic, should be one of
15 "cortina,gemini-pci", "faraday,ftpci100"
16 "cortina,gemini-pci-dual", "faraday,ftpci100-dual"
18 "faraday,ftpci100-dual"
19 - reg: memory base and size for the host bridge
20 - #address-cells: set to <3>
21 - #size-cells: set to <2>
22 - #interrupt-cells: set to <1>
[all …]
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| /Linux-v5.10/drivers/irqchip/ |
| D | irq-ingenic-tcu.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/interrupt.h>
11 #include <linux/mfd/ingenic-tcu.h>
17 struct regmap *map; member
26 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); in ingenic_tcu_intc_cascade()
29 struct regmap *map = gc->private; in ingenic_tcu_intc_cascade() local
33 regmap_read(map, TCU_REG_TFR, &irq_reg); in ingenic_tcu_intc_cascade()
34 regmap_read(map, TCU_REG_TMR, &irq_mask); in ingenic_tcu_intc_cascade()
50 struct regmap *map = gc->private; in ingenic_tcu_gc_unmask_enable_reg() local
51 u32 mask = d->mask; in ingenic_tcu_gc_unmask_enable_reg() local
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| D | irq-ls-extirq.c | 1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "irq-ls-extirq: " fmt
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 struct irq_fwspec map[MAXIRQ]; member
29 struct ls_extirq_data *priv = data->chip_data; in ls_extirq_set_type()
30 irq_hw_number_t hwirq = data->hwirq; in ls_extirq_set_type()
31 u32 value, mask; in ls_extirq_set_type() local
33 if (priv->bit_reverse) in ls_extirq_set_type()
34 mask = 1U << (31 - hwirq); in ls_extirq_set_type()
36 mask = 1U << hwirq; in ls_extirq_set_type()
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| D | irq-hip04.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2002-2014 ARM Limited.
6 * Copyright (c) 2013-2014 Hisilicon Ltd.
7 * Copyright (c) 2013-2014 Linaro Ltd.
9 * Interrupt architecture for the HIP04 INTC:
11 * o There is one Interrupt Distributor, which receives interrupts
12 * from system devices and sends them to the Interrupt Controllers.
20 * Note that IRQs 0-31 are special - they are local to each CPU.
22 * registers are banked per-cpu for these sources.
39 #include <linux/interrupt.h>
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| /Linux-v5.10/arch/arm/boot/dts/ |
| D | armada-xp-mv78260.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
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| D | armada-xp-mv78460.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
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| D | armada-xp-mv78230.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
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| D | armada-385.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
30 compatible = "arm,cortex-a9";
37 compatible = "marvell,armada-370-pcie";
[all …]
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| /Linux-v5.10/drivers/base/regmap/ |
| D | regmap-irq.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/interrupt.h>
24 struct regmap *map; member
52 return &data->chip->irqs[irq]; in irq_to_regmap_irq()
59 mutex_lock(&d->lock); in regmap_irq_lock()
63 unsigned int reg, unsigned int mask, in regmap_irq_update_bits() argument
66 if (d->chip->mask_writeonly) in regmap_irq_update_bits()
67 return regmap_write_bits(d->map, reg, mask, val); in regmap_irq_update_bits()
69 return regmap_update_bits(d->map, reg, mask, val); in regmap_irq_update_bits()
75 struct regmap *map = d->map; in regmap_irq_sync_unlock() local
[all …]
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| /Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | renesas,rza1-irqc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/A1 Interrupt Controller
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
17 - NMI edge select.
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| D | brcm,bcm7120-l2-intc.txt | 1 Broadcom BCM7120-style Level 2 interrupt controller
3 This interrupt controller hardware is a second level interrupt controller that
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
7 Such an interrupt controller has the following hardware design:
9 - outputs multiple interrupts signals towards its interrupt controller parent
11 - controls how some of the interrupts will be flowing, whether they will
12 directly output an interrupt signal towards the interrupt controller parent,
13 or if they will output an interrupt signal at this 2nd level interrupt
16 - has one 32-bit enable word and one 32-bit status word
18 - no atomic set/clear operations
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| D | fsl,ls-extirq.txt | 4 the polarity of certain external interrupt lines.
10 - compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".
11 - #interrupt-cells: Must be 2. The first element is the index of the
12 external interrupt line. The second element is the trigger type.
13 - #address-cells: Must be 0.
14 - interrupt-controller: Identifies the node as an interrupt controller
15 - reg: Specifies the Interrupt Polarity Control Register (INTPCR) in
17 - interrupt-map: Specifies the mapping from external interrupts to GIC
19 - interrupt-map-mask: Must be <0xffffffff 0>.
23 compatible = "fsl,ls1021a-scfg", "syscon";
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| /Linux-v5.10/arch/powerpc/sysdev/ge/ |
| D | ge_pic.c | 2 * Interrupt handling for GE FPGA based PIC
17 #include <linux/interrupt.h>
38 /* Interrupt Controller Interface Registers */
57 * Interrupt Controller Handling
59 * The interrupt controller handles interrupts for most on board interrupts,
67 * 12 RO Real Time Clock Interrupt Status
68 * 11 RO Temperature Interrupt Status
69 * 10 RO Temperature Critical Interrupt Status
70 * 9 RO Ethernet PHY1 Interrupt Status
71 * 8 RO Ethernet PHY3 Interrupt Status
[all …]
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| /Linux-v5.10/block/ |
| D | blk-mq-rdma.c | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/blk-mq.h>
6 #include <linux/blk-mq-rdma.h>
10 * blk_mq_rdma_map_queues - provide a default queue mapping for rdma device
11 * @map: CPU to hardware queue map.
13 * @first_vec: first interrupt vectors to use for queues (usually 0)
16 * interrupt vetors as @set has queues. It will then query it's affinity mask
21 * @set->nr_hw_queues, or @dev does not provide an affinity mask for a
24 int blk_mq_rdma_map_queues(struct blk_mq_queue_map *map, in blk_mq_rdma_map_queues() argument
27 const struct cpumask *mask; in blk_mq_rdma_map_queues() local
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| /Linux-v5.10/arch/mips/boot/dts/img/ |
| D | boston.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/boston-clock.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 stdout-path = "uart0:115200";
23 #address-cells = <1>;
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| /Linux-v5.10/drivers/pcmcia/ |
| D | pd6729.c | 2 * Driver for the Cirrus PD6729 PCI-PCMCIA bridge.
16 #include <linux/interrupt.h>
28 MODULE_DESCRIPTION("Driver for the Cirrus PD6729 PCI-PCMCIA bridge");
29 MODULE_AUTHOR("Jun Komuro <komurojun-mbn@nifty.com>");
46 * Specifies the interrupt delivery mode. The default (1) is to use PCI
51 static int irq_mode = 1; /* 0 = ISA interrupt, 1 = PCI interrupt */
55 "interrupt delivery mode. 0 = ISA, 1 = PCI. default is 1");
69 reg += socket->number * 0x40; in indirect_read()
70 port = socket->io_base; in indirect_read()
86 reg = reg + socket->number * 0x40; in indirect_read16()
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