Lines Matching +full:interrupt +full:- +full:map +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/interrupt.h>
24 struct regmap *map; member
52 return &data->chip->irqs[irq]; in irq_to_regmap_irq()
59 mutex_lock(&d->lock); in regmap_irq_lock()
63 unsigned int reg, unsigned int mask, in regmap_irq_update_bits() argument
66 if (d->chip->mask_writeonly) in regmap_irq_update_bits()
67 return regmap_write_bits(d->map, reg, mask, val); in regmap_irq_update_bits()
69 return regmap_update_bits(d->map, reg, mask, val); in regmap_irq_update_bits()
75 struct regmap *map = d->map; in regmap_irq_sync_unlock() local
81 if (d->chip->runtime_pm) { in regmap_irq_sync_unlock()
82 ret = pm_runtime_get_sync(map->dev); in regmap_irq_sync_unlock()
84 dev_err(map->dev, "IRQ sync failed to resume: %d\n", in regmap_irq_sync_unlock()
88 if (d->clear_status) { in regmap_irq_sync_unlock()
89 for (i = 0; i < d->chip->num_regs; i++) { in regmap_irq_sync_unlock()
90 reg = d->chip->status_base + in regmap_irq_sync_unlock()
91 (i * map->reg_stride * d->irq_reg_stride); in regmap_irq_sync_unlock()
93 ret = regmap_read(map, reg, &val); in regmap_irq_sync_unlock()
95 dev_err(d->map->dev, in regmap_irq_sync_unlock()
96 "Failed to clear the interrupt status bits\n"); in regmap_irq_sync_unlock()
99 d->clear_status = false; in regmap_irq_sync_unlock()
103 * If there's been a change in the mask write it back to the in regmap_irq_sync_unlock()
107 for (i = 0; i < d->chip->num_regs; i++) { in regmap_irq_sync_unlock()
108 if (!d->chip->mask_base) in regmap_irq_sync_unlock()
111 reg = d->chip->mask_base + in regmap_irq_sync_unlock()
112 (i * map->reg_stride * d->irq_reg_stride); in regmap_irq_sync_unlock()
113 if (d->chip->mask_invert) { in regmap_irq_sync_unlock()
115 d->mask_buf_def[i], ~d->mask_buf[i]); in regmap_irq_sync_unlock()
116 } else if (d->chip->unmask_base) { in regmap_irq_sync_unlock()
117 /* set mask with mask_base register */ in regmap_irq_sync_unlock()
119 d->mask_buf_def[i], ~d->mask_buf[i]); in regmap_irq_sync_unlock()
121 dev_err(d->map->dev, in regmap_irq_sync_unlock()
124 unmask_offset = d->chip->unmask_base - in regmap_irq_sync_unlock()
125 d->chip->mask_base; in regmap_irq_sync_unlock()
126 /* clear mask with unmask_base register */ in regmap_irq_sync_unlock()
129 d->mask_buf_def[i], in regmap_irq_sync_unlock()
130 d->mask_buf[i]); in regmap_irq_sync_unlock()
133 d->mask_buf_def[i], d->mask_buf[i]); in regmap_irq_sync_unlock()
136 dev_err(d->map->dev, "Failed to sync masks in %x\n", in regmap_irq_sync_unlock()
139 reg = d->chip->wake_base + in regmap_irq_sync_unlock()
140 (i * map->reg_stride * d->irq_reg_stride); in regmap_irq_sync_unlock()
141 if (d->wake_buf) { in regmap_irq_sync_unlock()
142 if (d->chip->wake_invert) in regmap_irq_sync_unlock()
144 d->mask_buf_def[i], in regmap_irq_sync_unlock()
145 ~d->wake_buf[i]); in regmap_irq_sync_unlock()
148 d->mask_buf_def[i], in regmap_irq_sync_unlock()
149 d->wake_buf[i]); in regmap_irq_sync_unlock()
151 dev_err(d->map->dev, in regmap_irq_sync_unlock()
156 if (!d->chip->init_ack_masked) in regmap_irq_sync_unlock()
160 * OR if there is masked interrupt which hasn't been Acked, in regmap_irq_sync_unlock()
163 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) { in regmap_irq_sync_unlock()
164 reg = d->chip->ack_base + in regmap_irq_sync_unlock()
165 (i * map->reg_stride * d->irq_reg_stride); in regmap_irq_sync_unlock()
167 if (d->chip->ack_invert) in regmap_irq_sync_unlock()
168 ret = regmap_write(map, reg, ~d->mask_buf[i]); in regmap_irq_sync_unlock()
170 ret = regmap_write(map, reg, d->mask_buf[i]); in regmap_irq_sync_unlock()
171 if (d->chip->clear_ack) { in regmap_irq_sync_unlock()
172 if (d->chip->ack_invert && !ret) in regmap_irq_sync_unlock()
173 ret = regmap_write(map, reg, in regmap_irq_sync_unlock()
174 d->mask_buf[i]); in regmap_irq_sync_unlock()
176 ret = regmap_write(map, reg, in regmap_irq_sync_unlock()
177 ~d->mask_buf[i]); in regmap_irq_sync_unlock()
180 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n", in regmap_irq_sync_unlock()
185 /* Don't update the type bits if we're using mask bits for irq type. */ in regmap_irq_sync_unlock()
186 if (!d->chip->type_in_mask) { in regmap_irq_sync_unlock()
187 for (i = 0; i < d->chip->num_type_reg; i++) { in regmap_irq_sync_unlock()
188 if (!d->type_buf_def[i]) in regmap_irq_sync_unlock()
190 reg = d->chip->type_base + in regmap_irq_sync_unlock()
191 (i * map->reg_stride * d->type_reg_stride); in regmap_irq_sync_unlock()
192 if (d->chip->type_invert) in regmap_irq_sync_unlock()
194 d->type_buf_def[i], ~d->type_buf[i]); in regmap_irq_sync_unlock()
197 d->type_buf_def[i], d->type_buf[i]); in regmap_irq_sync_unlock()
199 dev_err(d->map->dev, "Failed to sync type in %x\n", in regmap_irq_sync_unlock()
204 if (d->chip->runtime_pm) in regmap_irq_sync_unlock()
205 pm_runtime_put(map->dev); in regmap_irq_sync_unlock()
208 if (d->wake_count < 0) in regmap_irq_sync_unlock()
209 for (i = d->wake_count; i < 0; i++) in regmap_irq_sync_unlock()
210 irq_set_irq_wake(d->irq, 0); in regmap_irq_sync_unlock()
211 else if (d->wake_count > 0) in regmap_irq_sync_unlock()
212 for (i = 0; i < d->wake_count; i++) in regmap_irq_sync_unlock()
213 irq_set_irq_wake(d->irq, 1); in regmap_irq_sync_unlock()
215 d->wake_count = 0; in regmap_irq_sync_unlock()
217 mutex_unlock(&d->lock); in regmap_irq_sync_unlock()
223 struct regmap *map = d->map; in regmap_irq_enable() local
224 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_enable()
225 unsigned int mask, type; in regmap_irq_enable() local
227 type = irq_data->type.type_falling_val | irq_data->type.type_rising_val; in regmap_irq_enable()
231 * separate mask bits for rising and falling edge interrupts, but in regmap_irq_enable()
232 * we want to make them into a single virtual interrupt with in regmap_irq_enable()
235 * If the interrupt we're enabling defines the falling or rising in regmap_irq_enable()
236 * masks then instead of using the regular mask bits for this in regmap_irq_enable()
237 * interrupt, use the value previously written to the type buffer in regmap_irq_enable()
240 if (d->chip->type_in_mask && type) in regmap_irq_enable()
241 mask = d->type_buf[irq_data->reg_offset / map->reg_stride]; in regmap_irq_enable()
243 mask = irq_data->mask; in regmap_irq_enable()
245 if (d->chip->clear_on_unmask) in regmap_irq_enable()
246 d->clear_status = true; in regmap_irq_enable()
248 d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask; in regmap_irq_enable()
254 struct regmap *map = d->map; in regmap_irq_disable() local
255 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_disable()
257 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask; in regmap_irq_disable()
263 struct regmap *map = d->map; in regmap_irq_set_type() local
264 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_set_type()
266 const struct regmap_irq_type *t = &irq_data->type; in regmap_irq_set_type()
268 if ((t->types_supported & type) != type) in regmap_irq_set_type()
271 reg = t->type_reg_offset / map->reg_stride; in regmap_irq_set_type()
273 if (t->type_reg_mask) in regmap_irq_set_type()
274 d->type_buf[reg] &= ~t->type_reg_mask; in regmap_irq_set_type()
276 d->type_buf[reg] &= ~(t->type_falling_val | in regmap_irq_set_type()
277 t->type_rising_val | in regmap_irq_set_type()
278 t->type_level_low_val | in regmap_irq_set_type()
279 t->type_level_high_val); in regmap_irq_set_type()
282 d->type_buf[reg] |= t->type_falling_val; in regmap_irq_set_type()
286 d->type_buf[reg] |= t->type_rising_val; in regmap_irq_set_type()
290 d->type_buf[reg] |= (t->type_falling_val | in regmap_irq_set_type()
291 t->type_rising_val); in regmap_irq_set_type()
295 d->type_buf[reg] |= t->type_level_high_val; in regmap_irq_set_type()
299 d->type_buf[reg] |= t->type_level_low_val; in regmap_irq_set_type()
302 return -EINVAL; in regmap_irq_set_type()
310 struct regmap *map = d->map; in regmap_irq_set_wake() local
311 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_set_wake()
314 if (d->wake_buf) in regmap_irq_set_wake()
315 d->wake_buf[irq_data->reg_offset / map->reg_stride] in regmap_irq_set_wake()
316 &= ~irq_data->mask; in regmap_irq_set_wake()
317 d->wake_count++; in regmap_irq_set_wake()
319 if (d->wake_buf) in regmap_irq_set_wake()
320 d->wake_buf[irq_data->reg_offset / map->reg_stride] in regmap_irq_set_wake()
321 |= irq_data->mask; in regmap_irq_set_wake()
322 d->wake_count--; in regmap_irq_set_wake()
340 const struct regmap_irq_chip *chip = data->chip; in read_sub_irq_data()
341 struct regmap *map = data->map; in read_sub_irq_data() local
345 if (!chip->sub_reg_offsets) { in read_sub_irq_data()
347 ret = regmap_read(map, chip->status_base + in read_sub_irq_data()
348 (b * map->reg_stride * data->irq_reg_stride), in read_sub_irq_data()
349 &data->status_buf[b]); in read_sub_irq_data()
351 subreg = &chip->sub_reg_offsets[b]; in read_sub_irq_data()
352 for (i = 0; i < subreg->num_regs; i++) { in read_sub_irq_data()
353 unsigned int offset = subreg->offset[i]; in read_sub_irq_data()
355 ret = regmap_read(map, chip->status_base + offset, in read_sub_irq_data()
356 &data->status_buf[offset]); in read_sub_irq_data()
367 const struct regmap_irq_chip *chip = data->chip; in regmap_irq_thread()
368 struct regmap *map = data->map; in regmap_irq_thread() local
373 if (chip->handle_pre_irq) in regmap_irq_thread()
374 chip->handle_pre_irq(chip->irq_drv_data); in regmap_irq_thread()
376 if (chip->runtime_pm) { in regmap_irq_thread()
377 ret = pm_runtime_get_sync(map->dev); in regmap_irq_thread()
379 dev_err(map->dev, "IRQ thread failed to resume: %d\n", in regmap_irq_thread()
391 if (chip->num_main_regs) { in regmap_irq_thread()
395 size = chip->num_regs * sizeof(unsigned int); in regmap_irq_thread()
397 max_main_bits = (chip->num_main_status_bits) ? in regmap_irq_thread()
398 chip->num_main_status_bits : chip->num_regs; in regmap_irq_thread()
400 memset(data->status_buf, 0, size); in regmap_irq_thread()
407 for (i = 0; i < chip->num_main_regs; i++) { in regmap_irq_thread()
408 ret = regmap_read(map, chip->main_status + in regmap_irq_thread()
409 (i * map->reg_stride in regmap_irq_thread()
410 * data->irq_reg_stride), in regmap_irq_thread()
411 &data->main_status_buf[i]); in regmap_irq_thread()
413 dev_err(map->dev, in regmap_irq_thread()
421 for (i = 0; i < chip->num_main_regs; i++) { in regmap_irq_thread()
423 const unsigned long mreg = data->main_status_buf[i]; in regmap_irq_thread()
425 for_each_set_bit(b, &mreg, map->format.val_bytes * 8) { in regmap_irq_thread()
426 if (i * map->format.val_bytes * 8 + b > in regmap_irq_thread()
432 dev_err(map->dev, in regmap_irq_thread()
440 } else if (!map->use_single_read && map->reg_stride == 1 && in regmap_irq_thread()
441 data->irq_reg_stride == 1) { in regmap_irq_thread()
443 u8 *buf8 = data->status_reg_buf; in regmap_irq_thread()
444 u16 *buf16 = data->status_reg_buf; in regmap_irq_thread()
445 u32 *buf32 = data->status_reg_buf; in regmap_irq_thread()
447 BUG_ON(!data->status_reg_buf); in regmap_irq_thread()
449 ret = regmap_bulk_read(map, chip->status_base, in regmap_irq_thread()
450 data->status_reg_buf, in regmap_irq_thread()
451 chip->num_regs); in regmap_irq_thread()
453 dev_err(map->dev, "Failed to read IRQ status: %d\n", in regmap_irq_thread()
458 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
459 switch (map->format.val_bytes) { in regmap_irq_thread()
461 data->status_buf[i] = buf8[i]; in regmap_irq_thread()
464 data->status_buf[i] = buf16[i]; in regmap_irq_thread()
467 data->status_buf[i] = buf32[i]; in regmap_irq_thread()
476 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
477 ret = regmap_read(map, chip->status_base + in regmap_irq_thread()
478 (i * map->reg_stride in regmap_irq_thread()
479 * data->irq_reg_stride), in regmap_irq_thread()
480 &data->status_buf[i]); in regmap_irq_thread()
483 dev_err(map->dev, in regmap_irq_thread()
494 * interrupt. We assume that typically few of the interrupts in regmap_irq_thread()
498 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
499 data->status_buf[i] &= ~data->mask_buf[i]; in regmap_irq_thread()
501 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) { in regmap_irq_thread()
502 reg = chip->ack_base + in regmap_irq_thread()
503 (i * map->reg_stride * data->irq_reg_stride); in regmap_irq_thread()
504 if (chip->ack_invert) in regmap_irq_thread()
505 ret = regmap_write(map, reg, in regmap_irq_thread()
506 ~data->status_buf[i]); in regmap_irq_thread()
508 ret = regmap_write(map, reg, in regmap_irq_thread()
509 data->status_buf[i]); in regmap_irq_thread()
510 if (chip->clear_ack) { in regmap_irq_thread()
511 if (chip->ack_invert && !ret) in regmap_irq_thread()
512 ret = regmap_write(map, reg, in regmap_irq_thread()
513 data->status_buf[i]); in regmap_irq_thread()
515 ret = regmap_write(map, reg, in regmap_irq_thread()
516 ~data->status_buf[i]); in regmap_irq_thread()
519 dev_err(map->dev, "Failed to ack 0x%x: %d\n", in regmap_irq_thread()
524 for (i = 0; i < chip->num_irqs; i++) { in regmap_irq_thread()
525 if (data->status_buf[chip->irqs[i].reg_offset / in regmap_irq_thread()
526 map->reg_stride] & chip->irqs[i].mask) { in regmap_irq_thread()
527 handle_nested_irq(irq_find_mapping(data->domain, i)); in regmap_irq_thread()
533 if (chip->runtime_pm) in regmap_irq_thread()
534 pm_runtime_put(map->dev); in regmap_irq_thread()
536 if (chip->handle_post_irq) in regmap_irq_thread()
537 chip->handle_post_irq(chip->irq_drv_data); in regmap_irq_thread()
548 struct regmap_irq_chip_data *data = h->host_data; in regmap_irq_map()
551 irq_set_chip(virq, &data->irq_chip); in regmap_irq_map()
553 irq_set_parent(virq, data->irq); in regmap_irq_map()
560 .map = regmap_irq_map,
565 * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling
568 * @map: The regmap for the device.
570 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
572 * @chip: Configuration for the interrupt controller.
582 struct regmap *map, int irq, in regmap_add_irq_chip_fwnode() argument
589 int ret = -ENOMEM; in regmap_add_irq_chip_fwnode()
594 if (chip->num_regs <= 0) in regmap_add_irq_chip_fwnode()
595 return -EINVAL; in regmap_add_irq_chip_fwnode()
597 if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack)) in regmap_add_irq_chip_fwnode()
598 return -EINVAL; in regmap_add_irq_chip_fwnode()
600 for (i = 0; i < chip->num_irqs; i++) { in regmap_add_irq_chip_fwnode()
601 if (chip->irqs[i].reg_offset % map->reg_stride) in regmap_add_irq_chip_fwnode()
602 return -EINVAL; in regmap_add_irq_chip_fwnode()
603 if (chip->irqs[i].reg_offset / map->reg_stride >= in regmap_add_irq_chip_fwnode()
604 chip->num_regs) in regmap_add_irq_chip_fwnode()
605 return -EINVAL; in regmap_add_irq_chip_fwnode()
609 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0); in regmap_add_irq_chip_fwnode()
611 dev_warn(map->dev, "Failed to allocate IRQs: %d\n", in regmap_add_irq_chip_fwnode()
619 return -ENOMEM; in regmap_add_irq_chip_fwnode()
621 if (chip->num_main_regs) { in regmap_add_irq_chip_fwnode()
622 d->main_status_buf = kcalloc(chip->num_main_regs, in regmap_add_irq_chip_fwnode()
626 if (!d->main_status_buf) in regmap_add_irq_chip_fwnode()
630 d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int), in regmap_add_irq_chip_fwnode()
632 if (!d->status_buf) in regmap_add_irq_chip_fwnode()
635 d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int), in regmap_add_irq_chip_fwnode()
637 if (!d->mask_buf) in regmap_add_irq_chip_fwnode()
640 d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int), in regmap_add_irq_chip_fwnode()
642 if (!d->mask_buf_def) in regmap_add_irq_chip_fwnode()
645 if (chip->wake_base) { in regmap_add_irq_chip_fwnode()
646 d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int), in regmap_add_irq_chip_fwnode()
648 if (!d->wake_buf) in regmap_add_irq_chip_fwnode()
652 num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg; in regmap_add_irq_chip_fwnode()
654 d->type_buf_def = kcalloc(num_type_reg, in regmap_add_irq_chip_fwnode()
656 if (!d->type_buf_def) in regmap_add_irq_chip_fwnode()
659 d->type_buf = kcalloc(num_type_reg, sizeof(unsigned int), in regmap_add_irq_chip_fwnode()
661 if (!d->type_buf) in regmap_add_irq_chip_fwnode()
665 d->irq_chip = regmap_irq_chip; in regmap_add_irq_chip_fwnode()
666 d->irq_chip.name = chip->name; in regmap_add_irq_chip_fwnode()
667 d->irq = irq; in regmap_add_irq_chip_fwnode()
668 d->map = map; in regmap_add_irq_chip_fwnode()
669 d->chip = chip; in regmap_add_irq_chip_fwnode()
670 d->irq_base = irq_base; in regmap_add_irq_chip_fwnode()
672 if (chip->irq_reg_stride) in regmap_add_irq_chip_fwnode()
673 d->irq_reg_stride = chip->irq_reg_stride; in regmap_add_irq_chip_fwnode()
675 d->irq_reg_stride = 1; in regmap_add_irq_chip_fwnode()
677 if (chip->type_reg_stride) in regmap_add_irq_chip_fwnode()
678 d->type_reg_stride = chip->type_reg_stride; in regmap_add_irq_chip_fwnode()
680 d->type_reg_stride = 1; in regmap_add_irq_chip_fwnode()
682 if (!map->use_single_read && map->reg_stride == 1 && in regmap_add_irq_chip_fwnode()
683 d->irq_reg_stride == 1) { in regmap_add_irq_chip_fwnode()
684 d->status_reg_buf = kmalloc_array(chip->num_regs, in regmap_add_irq_chip_fwnode()
685 map->format.val_bytes, in regmap_add_irq_chip_fwnode()
687 if (!d->status_reg_buf) in regmap_add_irq_chip_fwnode()
691 mutex_init(&d->lock); in regmap_add_irq_chip_fwnode()
693 for (i = 0; i < chip->num_irqs; i++) in regmap_add_irq_chip_fwnode()
694 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride] in regmap_add_irq_chip_fwnode()
695 |= chip->irqs[i].mask; in regmap_add_irq_chip_fwnode()
697 /* Mask all the interrupts by default */ in regmap_add_irq_chip_fwnode()
698 for (i = 0; i < chip->num_regs; i++) { in regmap_add_irq_chip_fwnode()
699 d->mask_buf[i] = d->mask_buf_def[i]; in regmap_add_irq_chip_fwnode()
700 if (!chip->mask_base) in regmap_add_irq_chip_fwnode()
703 reg = chip->mask_base + in regmap_add_irq_chip_fwnode()
704 (i * map->reg_stride * d->irq_reg_stride); in regmap_add_irq_chip_fwnode()
705 if (chip->mask_invert) in regmap_add_irq_chip_fwnode()
707 d->mask_buf[i], ~d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
708 else if (d->chip->unmask_base) { in regmap_add_irq_chip_fwnode()
709 unmask_offset = d->chip->unmask_base - in regmap_add_irq_chip_fwnode()
710 d->chip->mask_base; in regmap_add_irq_chip_fwnode()
713 d->mask_buf[i], in regmap_add_irq_chip_fwnode()
714 d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
717 d->mask_buf[i], d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
719 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
724 if (!chip->init_ack_masked) in regmap_add_irq_chip_fwnode()
728 reg = chip->status_base + in regmap_add_irq_chip_fwnode()
729 (i * map->reg_stride * d->irq_reg_stride); in regmap_add_irq_chip_fwnode()
730 ret = regmap_read(map, reg, &d->status_buf[i]); in regmap_add_irq_chip_fwnode()
732 dev_err(map->dev, "Failed to read IRQ status: %d\n", in regmap_add_irq_chip_fwnode()
737 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) { in regmap_add_irq_chip_fwnode()
738 reg = chip->ack_base + in regmap_add_irq_chip_fwnode()
739 (i * map->reg_stride * d->irq_reg_stride); in regmap_add_irq_chip_fwnode()
740 if (chip->ack_invert) in regmap_add_irq_chip_fwnode()
741 ret = regmap_write(map, reg, in regmap_add_irq_chip_fwnode()
742 ~(d->status_buf[i] & d->mask_buf[i])); in regmap_add_irq_chip_fwnode()
744 ret = regmap_write(map, reg, in regmap_add_irq_chip_fwnode()
745 d->status_buf[i] & d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
746 if (chip->clear_ack) { in regmap_add_irq_chip_fwnode()
747 if (chip->ack_invert && !ret) in regmap_add_irq_chip_fwnode()
748 ret = regmap_write(map, reg, in regmap_add_irq_chip_fwnode()
749 (d->status_buf[i] & in regmap_add_irq_chip_fwnode()
750 d->mask_buf[i])); in regmap_add_irq_chip_fwnode()
752 ret = regmap_write(map, reg, in regmap_add_irq_chip_fwnode()
753 ~(d->status_buf[i] & in regmap_add_irq_chip_fwnode()
754 d->mask_buf[i])); in regmap_add_irq_chip_fwnode()
757 dev_err(map->dev, "Failed to ack 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
765 if (d->wake_buf) { in regmap_add_irq_chip_fwnode()
766 for (i = 0; i < chip->num_regs; i++) { in regmap_add_irq_chip_fwnode()
767 d->wake_buf[i] = d->mask_buf_def[i]; in regmap_add_irq_chip_fwnode()
768 reg = chip->wake_base + in regmap_add_irq_chip_fwnode()
769 (i * map->reg_stride * d->irq_reg_stride); in regmap_add_irq_chip_fwnode()
771 if (chip->wake_invert) in regmap_add_irq_chip_fwnode()
773 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
777 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
778 d->wake_buf[i]); in regmap_add_irq_chip_fwnode()
780 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
787 if (chip->num_type_reg && !chip->type_in_mask) { in regmap_add_irq_chip_fwnode()
788 for (i = 0; i < chip->num_type_reg; ++i) { in regmap_add_irq_chip_fwnode()
789 reg = chip->type_base + in regmap_add_irq_chip_fwnode()
790 (i * map->reg_stride * d->type_reg_stride); in regmap_add_irq_chip_fwnode()
792 ret = regmap_read(map, reg, &d->type_buf_def[i]); in regmap_add_irq_chip_fwnode()
794 if (d->chip->type_invert) in regmap_add_irq_chip_fwnode()
795 d->type_buf_def[i] = ~d->type_buf_def[i]; in regmap_add_irq_chip_fwnode()
798 dev_err(map->dev, "Failed to get type defaults at 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
806 d->domain = irq_domain_add_legacy(to_of_node(fwnode), in regmap_add_irq_chip_fwnode()
807 chip->num_irqs, irq_base, in regmap_add_irq_chip_fwnode()
810 d->domain = irq_domain_add_linear(to_of_node(fwnode), in regmap_add_irq_chip_fwnode()
811 chip->num_irqs, in regmap_add_irq_chip_fwnode()
813 if (!d->domain) { in regmap_add_irq_chip_fwnode()
814 dev_err(map->dev, "Failed to create IRQ domain\n"); in regmap_add_irq_chip_fwnode()
815 ret = -ENOMEM; in regmap_add_irq_chip_fwnode()
821 chip->name, d); in regmap_add_irq_chip_fwnode()
823 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n", in regmap_add_irq_chip_fwnode()
824 irq, chip->name, ret); in regmap_add_irq_chip_fwnode()
835 kfree(d->type_buf); in regmap_add_irq_chip_fwnode()
836 kfree(d->type_buf_def); in regmap_add_irq_chip_fwnode()
837 kfree(d->wake_buf); in regmap_add_irq_chip_fwnode()
838 kfree(d->mask_buf_def); in regmap_add_irq_chip_fwnode()
839 kfree(d->mask_buf); in regmap_add_irq_chip_fwnode()
840 kfree(d->status_buf); in regmap_add_irq_chip_fwnode()
841 kfree(d->status_reg_buf); in regmap_add_irq_chip_fwnode()
848 * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
850 * @map: The regmap for the device.
852 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
854 * @chip: Configuration for the interrupt controller.
862 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags, in regmap_add_irq_chip() argument
866 return regmap_add_irq_chip_fwnode(dev_fwnode(map->dev), map, irq, in regmap_add_irq_chip()
872 * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
890 for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) { in regmap_del_irq_chip()
892 if (!d->chip->irqs[hwirq].mask) in regmap_del_irq_chip()
899 virq = irq_find_mapping(d->domain, hwirq); in regmap_del_irq_chip()
904 irq_domain_remove(d->domain); in regmap_del_irq_chip()
905 kfree(d->type_buf); in regmap_del_irq_chip()
906 kfree(d->type_buf_def); in regmap_del_irq_chip()
907 kfree(d->wake_buf); in regmap_del_irq_chip()
908 kfree(d->mask_buf_def); in regmap_del_irq_chip()
909 kfree(d->mask_buf); in regmap_del_irq_chip()
910 kfree(d->status_reg_buf); in regmap_del_irq_chip()
911 kfree(d->status_buf); in regmap_del_irq_chip()
920 regmap_del_irq_chip(d->irq, d); in devm_regmap_irq_chip_release()
936 * devm_regmap_add_irq_chip_fwnode() - Resource managed regmap_add_irq_chip_fwnode()
940 * @map: The regmap for the device.
942 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
944 * @chip: Configuration for the interrupt controller.
954 struct regmap *map, int irq, in devm_regmap_add_irq_chip_fwnode() argument
965 return -ENOMEM; in devm_regmap_add_irq_chip_fwnode()
967 ret = regmap_add_irq_chip_fwnode(fwnode, map, irq, irq_flags, irq_base, in devm_regmap_add_irq_chip_fwnode()
982 * devm_regmap_add_irq_chip() - Resource manager regmap_add_irq_chip()
985 * @map: The regmap for the device.
987 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
989 * @chip: Configuration for the interrupt controller.
997 int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq, in devm_regmap_add_irq_chip() argument
1002 return devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(map->dev), map, in devm_regmap_add_irq_chip()
1009 * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
1022 WARN_ON(irq != data->irq); in devm_regmap_del_irq_chip()
1032 * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
1040 WARN_ON(!data->irq_base); in regmap_irq_chip_get_base()
1041 return data->irq_base; in regmap_irq_chip_get_base()
1046 * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
1049 * @irq: index of the interrupt requested in the chip IRQs.
1056 if (!data->chip->irqs[irq].mask) in regmap_irq_get_virq()
1057 return -EINVAL; in regmap_irq_get_virq()
1059 return irq_create_mapping(data->domain, irq); in regmap_irq_get_virq()
1064 * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
1076 return data->domain; in regmap_irq_get_domain()