Lines Matching +full:interrupt +full:- +full:map +full:- +full:mask

1 Broadcom BCM7120-style Level 2 interrupt controller
3 This interrupt controller hardware is a second level interrupt controller that
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
7 Such an interrupt controller has the following hardware design:
9 - outputs multiple interrupts signals towards its interrupt controller parent
11 - controls how some of the interrupts will be flowing, whether they will
12   directly output an interrupt signal towards the interrupt controller parent,
13   or if they will output an interrupt signal at this 2nd level interrupt
16 - has one 32-bit enable word and one 32-bit status word
18 - no atomic set/clear operations
20 - not all bits within the interrupt controller actually map to an interrupt
24 2nd level interrupt line		Outputs for the parent controller (e.g: ARM GIC)
26 0 -----[ MUX ] ------------|==========> GIC interrupt 75
27           \-----------\
29 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
30           \------------|
32 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
33           \------------|
35 3 ---------------------|
36 4 ---------------------|
37 5 ---------------------|
38 7 ---------------------|---|===========> GIC interrupt 66
39 9 ---------------------|
40 10 --------------------|
41 11 --------------------/
43 6 ------------------------\
44                            |===========> GIC interrupt 64
45 8 ------------------------/
54 - compatible: should be "brcm,bcm7120-l2-intc"
55 - reg: specifies the base physical address and size of the registers
56 - interrupt-controller: identifies the node as an interrupt controller
57 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
59 - interrupts: specifies the interrupt line(s) in the interrupt-parent controller
60   node, valid values depend on the type of parent interrupt controller
61 - brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
62   are wired to this 2nd level interrupt controller, and how they match their
63   respective interrupt parents. Should match exactly the number of interrupts
68 - brcm,irq-can-wake: if present, this means the L2 controller can be used as a
71 - brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which
73   respective interrupt outputs bypass this 2nd level interrupt controller
74   completely; it is completely transparent for the interrupt controller
75   parent. This should have one 32-bit word per enable/status pair.
79 irq0_intc: interrupt-controller@f0406800 {
80 	compatible = "brcm,bcm7120-l2-intc";
81 	interrupt-parent = <&intc>;
82 	#interrupt-cells = <1>;
84 	interrupt-controller;
86 	brcm,int-map-mask = <0xeb8>, <0x140>;
87 	brcm,int-fwd-mask = <0x7>;