Lines Matching +full:interrupt +full:- +full:map +full:- +full:mask

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Dilip Kota <eswara.kota@linux.intel.com>
16         const: intel,lgm-pcie
18     - compatible
23       - const: intel,lgm-pcie
24       - const: snps,dw-pcie
29   "#address-cells":
32   "#size-cells":
37       - description: Controller control and status registers.
38       - description: PCIe configuration registers.
39       - description: Controller application registers.
41   reg-names:
43       - const: dbi
44       - const: config
45       - const: app
59   phy-names:
62   reset-gpios:
65   linux,pci-domain: true
67   num-lanes:
71   '#interrupt-cells':
74   interrupt-map-mask:
77   interrupt-map:
80   max-link-speed:
86   bus-range:
89   reset-assert-ms:
96   - compatible
97   - device_type
98   - "#address-cells"
99   - "#size-cells"
100   - reg
101   - reg-names
102   - ranges
103   - resets
104   - clocks
105   - phys
106   - phy-names
107   - reset-gpios
108   - '#interrupt-cells'
109   - interrupt-map
110   - interrupt-map-mask
115   - |
116     #include <dt-bindings/gpio/gpio.h>
118       compatible = "intel,lgm-pcie", "snps,dw-pcie";
120       #address-cells = <3>;
121       #size-cells = <2>;
125       reg-names = "dbi", "config", "app";
126       linux,pci-domain = <0>;
127       max-link-speed = <4>;
128       bus-range = <0x00 0x08>;
129       #interrupt-cells = <1>;
130       interrupt-map-mask = <0 0 0 0x7>;
131       interrupt-map = <0 0 0 1 &ioapic1 27 1>,
139       phy-names = "pcie";
140       reset-assert-ms = <500>;
141       reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
142       num-lanes = <2>;