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/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Damdgpu_rlc.c40 if (adev->gfx.rlc.in_safe_mode[xcc_id]) in amdgpu_gfx_rlc_enter_safe_mode()
44 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.funcs->set_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_enter_safe_mode()
51 adev->gfx.rlc.in_safe_mode[xcc_id] = true; in amdgpu_gfx_rlc_enter_safe_mode()
65 if (!(adev->gfx.rlc.in_safe_mode[xcc_id])) in amdgpu_gfx_rlc_exit_safe_mode()
69 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
75 adev->gfx.rlc.funcs->unset_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_exit_safe_mode()
76 adev->gfx.rlc.in_safe_mode[xcc_id] = false; in amdgpu_gfx_rlc_exit_safe_mode()
100 &adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_init_sr()
101 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_init_sr()
[all …]
Damdgpu_gfx.c33 /* delay 0.1 second to enable gfx off feature */
39 * GPU GFX IP block helpers function.
47 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
48 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
49 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
58 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
59 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
60 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
61 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
62 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
[all …]
Dgfx_v6_0.c341 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v6_0_init_microcode()
344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_init_microcode()
345 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
346 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
349 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); in gfx_v6_0_init_microcode()
352 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_init_microcode()
353 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
354 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
357 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); in gfx_v6_0_init_microcode()
360 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v6_0_init_microcode()
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Dgfx_v11_0.c42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
195 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx11_kiq_unmap_queues()
263 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
435 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v11_0_free_microcode()
436 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v11_0_free_microcode()
437 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v11_0_free_microcode()
438 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v11_0_free_microcode()
440 kfree(adev->gfx.rlc.register_list_format); in gfx_v11_0_free_microcode()
472 if ((adev->gfx.me_fw_version >= 1505) && in gfx_v11_0_check_fw_cp_gfx_shadow()
473 (adev->gfx.pfp_fw_version >= 1600) && in gfx_v11_0_check_fw_cp_gfx_shadow()
[all …]
Dgfx_v7_0.c889 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v7_0_free_microcode()
890 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v7_0_free_microcode()
891 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v7_0_free_microcode()
892 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v7_0_free_microcode()
893 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v7_0_free_microcode()
894 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v7_0_free_microcode()
938 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v7_0_init_microcode()
943 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); in gfx_v7_0_init_microcode()
948 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); in gfx_v7_0_init_microcode()
953 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); in gfx_v7_0_init_microcode()
[all …]
Dgfx_v8_0.c927 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
928 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v8_0_free_microcode()
929 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
930 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
931 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v8_0_free_microcode()
934 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v8_0_free_microcode()
936 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
986 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v8_0_init_microcode()
989 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v8_0_init_microcode()
993 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v8_0_init_microcode()
[all …]
Dgfx_v9_0.c46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
893 adev->gfx.kiq[0].pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
1083 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
1084 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v9_0_free_microcode()
1085 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
1086 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v9_0_free_microcode()
1087 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v9_0_free_microcode()
1088 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v9_0_free_microcode()
1090 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_0_free_microcode()
1095 adev->gfx.me_fw_write_wait = false; in gfx_v9_0_check_fw_write_wait()
[all …]
Dgfx_v9_4_3.c34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
187 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_set_kiq_pm4_funcs()
189 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; in gfx_v9_4_3_set_kiq_pm4_funcs()
196 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_init_golden_registers()
343 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v9_4_3_get_gpu_clock_counter()
347 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v9_4_3_get_gpu_clock_counter()
354 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v9_4_3_free_microcode()
355 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v9_4_3_free_microcode()
356 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v9_4_3_free_microcode()
357 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v9_4_3_free_microcode()
[all …]
Damdgpu_atomfirmware.c776 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines; in amdgpu_atomfirmware_get_gfx_info()
777 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
778 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
779 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()
780 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches; in amdgpu_atomfirmware_get_gfx_info()
781 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); in amdgpu_atomfirmware_get_gfx_info()
782 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; in amdgpu_atomfirmware_get_gfx_info()
783 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth; in amdgpu_atomfirmware_get_gfx_info()
784 adev->gfx.config.gs_prim_buffer_depth = in amdgpu_atomfirmware_get_gfx_info()
786 adev->gfx.config.double_offchip_lds_buf = in amdgpu_atomfirmware_get_gfx_info()
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Damdgpu_kms.c225 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
226 fw_info->feature = adev->gfx.me_feature_version; in amdgpu_firmware_info()
229 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
230 fw_info->feature = adev->gfx.pfp_feature_version; in amdgpu_firmware_info()
233 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
234 fw_info->feature = adev->gfx.ce_feature_version; in amdgpu_firmware_info()
237 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
238 fw_info->feature = adev->gfx.rlc_feature_version; in amdgpu_firmware_info()
241 fw_info->ver = adev->gfx.rlc_srlc_fw_version; in amdgpu_firmware_info()
242 fw_info->feature = adev->gfx.rlc_srlc_feature_version; in amdgpu_firmware_info()
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Dgfx_v10_0.c40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
3557 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx10_kiq_unmap_queues()
3625 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
3880 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v10_0_free_microcode()
3881 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v10_0_free_microcode()
3882 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v10_0_free_microcode()
3883 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v10_0_free_microcode()
3884 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v10_0_free_microcode()
3885 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v10_0_free_microcode()
3887 kfree(adev->gfx.rlc.register_list_format); in gfx_v10_0_free_microcode()
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Damdgpu_amdkfd.c152 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, in amdgpu_amdkfd_device_init()
153 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, in amdgpu_amdkfd_device_init()
166 adev->gfx.mec_bitmap[0].queue_bitmap, in amdgpu_amdkfd_device_init()
173 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
174 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
390 return adev->gfx.pfp_fw_version; in amdgpu_amdkfd_get_fw_version()
393 return adev->gfx.me_fw_version; in amdgpu_amdkfd_get_fw_version()
396 return adev->gfx.ce_fw_version; in amdgpu_amdkfd_get_fw_version()
399 return adev->gfx.mec_fw_version; in amdgpu_amdkfd_get_fw_version()
402 return adev->gfx.mec2_fw_version; in amdgpu_amdkfd_get_fw_version()
[all …]
Damdgpu_ucode.c107 DRM_DEBUG("GFX\n"); in amdgpu_ucode_print_gfx_hdr()
125 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); in amdgpu_ucode_print_gfx_hdr()
687 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
688 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
689 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
690 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
691 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
692 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
693 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
694 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
[all …]
Damdgpu_gfx.h28 * GFX stuff
38 /* GFX current status */
165 * GFX configurations
223 /* gfx configure feature */
404 /* gfx status */
415 /* gfx off */
418 … gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: ad…
419 struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */
457 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
458 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((a…
[all …]
Damdgpu_debugfs.c130 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
131 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) { in amdgpu_debugfs_process_reg_op()
256 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_regs2_op()
257 (rd->id.grbm.se != 0xFFFFFFFF && rd->id.grbm.se >= adev->gfx.config.max_shader_engines)) { in amdgpu_debugfs_regs2_op()
433 if (adev->gfx.funcs->read_wave_data) in amdgpu_debugfs_gprwave_read()
434 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); in amdgpu_debugfs_gprwave_read()
438 if (adev->gfx.funcs->read_wave_vgprs) in amdgpu_debugfs_gprwave_read()
439 …adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread,… in amdgpu_debugfs_gprwave_read()
441 if (adev->gfx.funcs->read_wave_sgprs) in amdgpu_debugfs_gprwave_read()
442 …adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, dat… in amdgpu_debugfs_gprwave_read()
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Dimu_v11_0.c53 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, fw_name); in imu_v11_0_init_microcode()
56 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_init_microcode()
57 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); in imu_v11_0_init_microcode()
58 //adev->gfx.imu_feature_version = le32_to_cpu(imu_hdr->ucode_feature_version); in imu_v11_0_init_microcode()
63 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
68 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
78 amdgpu_ucode_release(&adev->gfx.imu_fw); in imu_v11_0_init_microcode()
90 if (!adev->gfx.imu_fw) in imu_v11_0_load_microcode()
93 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_load_microcode()
96 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + in imu_v11_0_load_microcode()
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Damdgpu_discovery.c631 adev->gfx.xcc_mask &= in amdgpu_discovery_read_from_harvest_table()
915 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; in amdgpu_discovery_get_harvest_info()
1206 adev->gfx.xcc_mask = 0; in amdgpu_discovery_reg_base_init()
1292 adev->gfx.xcc_mask |= in amdgpu_discovery_reg_base_init()
1417 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); in amdgpu_discovery_get_gfx_info()
1418 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + in amdgpu_discovery_get_gfx_info()
1420 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
1421 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
1422 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); in amdgpu_discovery_get_gfx_info()
1423 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); in amdgpu_discovery_get_gfx_info()
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Damdgpu_amdkfd_gfx_v9.c66 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_acquire_queue()
67 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_acquire_queue()
75 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in kgd_gfx_v9_get_queue_mask()
115 * need to do this twice, once for gfx and once for mmhub in kgd_gfx_v9_set_pasid_vmid_mapping()
166 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_init_interrupts()
167 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_init_interrupts()
307 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[inst].ring; in kgd_gfx_v9_hiq_mqd_load()
316 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_hiq_mqd_load()
317 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_hiq_mqd_load()
322 spin_lock(&adev->gfx.kiq[inst].ring_lock); in kgd_gfx_v9_hiq_mqd_load()
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/Linux-v6.6/Documentation/devicetree/bindings/gpu/
Daspeed-gfx.txt1 Device tree configuration for the GFX display device on the ASPEED SoCs
6 + aspeed,ast2500-gfx
7 + aspeed,ast2400-gfx
11 - reg: Physical base address and length of the GFX registers
13 - interrupts: interrupt number for the GFX device
17 - resets: reset line that must be released to use the GFX device
26 gfx: display@1e6e6000 {
27 compatible = "aspeed,ast2500-gfx", "syscon";
/Linux-v6.6/Documentation/devicetree/bindings/mfd/
Daspeed-gfx.txt1 * Device tree bindings for Aspeed SoC Display Controller (GFX)
8 - compatible: "aspeed,ast2500-gfx", "syscon"
9 - reg: contains offset/length value of the GFX memory
14 gfx: display@1e6e6000 {
15 compatible = "aspeed,ast2500-gfx", "syscon";
/Linux-v6.6/Documentation/ABI/testing/
Dsysfs-driver-intel-i915-hwmon4 Contact: intel-gfx@lists.freedesktop.org
12 Contact: intel-gfx@lists.freedesktop.org
26 Contact: intel-gfx@lists.freedesktop.org
34 Contact: intel-gfx@lists.freedesktop.org
43 Contact: intel-gfx@lists.freedesktop.org
56 Contact: intel-gfx@lists.freedesktop.org
69 Contact: intel-gfx@lists.freedesktop.org
/Linux-v6.6/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu_v13_0_1_ppsmc.h55 #define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power down GFX, i.e. enter GFXOFF
56 #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload
61 #define PPSMC_MSG_GfxDeviceDriverReset 0x11 ///< Request GFX mode 2 reset
67 #define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency
71 #define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK
72 #define PPSMC_MSG_SetHardMinGfxClk 0x1C ///< Set hard min for GFX CLK
83 #define PPSMC_MSG_RequestActiveWgp 0x27 ///< Request GFX active WGP number
/Linux-v6.6/drivers/pmdomain/qcom/
Drpmhpd.c107 static struct rpmhpd gfx = { variable
108 .pd = { .name = "gfx", },
109 .res_name = "gfx.lvl",
210 [SC8280XP_GFX] = &gfx,
230 [SA8775P_GFX] = &gfx,
252 [SDM670_GFX] = &gfx,
270 [SDM845_GFX] = &gfx,
328 [SM6350_GFX] = &gfx,
345 [SM8150_GFX] = &gfx,
364 [SA8155P_GFX] = &gfx,
[all …]
/Linux-v6.6/drivers/gpu/drm/loongson/
Dlsdc_gfxpll.c15 * GFX PLL is the PLL used by DC, GMC and GPU, the structure of the GFX PLL
139 /* GFX (DC, GPU, GMC) PLL initialization and destroy function */
177 const struct loongson_gfx_desc *gfx = to_loongson_gfx(ldev->descp); in loongson_gfxpll_create() local
186 this->reg_size = gfx->gfxpll.reg_size; in loongson_gfxpll_create()
187 this->reg_base = gfx->conf_reg_base + gfx->gfxpll.reg_offset; in loongson_gfxpll_create()
/Linux-v6.6/Documentation/gpu/amdgpu/
Ddriver-core.rst84 GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers
86 provides the driver interface to interact with the GFX/Compute engine.
90 GFX/compute engine.
96 This is another microcontroller in the GFX/Compute engine. It handles
97 power management related functionality within the GFX/Compute engine.
111 This is a control queue used by the kernel driver to manage other gfx
112 and compute queues on the GFX/compute engine. You can use it to

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