Lines Matching full:gfx
42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
195 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx11_kiq_unmap_queues()
263 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
435 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v11_0_free_microcode()
436 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v11_0_free_microcode()
437 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v11_0_free_microcode()
438 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v11_0_free_microcode()
440 kfree(adev->gfx.rlc.register_list_format); in gfx_v11_0_free_microcode()
472 if ((adev->gfx.me_fw_version >= 1505) && in gfx_v11_0_check_fw_cp_gfx_shadow()
473 (adev->gfx.pfp_fw_version >= 1600) && in gfx_v11_0_check_fw_cp_gfx_shadow()
474 (adev->gfx.mec_fw_version >= 512)) { in gfx_v11_0_check_fw_cp_gfx_shadow()
476 adev->gfx.cp_gfx_shadow = true; in gfx_v11_0_check_fw_cp_gfx_shadow()
478 adev->gfx.cp_gfx_shadow = false; in gfx_v11_0_check_fw_cp_gfx_shadow()
482 adev->gfx.cp_gfx_shadow = false; in gfx_v11_0_check_fw_cp_gfx_shadow()
501 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v11_0_init_microcode()
505 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( in gfx_v11_0_init_microcode()
507 adev->gfx.pfp_fw->data, 2, 0); in gfx_v11_0_init_microcode()
508 if (adev->gfx.rs64_enable) { in gfx_v11_0_init_microcode()
518 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); in gfx_v11_0_init_microcode()
521 if (adev->gfx.rs64_enable) { in gfx_v11_0_init_microcode()
531 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); in gfx_v11_0_init_microcode()
534 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v11_0_init_microcode()
543 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); in gfx_v11_0_init_microcode()
546 if (adev->gfx.rs64_enable) { in gfx_v11_0_init_microcode()
560 /* only one MEC for gfx 11.0.0. */ in gfx_v11_0_init_microcode()
561 adev->gfx.mec2_fw = NULL; in gfx_v11_0_init_microcode()
566 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v11_0_init_microcode()
567 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v11_0_init_microcode()
568 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v11_0_init_microcode()
569 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v11_0_init_microcode()
613 if (adev->gfx.rlc.cs_data == NULL) in gfx_v11_0_get_csb_buffer()
625 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v11_0_get_csb_buffer()
644 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); in gfx_v11_0_get_csb_buffer()
656 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v11_0_rlc_fini()
657 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v11_0_rlc_fini()
658 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v11_0_rlc_fini()
661 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v11_0_rlc_fini()
662 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v11_0_rlc_fini()
663 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v11_0_rlc_fini()
670 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v11_0_init_rlcg_reg_access_ctrl()
678 adev->gfx.rlc.rlcg_reg_access_supported = true; in gfx_v11_0_init_rlcg_reg_access_ctrl()
686 adev->gfx.rlc.cs_data = gfx11_cs_data; in gfx_v11_0_rlc_init()
688 cs_data = adev->gfx.rlc.cs_data; in gfx_v11_0_rlc_init()
698 if (adev->gfx.rlc.funcs->update_spm_vmid) in gfx_v11_0_rlc_init()
699 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); in gfx_v11_0_rlc_init()
706 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v11_0_mec_fini()
707 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v11_0_mec_fini()
708 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); in gfx_v11_0_mec_fini()
713 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); in gfx_v11_0_me_init()
724 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v11_0_mec_init()
728 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; in gfx_v11_0_mec_init()
733 &adev->gfx.mec.hpd_eop_obj, in gfx_v11_0_mec_init()
734 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v11_0_mec_init()
744 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v11_0_mec_init()
745 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v11_0_mec_init()
834 if (adev->gfx.cp_gfx_shadow) { in gfx_v11_0_get_gfx_shadow_info()
863 adev->gfx.config.max_hw_contexts = 8; in gfx_v11_0_gpu_early_init()
864 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
865 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
866 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v11_0_gpu_early_init()
867 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v11_0_gpu_early_init()
870 adev->gfx.ras = &gfx_v11_0_3_ras; in gfx_v11_0_gpu_early_init()
871 adev->gfx.config.max_hw_contexts = 8; in gfx_v11_0_gpu_early_init()
872 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
873 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
874 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v11_0_gpu_early_init()
875 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v11_0_gpu_early_init()
879 adev->gfx.config.max_hw_contexts = 8; in gfx_v11_0_gpu_early_init()
880 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
881 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
882 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; in gfx_v11_0_gpu_early_init()
883 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; in gfx_v11_0_gpu_early_init()
900 ring = &adev->gfx.gfx_ring[ring_id]; in gfx_v11_0_gfx_ring_init()
917 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v11_0_gfx_ring_init()
932 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v11_0_compute_ring_init()
942 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v11_0_compute_ring_init()
948 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v11_0_compute_ring_init()
953 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v11_0_compute_ring_init()
1009 &adev->gfx.rlc.rlc_autoload_bo, in gfx_v11_0_rlc_autoload_buffer_init()
1010 &adev->gfx.rlc.rlc_autoload_gpu_addr, in gfx_v11_0_rlc_autoload_buffer_init()
1011 (void **)&adev->gfx.rlc.rlc_autoload_ptr); in gfx_v11_0_rlc_autoload_buffer_init()
1029 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; in gfx_v11_0_rlc_backdoor_autoload_copy_ucode()
1084 if (adev->gfx.rs64_enable) { in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1087 adev->gfx.pfp_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1089 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1095 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1104 adev->gfx.me_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1106 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1112 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1121 adev->gfx.mec_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1123 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1129 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1143 adev->gfx.pfp_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1144 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1152 adev->gfx.me_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1153 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1161 adev->gfx.mec_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1162 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1172 adev->gfx.rlc_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1173 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1183 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1185 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1191 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
1276 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; in gfx_v11_0_rlc_backdoor_autoload_enable()
1284 if (adev->gfx.imu.funcs->load_microcode) in gfx_v11_0_rlc_backdoor_autoload_enable()
1285 adev->gfx.imu.funcs->load_microcode(adev); in gfx_v11_0_rlc_backdoor_autoload_enable()
1287 if (adev->gfx.imu.funcs->setup_imu) in gfx_v11_0_rlc_backdoor_autoload_enable()
1288 adev->gfx.imu.funcs->setup_imu(adev); in gfx_v11_0_rlc_backdoor_autoload_enable()
1289 if (adev->gfx.imu.funcs->start_imu) in gfx_v11_0_rlc_backdoor_autoload_enable()
1290 adev->gfx.imu.funcs->start_imu(adev); in gfx_v11_0_rlc_backdoor_autoload_enable()
1310 adev->gfx.me.num_me = 1; in gfx_v11_0_sw_init()
1311 adev->gfx.me.num_pipe_per_me = 1; in gfx_v11_0_sw_init()
1312 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v11_0_sw_init()
1313 adev->gfx.mec.num_mec = 2; in gfx_v11_0_sw_init()
1314 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v11_0_sw_init()
1315 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v11_0_sw_init()
1319 adev->gfx.me.num_me = 1; in gfx_v11_0_sw_init()
1320 adev->gfx.me.num_pipe_per_me = 1; in gfx_v11_0_sw_init()
1321 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v11_0_sw_init()
1322 adev->gfx.mec.num_mec = 1; in gfx_v11_0_sw_init()
1323 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v11_0_sw_init()
1324 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v11_0_sw_init()
1327 adev->gfx.me.num_me = 1; in gfx_v11_0_sw_init()
1328 adev->gfx.me.num_pipe_per_me = 1; in gfx_v11_0_sw_init()
1329 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v11_0_sw_init()
1330 adev->gfx.mec.num_mec = 1; in gfx_v11_0_sw_init()
1331 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v11_0_sw_init()
1332 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v11_0_sw_init()
1344 &adev->gfx.eop_irq); in gfx_v11_0_sw_init()
1351 &adev->gfx.priv_reg_irq); in gfx_v11_0_sw_init()
1358 &adev->gfx.priv_inst_irq); in gfx_v11_0_sw_init()
1365 &adev->gfx.rlc_gc_fed_irq); in gfx_v11_0_sw_init()
1369 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v11_0_sw_init()
1371 if (adev->gfx.imu.funcs) { in gfx_v11_0_sw_init()
1372 if (adev->gfx.imu.funcs->init_microcode) { in gfx_v11_0_sw_init()
1373 r = adev->gfx.imu.funcs->init_microcode(adev); in gfx_v11_0_sw_init()
1393 /* set up the gfx ring */ in gfx_v11_0_sw_init()
1394 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_sw_init()
1395 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
1396 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_sw_init()
1411 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_sw_init()
1412 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
1413 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v11_0_sw_init()
1435 kiq = &adev->gfx.kiq[0]; in gfx_v11_0_sw_init()
1457 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); in gfx_v11_0_sw_init()
1466 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, in gfx_v11_0_pfp_fini()
1467 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v11_0_pfp_fini()
1468 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v11_0_pfp_fini()
1470 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, in gfx_v11_0_pfp_fini()
1471 &adev->gfx.pfp.pfp_fw_data_gpu_addr, in gfx_v11_0_pfp_fini()
1472 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); in gfx_v11_0_pfp_fini()
1477 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, in gfx_v11_0_me_fini()
1478 &adev->gfx.me.me_fw_gpu_addr, in gfx_v11_0_me_fini()
1479 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v11_0_me_fini()
1481 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, in gfx_v11_0_me_fini()
1482 &adev->gfx.me.me_fw_data_gpu_addr, in gfx_v11_0_me_fini()
1483 (void **)&adev->gfx.me.me_fw_data_ptr); in gfx_v11_0_me_fini()
1488 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, in gfx_v11_0_rlc_autoload_buffer_fini()
1489 &adev->gfx.rlc.rlc_autoload_gpu_addr, in gfx_v11_0_rlc_autoload_buffer_fini()
1490 (void **)&adev->gfx.rlc.rlc_autoload_ptr); in gfx_v11_0_rlc_autoload_buffer_fini()
1498 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v11_0_sw_fini()
1499 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v11_0_sw_fini()
1500 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v11_0_sw_fini()
1501 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v11_0_sw_fini()
1506 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); in gfx_v11_0_sw_fini()
1562 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v11_0_get_sa_active_bitmap()
1563 adev->gfx.config.max_shader_engines); in gfx_v11_0_get_sa_active_bitmap()
1581 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * in gfx_v11_0_get_rb_active_bitmap()
1582 adev->gfx.config.max_shader_engines); in gfx_v11_0_get_rb_active_bitmap()
1602 max_sa = adev->gfx.config.max_shader_engines * in gfx_v11_0_setup_rb()
1603 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()
1604 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / in gfx_v11_0_setup_rb()
1605 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()
1612 adev->gfx.config.backend_enable_mask = active_rb_bitmap; in gfx_v11_0_setup_rb()
1613 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); in gfx_v11_0_setup_rb()
1665 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA in gfx_v11_0_init_gds_vmid()
1689 adev->gfx.config.tcc_disabled_mask = in gfx_v11_0_get_tcc_info()
1703 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); in gfx_v11_0_constants_init()
1705 adev->gfx.config.pa_sc_tile_steering_override = 0; in gfx_v11_0_constants_init()
1709 adev->gfx.config.ta_cntl2_truncate_coord_mode = in gfx_v11_0_constants_init()
1759 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v11_0_init_csb()
1762 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v11_0_init_csb()
1764 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v11_0_init_csb()
1765 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v11_0_init_csb()
1836 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v11_0_load_rlcg_microcode()
1837 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_load_rlcg_microcode()
1848 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcg_microcode()
1858 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; in gfx_v11_0_load_rlc_iram_dram_microcode()
1860 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_load_rlc_iram_dram_microcode()
1873 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlc_iram_dram_microcode()
1875 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_load_rlc_iram_dram_microcode()
1887 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlc_iram_dram_microcode()
1902 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; in gfx_v11_0_load_rlcp_rlcv_microcode()
1904 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_load_rlcp_rlcv_microcode()
1917 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcp_rlcv_microcode()
1923 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v11_0_load_rlcp_rlcv_microcode()
1936 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcp_rlcv_microcode()
1949 if (!adev->gfx.rlc_fw) in gfx_v11_0_rlc_load_microcode()
1952 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v11_0_rlc_load_microcode()
1988 adev->gfx.rlc.funcs->stop(adev); in gfx_v11_0_rlc_resume()
2005 adev->gfx.rlc.funcs->start(adev); in gfx_v11_0_rlc_resume()
2150 adev->gfx.pfp_fw->data; in gfx_v11_0_config_pfp_cache_rs64()
2200 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_config_pfp_cache_rs64()
2272 adev->gfx.me_fw->data; in gfx_v11_0_config_me_cache_rs64()
2323 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_config_me_cache_rs64()
2395 adev->gfx.mec_fw->data; in gfx_v11_0_config_mec_cache_rs64()
2409 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v11_0_config_mec_cache_rs64()
2478 adev->gfx.mec_fw->data; in gfx_v11_0_config_gfx_rs64()
2480 adev->gfx.me_fw->data; in gfx_v11_0_config_gfx_rs64()
2482 adev->gfx.pfp_fw->data; in gfx_v11_0_config_gfx_rs64()
2586 if (adev->gfx.rs64_enable) { in gfx_v11_0_wait_for_rlc_autoload_complete()
2587 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2589 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2594 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2596 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2601 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2603 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2609 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2614 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2619 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v11_0_wait_for_rlc_autoload_complete()
2646 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); in gfx_v11_0_cp_gfx_enable()
2659 adev->gfx.pfp_fw->data; in gfx_v11_0_cp_gfx_load_pfp_microcode()
2663 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_cp_gfx_load_pfp_microcode()
2669 &adev->gfx.pfp.pfp_fw_obj, in gfx_v11_0_cp_gfx_load_pfp_microcode()
2670 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v11_0_cp_gfx_load_pfp_microcode()
2671 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v11_0_cp_gfx_load_pfp_microcode()
2678 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); in gfx_v11_0_cp_gfx_load_pfp_microcode()
2680 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode()
2681 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode()
2683 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); in gfx_v11_0_cp_gfx_load_pfp_microcode()
2691 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v11_0_cp_gfx_load_pfp_microcode()
2706 adev->gfx.pfp_fw->data; in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2711 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2715 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2724 &adev->gfx.pfp.pfp_fw_obj, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2725 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2726 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2737 &adev->gfx.pfp.pfp_fw_data_obj, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2738 &adev->gfx.pfp.pfp_fw_data_gpu_addr, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2739 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2746 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2747 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2749 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2750 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2751 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2752 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2758 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2760 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2805 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2836 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2838 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2877 adev->gfx.me_fw->data; in gfx_v11_0_cp_gfx_load_me_microcode()
2881 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_cp_gfx_load_me_microcode()
2887 &adev->gfx.me.me_fw_obj, in gfx_v11_0_cp_gfx_load_me_microcode()
2888 &adev->gfx.me.me_fw_gpu_addr, in gfx_v11_0_cp_gfx_load_me_microcode()
2889 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v11_0_cp_gfx_load_me_microcode()
2896 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); in gfx_v11_0_cp_gfx_load_me_microcode()
2898 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); in gfx_v11_0_cp_gfx_load_me_microcode()
2899 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); in gfx_v11_0_cp_gfx_load_me_microcode()
2901 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); in gfx_v11_0_cp_gfx_load_me_microcode()
2909 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); in gfx_v11_0_cp_gfx_load_me_microcode()
2924 adev->gfx.me_fw->data; in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2929 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2933 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2942 &adev->gfx.me.me_fw_obj, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2943 &adev->gfx.me.me_fw_gpu_addr, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2944 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2955 &adev->gfx.me.me_fw_data_obj, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2956 &adev->gfx.me.me_fw_data_gpu_addr, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2957 (void **)&adev->gfx.me.me_fw_data_ptr); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2964 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2965 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2967 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2968 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2969 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2970 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2976 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2978 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3024 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3055 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3057 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3092 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) in gfx_v11_0_cp_gfx_load_microcode()
3097 if (adev->gfx.rs64_enable) in gfx_v11_0_cp_gfx_load_microcode()
3106 if (adev->gfx.rs64_enable) in gfx_v11_0_cp_gfx_load_microcode()
3128 adev->gfx.config.max_hw_contexts - 1); in gfx_v11_0_cp_gfx_start()
3134 ring = &adev->gfx.gfx_ring[0]; in gfx_v11_0_cp_gfx_start()
3166 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); in gfx_v11_0_cp_gfx_start()
3177 if (adev->gfx.num_gfx_rings > 1) { in gfx_v11_0_cp_gfx_start()
3178 /* maximum supported gfx ring is 2 */ in gfx_v11_0_cp_gfx_start()
3179 ring = &adev->gfx.gfx_ring[1]; in gfx_v11_0_cp_gfx_start()
3243 /* Init gfx ring 0 for pipe 0 */ in gfx_v11_0_cp_gfx_resume()
3248 ring = &adev->gfx.gfx_ring[0]; in gfx_v11_0_cp_gfx_resume()
3283 /* Init gfx ring 1 for pipe 1 */ in gfx_v11_0_cp_gfx_resume()
3284 if (adev->gfx.num_gfx_rings > 1) { in gfx_v11_0_cp_gfx_resume()
3287 /* maximum supported gfx ring is 2 */ in gfx_v11_0_cp_gfx_resume()
3288 ring = &adev->gfx.gfx_ring[1]; in gfx_v11_0_cp_gfx_resume()
3334 if (adev->gfx.rs64_enable) { in gfx_v11_0_cp_compute_enable()
3383 if (!adev->gfx.mec_fw) in gfx_v11_0_cp_compute_load_microcode()
3388 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v11_0_cp_compute_load_microcode()
3392 (adev->gfx.mec_fw->data + in gfx_v11_0_cp_compute_load_microcode()
3398 &adev->gfx.mec.mec_fw_obj, in gfx_v11_0_cp_compute_load_microcode()
3399 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v11_0_cp_compute_load_microcode()
3409 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v11_0_cp_compute_load_microcode()
3410 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v11_0_cp_compute_load_microcode()
3412 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); in gfx_v11_0_cp_compute_load_microcode()
3421 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v11_0_cp_compute_load_microcode()
3435 if (!adev->gfx.mec_fw) in gfx_v11_0_cp_compute_load_microcode_rs64()
3440 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; in gfx_v11_0_cp_compute_load_microcode_rs64()
3443 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v11_0_cp_compute_load_microcode_rs64()
3447 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v11_0_cp_compute_load_microcode_rs64()
3455 &adev->gfx.mec.mec_fw_obj, in gfx_v11_0_cp_compute_load_microcode_rs64()
3456 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v11_0_cp_compute_load_microcode_rs64()
3468 &adev->gfx.mec.mec_fw_data_obj, in gfx_v11_0_cp_compute_load_microcode_rs64()
3469 &adev->gfx.mec.mec_fw_data_gpu_addr, in gfx_v11_0_cp_compute_load_microcode_rs64()
3480 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v11_0_cp_compute_load_microcode_rs64()
3481 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); in gfx_v11_0_cp_compute_load_microcode_rs64()
3482 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v11_0_cp_compute_load_microcode_rs64()
3483 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); in gfx_v11_0_cp_compute_load_microcode_rs64()
3497 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v11_0_cp_compute_load_microcode_rs64()
3500 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3502 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); in gfx_v11_0_cp_compute_load_microcode_rs64()
3510 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3512 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v11_0_cp_compute_load_microcode_rs64()
3595 /* set up gfx hqd wptr */ in gfx_v11_0_gfx_mqd_init()
3626 /* set up gfx hqd base. this is similar as CP_RB_BASE */ in gfx_v11_0_gfx_mqd_init()
3677 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; in gfx_v11_0_gfx_init_queue()
3686 if (adev->gfx.me.mqd_backup[mqd_idx]) in gfx_v11_0_gfx_init_queue()
3687 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_gfx_init_queue()
3690 if (adev->gfx.me.mqd_backup[mqd_idx]) in gfx_v11_0_gfx_init_queue()
3691 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_gfx_init_queue()
3706 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_cp_async_gfx_ring_resume()
3707 ring = &adev->gfx.gfx_ring[i]; in gfx_v11_0_cp_async_gfx_ring_resume()
3979 if (adev->gfx.kiq[0].mqd_backup) in gfx_v11_0_kiq_init_queue()
3980 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4002 if (adev->gfx.kiq[0].mqd_backup) in gfx_v11_0_kiq_init_queue()
4003 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4013 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v11_0_kcq_init_queue()
4023 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v11_0_kcq_init_queue()
4024 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4027 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v11_0_kcq_init_queue()
4028 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4043 ring = &adev->gfx.kiq[0].ring; in gfx_v11_0_kiq_resume()
4071 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_kcq_resume()
4072 ring = &adev->gfx.compute_ring[i]; in gfx_v11_0_kcq_resume()
4107 if (adev->gfx.rs64_enable) in gfx_v11_0_cp_resume()
4143 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_cp_resume()
4144 ring = &adev->gfx.gfx_ring[i]; in gfx_v11_0_cp_resume()
4150 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_cp_resume()
4151 ring = &adev->gfx.compute_ring[i]; in gfx_v11_0_cp_resume()
4191 if (adev->gfx.rs64_enable) { in gfx_v11_0_select_cp_fw_arch()
4213 adev->gfx.config.gb_addr_config_fields.num_pkrs = in get_gb_addr_config()
4216 adev->gfx.config.gb_addr_config = gb_addr_config; in get_gb_addr_config()
4218 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in get_gb_addr_config()
4219 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4222 adev->gfx.config.max_tile_pipes = in get_gb_addr_config()
4223 adev->gfx.config.gb_addr_config_fields.num_pipes; in get_gb_addr_config()
4225 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in get_gb_addr_config()
4226 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4228 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in get_gb_addr_config()
4229 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4231 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in get_gb_addr_config()
4232 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4234 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in get_gb_addr_config()
4235 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
4260 if (adev->gfx.imu.funcs) { in gfx_v11_0_hw_init()
4262 if (adev->gfx.imu.funcs->program_rlc_ram) in gfx_v11_0_hw_init()
4263 adev->gfx.imu.funcs->program_rlc_ram(adev); in gfx_v11_0_hw_init()
4271 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { in gfx_v11_0_hw_init()
4272 if (adev->gfx.imu.funcs->load_microcode) in gfx_v11_0_hw_init()
4273 adev->gfx.imu.funcs->load_microcode(adev); in gfx_v11_0_hw_init()
4274 if (adev->gfx.imu.funcs->setup_imu) in gfx_v11_0_hw_init()
4275 adev->gfx.imu.funcs->setup_imu(adev); in gfx_v11_0_hw_init()
4276 if (adev->gfx.imu.funcs->start_imu) in gfx_v11_0_hw_init()
4277 adev->gfx.imu.funcs->start_imu(adev); in gfx_v11_0_hw_init()
4294 adev->gfx.is_poweron = true; in gfx_v11_0_hw_init()
4300 adev->gfx.rs64_enable) in gfx_v11_0_hw_init()
4313 * For gfx 11, rlc firmware loading relies on smu firmware is in gfx_v11_0_hw_init()
4353 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v11_0_hw_fini()
4354 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v11_0_hw_fini()
4381 adev->gfx.is_poweron = false; in gfx_v11_0_hw_fini()
4441 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_soft_reset()
4442 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v11_0_soft_reset()
4443 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v11_0_soft_reset()
4455 for (i = 0; i < adev->gfx.me.num_me; ++i) { in gfx_v11_0_soft_reset()
4456 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v11_0_soft_reset()
4457 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_soft_reset()
4551 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_check_soft_reset()
4552 ring = &adev->gfx.gfx_ring[i]; in gfx_v11_0_check_soft_reset()
4558 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_check_soft_reset()
4559 ring = &adev->gfx.compute_ring[i]; in gfx_v11_0_check_soft_reset()
4571 * GFX soft reset will impact MES, need resume MES when do GFX soft reset in gfx_v11_0_post_soft_reset()
4583 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v11_0_get_gpu_clock_counter()
4589 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v11_0_get_gpu_clock_counter()
4638 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; in gfx_v11_0_early_init()
4640 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; in gfx_v11_0_early_init()
4641 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v11_0_early_init()
4662 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v11_0_late_init()
4666 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v11_0_late_init()
5292 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { in gfx_v11_0_ring_emit_ib_gfx()
5471 /* set load_per_context_state & load_gfx_sh_regs for GFX */ in gfx_v11_0_ring_emit_cntxcntl()
5487 if (!adev->gfx.cp_gfx_shadow) in gfx_v11_0_ring_emit_gfx_shadow()
5534 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v11_0_ring_preempt_ib()
5587 gfx[0].gfx_meta_data) + in gfx_v11_0_ring_emit_de_meta()
5595 gfx[0].gds_backup) + in gfx_v11_0_ring_emit_de_meta()
5870 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v11_0_eop_irq()
5872 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); in gfx_v11_0_eop_irq()
5876 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_eop_irq()
5877 ring = &adev->gfx.compute_ring[i]; in gfx_v11_0_eop_irq()
5945 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_handle_priv_fault()
5946 ring = &adev->gfx.gfx_ring[i]; in gfx_v11_0_handle_priv_fault()
5947 /* we only enabled 1 gfx queue per pipe for now */ in gfx_v11_0_handle_priv_fault()
5954 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_handle_priv_fault()
5955 ring = &adev->gfx.compute_ring[i]; in gfx_v11_0_handle_priv_fault()
5989 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq) in gfx_v11_0_rlc_gc_fed_irq()
5990 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry); in gfx_v11_0_rlc_gc_fed_irq()
6002 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
6201 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; in gfx_v11_0_set_ring_funcs()
6203 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v11_0_set_ring_funcs()
6204 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; in gfx_v11_0_set_ring_funcs()
6206 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v11_0_set_ring_funcs()
6207 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; in gfx_v11_0_set_ring_funcs()
6231 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v11_0_set_irq_funcs()
6232 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; in gfx_v11_0_set_irq_funcs()
6234 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v11_0_set_irq_funcs()
6235 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; in gfx_v11_0_set_irq_funcs()
6237 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v11_0_set_irq_funcs()
6238 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; in gfx_v11_0_set_irq_funcs()
6240 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ in gfx_v11_0_set_irq_funcs()
6241 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; in gfx_v11_0_set_irq_funcs()
6248 adev->gfx.imu.mode = MISSION_MODE; in gfx_v11_0_set_imu_funcs()
6250 adev->gfx.imu.mode = DEBUG_MODE; in gfx_v11_0_set_imu_funcs()
6252 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; in gfx_v11_0_set_imu_funcs()
6257 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; in gfx_v11_0_set_rlc_funcs()
6262 unsigned total_cu = adev->gfx.config.max_cu_per_sh * in gfx_v11_0_set_gds_init()
6263 adev->gfx.config.max_sh_per_se * in gfx_v11_0_set_gds_init()
6264 adev->gfx.config.max_shader_engines; in gfx_v11_0_set_gds_init()
6274 /* set gfx eng mqd */ in gfx_v11_0_set_mqd_funcs()
6310 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); in gfx_v11_0_get_wgp_active_bitmap_per_sh()
6346 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v11_0_get_cu_info()
6347 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v11_0_get_cu_info()
6373 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v11_0_get_cu_info()