Lines Matching full:gfx
889 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v7_0_free_microcode()
890 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v7_0_free_microcode()
891 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v7_0_free_microcode()
892 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v7_0_free_microcode()
893 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v7_0_free_microcode()
894 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v7_0_free_microcode()
938 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v7_0_init_microcode()
943 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); in gfx_v7_0_init_microcode()
948 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); in gfx_v7_0_init_microcode()
953 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); in gfx_v7_0_init_microcode()
959 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); in gfx_v7_0_init_microcode()
965 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); in gfx_v7_0_init_microcode()
990 ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v7_0_tiling_mode_table_init()
992 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in gfx_v7_0_tiling_mode_table_init()
996 tile = adev->gfx.config.tile_mode_array; in gfx_v7_0_tiling_mode_table_init()
997 macrotile = adev->gfx.config.macrotile_mode_array; in gfx_v7_0_tiling_mode_table_init()
999 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v7_0_tiling_mode_table_init()
1596 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v7_0_get_rb_active_bitmap()
1597 adev->gfx.config.max_sh_per_se); in gfx_v7_0_get_rb_active_bitmap()
1639 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v7_0_write_harvested_raster_configs()
1640 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v7_0_write_harvested_raster_configs()
1756 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v7_0_setup_rb()
1757 adev->gfx.config.max_sh_per_se; in gfx_v7_0_setup_rb()
1761 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_setup_rb()
1762 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1765 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v7_0_setup_rb()
1771 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v7_0_setup_rb()
1772 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v7_0_setup_rb()
1774 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v7_0_setup_rb()
1775 adev->gfx.config.max_shader_engines, 16); in gfx_v7_0_setup_rb()
1779 if (!adev->gfx.config.backend_enable_mask || in gfx_v7_0_setup_rb()
1780 adev->gfx.config.num_rbs >= num_rb_pipes) { in gfx_v7_0_setup_rb()
1785 adev->gfx.config.backend_enable_mask, in gfx_v7_0_setup_rb()
1790 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_setup_rb()
1791 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1793 adev->gfx.config.rb_config[i][j].rb_backend_disable = in gfx_v7_0_setup_rb()
1795 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = in gfx_v7_0_setup_rb()
1797 adev->gfx.config.rb_config[i][j].raster_config = in gfx_v7_0_setup_rb()
1799 adev->gfx.config.rb_config[i][j].raster_config_1 = in gfx_v7_0_setup_rb()
1859 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA in gfx_v7_0_init_gds_vmid()
1874 adev->gfx.config.double_offchip_lds_buf = 1; in gfx_v7_0_config_init()
1882 * init the gfx constants such as the 3D engine, tiling configuration
1893 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
1894 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
1895 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
1979 …((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIF… in gfx_v7_0_constants_init()
1980 …(adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | in gfx_v7_0_constants_init()
1981 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | in gfx_v7_0_constants_init()
1982 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); in gfx_v7_0_constants_init()
2018 * gfx_v7_0_ring_test_ring - basic gfx ring test
2022 * Allocate a scratch register and write to it using the gfx ring (CIK).
2023 * Provides a basic gfx ring test to verify that the ring is working.
2105 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2112 * Emits a fence sequence number on the gfx ring and flushes
2190 * on the gfx ring. IBs are usually generated by userspace
2193 * on the gfx ring for execution by the GPU.
2286 * Allocate an IB and execute it on the gfx ring (CIK).
2287 * Provides a basic gfx ring test to verify that IBs are working.
2334 * On CIK, gfx and compute now have independent command processors.
2336 * GFX
2337 * Gfx consists of a single ring and can process both gfx jobs and
2338 * compute jobs. The gfx CP consists of three microengines (ME):
2356 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2361 * Halts or unhalts the gfx MEs.
2375 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2379 * Loads the gfx PFP, ME, and CE ucode.
2390 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v7_0_cp_gfx_load_microcode()
2393 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2394 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2395 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2400 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2401 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2402 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2403 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2404 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2405 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2411 (adev->gfx.pfp_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2417 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2421 (adev->gfx.ce_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2427 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2431 (adev->gfx.me_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2437 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2443 * gfx_v7_0_cp_gfx_start - start the gfx ring
2453 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_start()
2459 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v7_0_cp_gfx_start()
2471 /* init the CE partitions. CE only used for gfx on CIK */ in gfx_v7_0_cp_gfx_start()
2485 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_cp_gfx_start()
2499 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); in gfx_v7_0_cp_gfx_start()
2500 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v7_0_cp_gfx_start()
2519 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2523 * Program the location and size of the gfx ring buffer
2547 /* ring 0 - compute and gfx */ in gfx_v7_0_cp_gfx_resume()
2549 ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_resume()
2653 if (!adev->gfx.mec_fw) in gfx_v7_0_cp_compute_load_microcode()
2656 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v7_0_cp_compute_load_microcode()
2658 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); in gfx_v7_0_cp_compute_load_microcode()
2659 adev->gfx.mec_feature_version = le32_to_cpu( in gfx_v7_0_cp_compute_load_microcode()
2666 (adev->gfx.mec_fw->data + in gfx_v7_0_cp_compute_load_microcode()
2677 if (!adev->gfx.mec2_fw) in gfx_v7_0_cp_compute_load_microcode()
2680 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; in gfx_v7_0_cp_compute_load_microcode()
2682 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); in gfx_v7_0_cp_compute_load_microcode()
2683 adev->gfx.mec2_feature_version = le32_to_cpu( in gfx_v7_0_cp_compute_load_microcode()
2688 (adev->gfx.mec2_fw->data + in gfx_v7_0_cp_compute_load_microcode()
2712 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_fini()
2713 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_cp_compute_fini()
2721 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v7_0_mec_fini()
2730 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v7_0_mec_init()
2736 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec in gfx_v7_0_mec_init()
2742 &adev->gfx.mec.hpd_eop_obj, in gfx_v7_0_mec_init()
2743 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v7_0_mec_init()
2754 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v7_0_mec_init()
2755 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v7_0_mec_init()
2803 size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe) in gfx_v7_0_compute_pipe_init()
2807 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset; in gfx_v7_0_compute_pipe_init()
3002 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v7_0_compute_queue_init()
3048 for (i = 0; i < adev->gfx.mec.num_mec; i++) in gfx_v7_0_cp_compute_resume()
3049 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) in gfx_v7_0_cp_compute_resume()
3053 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()
3063 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()
3064 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_cp_compute_resume()
3236 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3237 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3240 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3241 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3245 adev->gfx.rlc.cs_data = ci_cs_data; in gfx_v7_0_rlc_init()
3246 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ in gfx_v7_0_rlc_init()
3247 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ in gfx_v7_0_rlc_init()
3249 src_ptr = adev->gfx.rlc.reg_list; in gfx_v7_0_rlc_init()
3250 dws = adev->gfx.rlc.reg_list_size; in gfx_v7_0_rlc_init()
3253 cs_data = adev->gfx.rlc.cs_data; in gfx_v7_0_rlc_init()
3269 if (adev->gfx.rlc.cp_table_size) { in gfx_v7_0_rlc_init()
3276 if (adev->gfx.rlc.funcs->update_spm_vmid) in gfx_v7_0_rlc_init()
3277 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); in gfx_v7_0_rlc_init()
3300 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_wait_for_rlc_serdes()
3301 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_wait_for_rlc_serdes()
3452 if (!adev->gfx.rlc_fw) in gfx_v7_0_rlc_resume()
3455 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; in gfx_v7_0_rlc_resume()
3457 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); in gfx_v7_0_rlc_resume()
3458 adev->gfx.rlc_feature_version = le32_to_cpu( in gfx_v7_0_rlc_resume()
3461 adev->gfx.rlc.funcs->stop(adev); in gfx_v7_0_rlc_resume()
3467 adev->gfx.rlc.funcs->reset(adev); in gfx_v7_0_rlc_resume()
3485 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gfx_v7_0_rlc_resume()
3490 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v7_0_rlc_resume()
3498 adev->gfx.rlc.funcs->start(adev); in gfx_v7_0_rlc_resume()
3778 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v7_0_get_cu_active_bitmap()
3787 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); in gfx_v7_0_init_ao_cu_mask()
3791 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); in gfx_v7_0_init_ao_cu_mask()
3831 if (adev->gfx.rlc.cs_data) { in gfx_v7_0_init_gfx_cgpg()
3833 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3834 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3835 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); in gfx_v7_0_init_gfx_cgpg()
3841 if (adev->gfx.rlc.reg_list) { in gfx_v7_0_init_gfx_cgpg()
3843 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) in gfx_v7_0_init_gfx_cgpg()
3844 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); in gfx_v7_0_init_gfx_cgpg()
3852 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v7_0_init_gfx_cgpg()
3853 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v7_0_init_gfx_cgpg()
3888 if (adev->gfx.rlc.cs_data == NULL) in gfx_v7_0_get_csb_size()
3896 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_get_csb_size()
3921 if (adev->gfx.rlc.cs_data == NULL) in gfx_v7_0_get_csb_buffer()
3933 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_get_csb_buffer()
4028 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v7_0_get_gpu_clock_counter()
4032 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v7_0_get_gpu_clock_counter()
4179 adev->gfx.xcc_mask = 1; in gfx_v7_0_early_init()
4180 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; in gfx_v7_0_early_init()
4181 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v7_0_early_init()
4183 adev->gfx.funcs = &gfx_v7_0_gfx_funcs; in gfx_v7_0_early_init()
4184 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs; in gfx_v7_0_early_init()
4197 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v7_0_late_init()
4201 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v7_0_late_init()
4217 adev->gfx.config.max_shader_engines = 2; in gfx_v7_0_gpu_early_init()
4218 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()
4219 adev->gfx.config.max_cu_per_sh = 7; in gfx_v7_0_gpu_early_init()
4220 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4221 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()
4222 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v7_0_gpu_early_init()
4223 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4224 adev->gfx.config.max_gs_threads = 32; in gfx_v7_0_gpu_early_init()
4225 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4227 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4228 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4229 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4230 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4234 adev->gfx.config.max_shader_engines = 4; in gfx_v7_0_gpu_early_init()
4235 adev->gfx.config.max_tile_pipes = 16; in gfx_v7_0_gpu_early_init()
4236 adev->gfx.config.max_cu_per_sh = 11; in gfx_v7_0_gpu_early_init()
4237 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4238 adev->gfx.config.max_backends_per_se = 4; in gfx_v7_0_gpu_early_init()
4239 adev->gfx.config.max_texture_channel_caches = 16; in gfx_v7_0_gpu_early_init()
4240 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4241 adev->gfx.config.max_gs_threads = 32; in gfx_v7_0_gpu_early_init()
4242 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4244 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4245 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4246 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4247 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4251 adev->gfx.config.max_shader_engines = 1; in gfx_v7_0_gpu_early_init()
4252 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()
4253 adev->gfx.config.max_cu_per_sh = 8; in gfx_v7_0_gpu_early_init()
4254 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()
4255 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4256 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v7_0_gpu_early_init()
4257 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4258 adev->gfx.config.max_gs_threads = 16; in gfx_v7_0_gpu_early_init()
4259 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4261 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4262 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4263 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4264 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4270 adev->gfx.config.max_shader_engines = 1; in gfx_v7_0_gpu_early_init()
4271 adev->gfx.config.max_tile_pipes = 2; in gfx_v7_0_gpu_early_init()
4272 adev->gfx.config.max_cu_per_sh = 2; in gfx_v7_0_gpu_early_init()
4273 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4274 adev->gfx.config.max_backends_per_se = 1; in gfx_v7_0_gpu_early_init()
4275 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v7_0_gpu_early_init()
4276 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4277 adev->gfx.config.max_gs_threads = 16; in gfx_v7_0_gpu_early_init()
4278 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4280 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4281 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4282 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4283 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4288 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v7_0_gpu_early_init()
4289 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; in gfx_v7_0_gpu_early_init()
4291 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v7_0_gpu_early_init()
4293 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v7_0_gpu_early_init()
4296 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v7_0_gpu_early_init()
4297 adev->gfx.config.mem_max_burst_length_bytes = 256; in gfx_v7_0_gpu_early_init()
4321 adev->gfx.config.mem_row_size_in_kb = 2; in gfx_v7_0_gpu_early_init()
4323 adev->gfx.config.mem_row_size_in_kb = 1; in gfx_v7_0_gpu_early_init()
4326 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in gfx_v7_0_gpu_early_init()
4327 if (adev->gfx.config.mem_row_size_in_kb > 4) in gfx_v7_0_gpu_early_init()
4328 adev->gfx.config.mem_row_size_in_kb = 4; in gfx_v7_0_gpu_early_init()
4331 adev->gfx.config.shader_engine_tile_size = 32; in gfx_v7_0_gpu_early_init()
4332 adev->gfx.config.num_gpus = 1; in gfx_v7_0_gpu_early_init()
4333 adev->gfx.config.multi_gpu_tile_size = 64; in gfx_v7_0_gpu_early_init()
4337 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v7_0_gpu_early_init()
4349 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v7_0_gpu_early_init()
4357 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v7_0_compute_ring_init()
4370 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v7_0_compute_ring_init()
4375 &adev->gfx.eop_irq, irq_type, in gfx_v7_0_compute_ring_init()
4392 adev->gfx.mec.num_mec = 2; in gfx_v7_0_sw_init()
4399 adev->gfx.mec.num_mec = 1; in gfx_v7_0_sw_init()
4402 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v7_0_sw_init()
4403 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v7_0_sw_init()
4406 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); in gfx_v7_0_sw_init()
4412 &adev->gfx.priv_reg_irq); in gfx_v7_0_sw_init()
4418 &adev->gfx.priv_inst_irq); in gfx_v7_0_sw_init()
4424 DRM_ERROR("Failed to load gfx firmware!\n"); in gfx_v7_0_sw_init()
4428 r = adev->gfx.rlc.funcs->init(adev); in gfx_v7_0_sw_init()
4441 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v7_0_sw_init()
4442 ring = &adev->gfx.gfx_ring[i]; in gfx_v7_0_sw_init()
4444 sprintf(ring->name, "gfx"); in gfx_v7_0_sw_init()
4446 &adev->gfx.eop_irq, in gfx_v7_0_sw_init()
4455 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v7_0_sw_init()
4456 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v7_0_sw_init()
4457 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v7_0_sw_init()
4473 adev->gfx.ce_ram_size = 0x8000; in gfx_v7_0_sw_init()
4485 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_sw_fini()
4486 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v7_0_sw_fini()
4487 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_sw_fini()
4488 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v7_0_sw_fini()
4493 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v7_0_sw_fini()
4494 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v7_0_sw_fini()
4495 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v7_0_sw_fini()
4496 if (adev->gfx.rlc.cp_table_size) { in gfx_v7_0_sw_fini()
4497 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v7_0_sw_fini()
4498 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v7_0_sw_fini()
4499 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v7_0_sw_fini()
4514 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v7_0_hw_init()
4516 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v7_0_hw_init()
4531 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v7_0_hw_fini()
4532 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v7_0_hw_fini()
4534 adev->gfx.rlc.funcs->stop(adev); in gfx_v7_0_hw_fini()
4619 adev->gfx.rlc.funcs->stop(adev); in gfx_v7_0_soft_reset()
4621 /* Disable GFX parsing/prefetching */ in gfx_v7_0_soft_reset()
4834 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v7_0_eop_irq()
4838 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_eop_irq()
4839 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_eop_irq()
4859 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); in gfx_v7_0_fault()
4863 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_fault()
4864 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_fault()
4886 // XXX soft reset the gfx block only in gfx_v7_0_priv_inst_irq()
5051 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_set_ring_funcs()
5052 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; in gfx_v7_0_set_ring_funcs()
5053 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_set_ring_funcs()
5054 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; in gfx_v7_0_set_ring_funcs()
5074 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v7_0_set_irq_funcs()
5075 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; in gfx_v7_0_set_irq_funcs()
5077 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v7_0_set_irq_funcs()
5078 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; in gfx_v7_0_set_irq_funcs()
5080 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v7_0_set_irq_funcs()
5081 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; in gfx_v7_0_set_irq_funcs()
5098 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v7_0_get_cu_info()
5105 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v7_0_get_cu_info()
5112 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_get_cu_info()
5113 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_get_cu_info()
5124 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v7_0_get_cu_info()