Lines Matching full:gfx
40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
3557 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx10_kiq_unmap_queues()
3625 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
3880 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v10_0_free_microcode()
3881 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v10_0_free_microcode()
3882 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v10_0_free_microcode()
3883 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v10_0_free_microcode()
3884 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v10_0_free_microcode()
3885 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v10_0_free_microcode()
3887 kfree(adev->gfx.rlc.register_list_format); in gfx_v10_0_free_microcode()
3892 adev->gfx.cp_fw_write_wait = false; in gfx_v10_0_check_fw_write_wait()
3900 if ((adev->gfx.me_fw_version >= 0x00000046) && in gfx_v10_0_check_fw_write_wait()
3901 (adev->gfx.me_feature_version >= 27) && in gfx_v10_0_check_fw_write_wait()
3902 (adev->gfx.pfp_fw_version >= 0x00000068) && in gfx_v10_0_check_fw_write_wait()
3903 (adev->gfx.pfp_feature_version >= 27) && in gfx_v10_0_check_fw_write_wait()
3904 (adev->gfx.mec_fw_version >= 0x0000005b) && in gfx_v10_0_check_fw_write_wait()
3905 (adev->gfx.mec_feature_version >= 27)) in gfx_v10_0_check_fw_write_wait()
3906 adev->gfx.cp_fw_write_wait = true; in gfx_v10_0_check_fw_write_wait()
3916 adev->gfx.cp_fw_write_wait = true; in gfx_v10_0_check_fw_write_wait()
3922 if (!adev->gfx.cp_fw_write_wait) in gfx_v10_0_check_fw_write_wait()
3973 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v10_0_init_microcode()
3979 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); in gfx_v10_0_init_microcode()
3985 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); in gfx_v10_0_init_microcode()
3992 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); in gfx_v10_0_init_microcode()
4002 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v10_0_init_microcode()
4011 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); in gfx_v10_0_init_microcode()
4018 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); in gfx_v10_0_init_microcode()
4024 adev->gfx.mec2_fw = NULL; in gfx_v10_0_init_microcode()
4032 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v10_0_init_microcode()
4033 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v10_0_init_microcode()
4034 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v10_0_init_microcode()
4035 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v10_0_init_microcode()
4036 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v10_0_init_microcode()
4037 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v10_0_init_microcode()
4083 if (adev->gfx.rlc.cs_data == NULL) in gfx_v10_0_get_csb_buffer()
4095 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v10_0_get_csb_buffer()
4114 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); in gfx_v10_0_get_csb_buffer()
4126 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v10_0_rlc_fini()
4127 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v10_0_rlc_fini()
4128 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v10_0_rlc_fini()
4131 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v10_0_rlc_fini()
4132 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v10_0_rlc_fini()
4133 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v10_0_rlc_fini()
4140 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v10_0_init_rlcg_reg_access_ctrl()
4157 adev->gfx.rlc.rlcg_reg_access_supported = true; in gfx_v10_0_init_rlcg_reg_access_ctrl()
4165 adev->gfx.rlc.cs_data = gfx10_cs_data; in gfx_v10_0_rlc_init()
4167 cs_data = adev->gfx.rlc.cs_data; in gfx_v10_0_rlc_init()
4181 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v10_0_mec_fini()
4182 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v10_0_mec_fini()
4187 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); in gfx_v10_0_me_init()
4203 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v10_0_mec_init()
4207 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; in gfx_v10_0_mec_init()
4212 &adev->gfx.mec.hpd_eop_obj, in gfx_v10_0_mec_init()
4213 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v10_0_mec_init()
4223 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v10_0_mec_init()
4224 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v10_0_mec_init()
4228 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v10_0_mec_init()
4230 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v10_0_mec_init()
4236 &adev->gfx.mec.mec_fw_obj, in gfx_v10_0_mec_init()
4237 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v10_0_mec_init()
4247 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v10_0_mec_init()
4248 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v10_0_mec_init()
4365 adev->gfx.config.max_hw_contexts = 8; in gfx_v10_0_gpu_early_init()
4366 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v10_0_gpu_early_init()
4367 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v10_0_gpu_early_init()
4368 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v10_0_gpu_early_init()
4369 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v10_0_gpu_early_init()
4380 adev->gfx.config.max_hw_contexts = 8; in gfx_v10_0_gpu_early_init()
4381 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v10_0_gpu_early_init()
4382 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v10_0_gpu_early_init()
4383 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v10_0_gpu_early_init()
4384 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v10_0_gpu_early_init()
4386 adev->gfx.config.gb_addr_config_fields.num_pkrs = in gfx_v10_0_gpu_early_init()
4391 adev->gfx.config.max_hw_contexts = 8; in gfx_v10_0_gpu_early_init()
4392 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v10_0_gpu_early_init()
4393 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v10_0_gpu_early_init()
4394 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v10_0_gpu_early_init()
4395 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v10_0_gpu_early_init()
4403 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v10_0_gpu_early_init()
4405 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v10_0_gpu_early_init()
4406 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4409 adev->gfx.config.max_tile_pipes = in gfx_v10_0_gpu_early_init()
4410 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v10_0_gpu_early_init()
4412 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v10_0_gpu_early_init()
4413 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4415 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v10_0_gpu_early_init()
4416 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4418 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v10_0_gpu_early_init()
4419 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4421 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v10_0_gpu_early_init()
4422 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4433 ring = &adev->gfx.gfx_ring[ring_id]; in gfx_v10_0_gfx_ring_init()
4452 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v10_0_gfx_ring_init()
4463 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v10_0_compute_ring_init()
4473 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v10_0_compute_ring_init()
4479 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v10_0_compute_ring_init()
4484 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v10_0_compute_ring_init()
4500 adev->gfx.me.num_me = 1; in gfx_v10_0_sw_init()
4501 adev->gfx.me.num_pipe_per_me = 1; in gfx_v10_0_sw_init()
4502 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v10_0_sw_init()
4503 adev->gfx.mec.num_mec = 2; in gfx_v10_0_sw_init()
4504 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v10_0_sw_init()
4505 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v10_0_sw_init()
4515 adev->gfx.me.num_me = 1; in gfx_v10_0_sw_init()
4516 adev->gfx.me.num_pipe_per_me = 1; in gfx_v10_0_sw_init()
4517 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v10_0_sw_init()
4518 adev->gfx.mec.num_mec = 2; in gfx_v10_0_sw_init()
4519 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v10_0_sw_init()
4520 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v10_0_sw_init()
4523 adev->gfx.me.num_me = 1; in gfx_v10_0_sw_init()
4524 adev->gfx.me.num_pipe_per_me = 1; in gfx_v10_0_sw_init()
4525 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v10_0_sw_init()
4526 adev->gfx.mec.num_mec = 1; in gfx_v10_0_sw_init()
4527 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v10_0_sw_init()
4528 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v10_0_sw_init()
4535 &adev->gfx.kiq[0].irq); in gfx_v10_0_sw_init()
4542 &adev->gfx.eop_irq); in gfx_v10_0_sw_init()
4548 &adev->gfx.priv_reg_irq); in gfx_v10_0_sw_init()
4554 &adev->gfx.priv_inst_irq); in gfx_v10_0_sw_init()
4558 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v10_0_sw_init()
4562 if (adev->gfx.rlc.funcs) { in gfx_v10_0_sw_init()
4563 if (adev->gfx.rlc.funcs->init) { in gfx_v10_0_sw_init()
4564 r = adev->gfx.rlc.funcs->init(adev); in gfx_v10_0_sw_init()
4578 /* set up the gfx ring */ in gfx_v10_0_sw_init()
4579 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v10_0_sw_init()
4580 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v10_0_sw_init()
4581 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v10_0_sw_init()
4596 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v10_0_sw_init()
4597 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v10_0_sw_init()
4598 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v10_0_sw_init()
4620 kiq = &adev->gfx.kiq[0]; in gfx_v10_0_sw_init()
4637 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; in gfx_v10_0_sw_init()
4646 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, in gfx_v10_0_pfp_fini()
4647 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v10_0_pfp_fini()
4648 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v10_0_pfp_fini()
4653 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, in gfx_v10_0_ce_fini()
4654 &adev->gfx.ce.ce_fw_gpu_addr, in gfx_v10_0_ce_fini()
4655 (void **)&adev->gfx.ce.ce_fw_ptr); in gfx_v10_0_ce_fini()
4660 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, in gfx_v10_0_me_fini()
4661 &adev->gfx.me.me_fw_gpu_addr, in gfx_v10_0_me_fini()
4662 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v10_0_me_fini()
4670 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v10_0_sw_fini()
4671 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v10_0_sw_fini()
4672 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v10_0_sw_fini()
4673 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v10_0_sw_fini()
4678 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); in gfx_v10_0_sw_fini()
4733 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v10_0_get_rb_active_bitmap()
4734 adev->gfx.config.max_sh_per_se); in gfx_v10_0_get_rb_active_bitmap()
4745 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v10_0_setup_rb()
4746 adev->gfx.config.max_sh_per_se; in gfx_v10_0_setup_rb()
4749 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v10_0_setup_rb()
4750 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_setup_rb()
4751 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_setup_rb()
4759 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v10_0_setup_rb()
4766 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v10_0_setup_rb()
4767 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v10_0_setup_rb()
4779 /* for ASICs that integrates GFX v10.3 in gfx_v10_0_init_pa_sc_tile_steering_override()
4786 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * in gfx_v10_0_init_pa_sc_tile_steering_override()
4787 adev->gfx.config.num_sc_per_sh; in gfx_v10_0_init_pa_sc_tile_steering_override()
4791 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; in gfx_v10_0_init_pa_sc_tile_steering_override()
4793 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; in gfx_v10_0_init_pa_sc_tile_steering_override()
4877 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA in gfx_v10_0_init_gds_vmid()
4894 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; in gfx_v10_0_tcp_harvest()
4919 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v10_0_tcp_harvest()
4920 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_tcp_harvest()
4971 adev->gfx.config.tcc_disabled_mask = in gfx_v10_0_get_tcc_info()
4984 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); in gfx_v10_0_constants_init()
4986 adev->gfx.config.pa_sc_tile_steering_override = in gfx_v10_0_constants_init()
5037 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v10_0_init_csb()
5042 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v10_0_init_csb()
5044 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v10_0_init_csb()
5045 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v10_0_init_csb()
5048 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v10_0_init_csb()
5050 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v10_0_init_csb()
5051 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v10_0_init_csb()
5124 if (!adev->gfx.rlc_fw) in gfx_v10_0_rlc_load_microcode()
5127 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v10_0_rlc_load_microcode()
5130 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v10_0_rlc_load_microcode()
5141 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v10_0_rlc_load_microcode()
5169 adev->gfx.rlc.funcs->stop(adev); in gfx_v10_0_rlc_resume()
5193 adev->gfx.rlc.funcs->start(adev); in gfx_v10_0_rlc_resume()
5218 &adev->gfx.rlc.rlc_toc_bo, in gfx_v10_0_parse_rlc_toc()
5219 &adev->gfx.rlc.rlc_toc_gpu_addr, in gfx_v10_0_parse_rlc_toc()
5220 (void **)&adev->gfx.rlc.rlc_toc_buf); in gfx_v10_0_parse_rlc_toc()
5227 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); in gfx_v10_0_parse_rlc_toc()
5229 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; in gfx_v10_0_parse_rlc_toc()
5280 &adev->gfx.rlc.rlc_autoload_bo, in gfx_v10_0_rlc_backdoor_autoload_buffer_init()
5281 &adev->gfx.rlc.rlc_autoload_gpu_addr, in gfx_v10_0_rlc_backdoor_autoload_buffer_init()
5282 (void **)&adev->gfx.rlc.rlc_autoload_ptr); in gfx_v10_0_rlc_backdoor_autoload_buffer_init()
5293 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5294 &adev->gfx.rlc.rlc_toc_gpu_addr, in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5295 (void **)&adev->gfx.rlc.rlc_toc_buf); in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5296 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5297 &adev->gfx.rlc.rlc_autoload_gpu_addr, in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5298 (void **)&adev->gfx.rlc.rlc_autoload_ptr); in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5308 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; in gfx_v10_0_rlc_backdoor_autoload_copy_ucode()
5333 data = adev->gfx.rlc.rlc_toc_buf; in gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode()
5350 adev->gfx.pfp_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5351 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5360 adev->gfx.ce_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5361 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5370 adev->gfx.me_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5371 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5380 adev->gfx.rlc_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5381 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5390 adev->gfx.mec_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5391 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5447 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; in gfx_v10_0_rlc_backdoor_autoload_enable()
5496 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v10_0_rlc_backdoor_autoload_config_me_cache()
5533 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v10_0_rlc_backdoor_autoload_config_ce_cache()
5570 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache()
5607 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
5684 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); in gfx_v10_0_cp_gfx_enable()
5699 adev->gfx.pfp_fw->data; in gfx_v10_0_cp_gfx_load_pfp_microcode()
5703 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v10_0_cp_gfx_load_pfp_microcode()
5709 &adev->gfx.pfp.pfp_fw_obj, in gfx_v10_0_cp_gfx_load_pfp_microcode()
5710 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v10_0_cp_gfx_load_pfp_microcode()
5711 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v10_0_cp_gfx_load_pfp_microcode()
5718 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); in gfx_v10_0_cp_gfx_load_pfp_microcode()
5720 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); in gfx_v10_0_cp_gfx_load_pfp_microcode()
5721 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); in gfx_v10_0_cp_gfx_load_pfp_microcode()
5752 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); in gfx_v10_0_cp_gfx_load_pfp_microcode()
5754 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); in gfx_v10_0_cp_gfx_load_pfp_microcode()
5762 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v10_0_cp_gfx_load_pfp_microcode()
5777 adev->gfx.ce_fw->data; in gfx_v10_0_cp_gfx_load_ce_microcode()
5781 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + in gfx_v10_0_cp_gfx_load_ce_microcode()
5787 &adev->gfx.ce.ce_fw_obj, in gfx_v10_0_cp_gfx_load_ce_microcode()
5788 &adev->gfx.ce.ce_fw_gpu_addr, in gfx_v10_0_cp_gfx_load_ce_microcode()
5789 (void **)&adev->gfx.ce.ce_fw_ptr); in gfx_v10_0_cp_gfx_load_ce_microcode()
5796 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); in gfx_v10_0_cp_gfx_load_ce_microcode()
5798 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); in gfx_v10_0_cp_gfx_load_ce_microcode()
5799 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); in gfx_v10_0_cp_gfx_load_ce_microcode()
5829 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); in gfx_v10_0_cp_gfx_load_ce_microcode()
5831 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); in gfx_v10_0_cp_gfx_load_ce_microcode()
5839 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v10_0_cp_gfx_load_ce_microcode()
5854 adev->gfx.me_fw->data; in gfx_v10_0_cp_gfx_load_me_microcode()
5858 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v10_0_cp_gfx_load_me_microcode()
5864 &adev->gfx.me.me_fw_obj, in gfx_v10_0_cp_gfx_load_me_microcode()
5865 &adev->gfx.me.me_fw_gpu_addr, in gfx_v10_0_cp_gfx_load_me_microcode()
5866 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v10_0_cp_gfx_load_me_microcode()
5873 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); in gfx_v10_0_cp_gfx_load_me_microcode()
5875 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); in gfx_v10_0_cp_gfx_load_me_microcode()
5876 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); in gfx_v10_0_cp_gfx_load_me_microcode()
5906 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); in gfx_v10_0_cp_gfx_load_me_microcode()
5908 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); in gfx_v10_0_cp_gfx_load_me_microcode()
5916 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); in gfx_v10_0_cp_gfx_load_me_microcode()
5925 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v10_0_cp_gfx_load_microcode()
5961 adev->gfx.config.max_hw_contexts - 1); in gfx_v10_0_cp_gfx_start()
5966 ring = &adev->gfx.gfx_ring[0]; in gfx_v10_0_cp_gfx_start()
5998 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); in gfx_v10_0_cp_gfx_start()
6014 if (adev->gfx.num_gfx_rings > 1) { in gfx_v10_0_cp_gfx_start()
6015 /* maximum supported gfx ring is 2 */ in gfx_v10_0_cp_gfx_start()
6016 ring = &adev->gfx.gfx_ring[1]; in gfx_v10_0_cp_gfx_start()
6100 /* Init gfx ring 0 for pipe 0 */ in gfx_v10_0_cp_gfx_resume()
6105 ring = &adev->gfx.gfx_ring[0]; in gfx_v10_0_cp_gfx_resume()
6143 /* Init gfx ring 1 for pipe 1 */ in gfx_v10_0_cp_gfx_resume()
6144 if (adev->gfx.num_gfx_rings > 1) { in gfx_v10_0_cp_gfx_resume()
6147 /* maximum supported gfx ring is 2 */ in gfx_v10_0_cp_gfx_resume()
6148 ring = &adev->gfx.gfx_ring[1]; in gfx_v10_0_cp_gfx_resume()
6228 adev->gfx.kiq[0].ring.sched.ready = false; in gfx_v10_0_cp_compute_enable()
6241 if (!adev->gfx.mec_fw) in gfx_v10_0_cp_compute_load_microcode()
6246 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v10_0_cp_compute_load_microcode()
6250 (adev->gfx.mec_fw->data + in gfx_v10_0_cp_compute_load_microcode()
6281 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & in gfx_v10_0_cp_compute_load_microcode()
6284 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v10_0_cp_compute_load_microcode()
6293 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v10_0_cp_compute_load_microcode()
6362 /* set up gfx hqd wptr */ in gfx_v10_0_gfx_mqd_init()
6382 /* set up gfx queue priority */ in gfx_v10_0_gfx_mqd_init()
6390 /* set up gfx hqd base. this is similar as CP_RB_BASE */ in gfx_v10_0_gfx_mqd_init()
6441 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; in gfx_v10_0_gfx_init_queue()
6450 * if there are 2 gfx rings, set the lower doorbell in gfx_v10_0_gfx_init_queue()
6459 if (adev->gfx.me.mqd_backup[mqd_idx]) in gfx_v10_0_gfx_init_queue()
6460 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v10_0_gfx_init_queue()
6463 if (adev->gfx.me.mqd_backup[mqd_idx]) in gfx_v10_0_gfx_init_queue()
6464 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v10_0_gfx_init_queue()
6479 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v10_0_cp_async_gfx_ring_resume()
6480 ring = &adev->gfx.gfx_ring[i]; in gfx_v10_0_cp_async_gfx_ring_resume()
6737 if (adev->gfx.kiq[0].mqd_backup) in gfx_v10_0_kiq_init_queue()
6738 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); in gfx_v10_0_kiq_init_queue()
6760 if (adev->gfx.kiq[0].mqd_backup) in gfx_v10_0_kiq_init_queue()
6761 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); in gfx_v10_0_kiq_init_queue()
6771 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v10_0_kcq_init_queue()
6781 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v10_0_kcq_init_queue()
6782 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v10_0_kcq_init_queue()
6785 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v10_0_kcq_init_queue()
6786 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v10_0_kcq_init_queue()
6801 ring = &adev->gfx.kiq[0].ring; in gfx_v10_0_kiq_resume()
6827 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_kcq_resume()
6828 ring = &adev->gfx.compute_ring[i]; in gfx_v10_0_kcq_resume()
6889 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v10_0_cp_resume()
6890 ring = &adev->gfx.gfx_ring[i]; in gfx_v10_0_cp_resume()
6896 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_cp_resume()
6897 ring = &adev->gfx.compute_ring[i]; in gfx_v10_0_cp_resume()
7116 * For gfx 10, rlc firmware loading relies on smu firmware is in gfx_v10_0_hw_init()
7164 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v10_0_hw_fini()
7165 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v10_0_hw_fini()
7180 * It causes GFX hang when another Win guest is rendering. in gfx_v10_0_hw_fini()
7285 /* Disable GFX parsing/prefetching */ in gfx_v10_0_soft_reset()
7400 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; in gfx_v10_0_early_init()
7408 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; in gfx_v10_0_early_init()
7418 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; in gfx_v10_0_early_init()
7424 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v10_0_early_init()
7445 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v10_0_late_init()
7449 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v10_0_late_init()
7556 /* MGLS is a global flag to control all MGLS in GFX */ in gfx_v10_0_update_medium_grain_clock_gating()
7862 /* === CGCG /CGLS for GFX 3D Only === */ in gfx_v10_0_update_gfx_clock_gating()
7876 /* === CGCG /CGLS for GFX 3D Only === */ in gfx_v10_0_update_gfx_clock_gating()
8310 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { in gfx_v10_0_ring_emit_ib_gfx()
8485 if (ring->adev->gfx.mcbp) in gfx_v10_0_ring_emit_cntxcntl()
8495 /* set load_per_context_state & load_gfx_sh_regs for GFX */ in gfx_v10_0_ring_emit_cntxcntl()
8546 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v10_0_ring_preempt_ib()
8601 gfx[0].gfx_meta_data) + in gfx_v10_0_ring_emit_ce_meta()
8639 gfx[0].gfx_meta_data) + in gfx_v10_0_ring_emit_de_meta()
8647 gfx[0].gds_backup) + in gfx_v10_0_ring_emit_de_meta()
8743 fw_version_ok = adev->gfx.cp_fw_write_wait; in gfx_v10_0_ring_emit_reg_write_reg_wait()
8934 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v10_0_eop_irq()
8936 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); in gfx_v10_0_eop_irq()
8940 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_eop_irq()
8941 ring = &adev->gfx.compute_ring[i]; in gfx_v10_0_eop_irq()
9009 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v10_0_handle_priv_fault()
9010 ring = &adev->gfx.gfx_ring[i]; in gfx_v10_0_handle_priv_fault()
9011 /* we only enabled 1 gfx queue per pipe for now */ in gfx_v10_0_handle_priv_fault()
9018 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_handle_priv_fault()
9019 ring = &adev->gfx.compute_ring[i]; in gfx_v10_0_handle_priv_fault()
9054 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); in gfx_v10_0_kiq_set_interrupt_state()
9098 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); in gfx_v10_0_kiq_irq()
9275 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; in gfx_v10_0_set_ring_funcs()
9277 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v10_0_set_ring_funcs()
9278 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; in gfx_v10_0_set_ring_funcs()
9280 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v10_0_set_ring_funcs()
9281 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; in gfx_v10_0_set_ring_funcs()
9306 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v10_0_set_irq_funcs()
9307 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; in gfx_v10_0_set_irq_funcs()
9309 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; in gfx_v10_0_set_irq_funcs()
9310 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; in gfx_v10_0_set_irq_funcs()
9312 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v10_0_set_irq_funcs()
9313 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; in gfx_v10_0_set_irq_funcs()
9315 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v10_0_set_irq_funcs()
9316 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; in gfx_v10_0_set_irq_funcs()
9333 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; in gfx_v10_0_set_rlc_funcs()
9337 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; in gfx_v10_0_set_rlc_funcs()
9346 unsigned int total_cu = adev->gfx.config.max_cu_per_sh * in gfx_v10_0_set_gds_init()
9347 adev->gfx.config.max_sh_per_se * in gfx_v10_0_set_gds_init()
9348 adev->gfx.config.max_shader_engines; in gfx_v10_0_set_gds_init()
9358 /* set gfx eng mqd */ in gfx_v10_0_set_mqd_funcs()
9387 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); in gfx_v10_0_get_wgp_active_bitmap_per_sh()
9435 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v10_0_get_cu_info()
9436 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_get_cu_info()
9437 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_get_cu_info()
9454 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v10_0_get_cu_info()
9456 if (counter < adev->gfx.config.max_cu_per_sh) in gfx_v10_0_get_cu_info()
9490 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v10_3_get_disabled_sa()
9491 adev->gfx.config.max_shader_engines); in gfx_v10_3_get_disabled_sa()
9505 max_sa_per_se = adev->gfx.config.max_sh_per_se; in gfx_v10_3_program_pbb_mode()
9507 max_shader_engines = adev->gfx.config.max_shader_engines; in gfx_v10_3_program_pbb_mode()