Lines Matching full:gfx
927 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
928 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v8_0_free_microcode()
929 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
930 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
931 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v8_0_free_microcode()
934 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v8_0_free_microcode()
936 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
986 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v8_0_init_microcode()
989 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v8_0_init_microcode()
993 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v8_0_init_microcode()
997 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v8_0_init_microcode()
998 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
999 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1003 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); in gfx_v8_0_init_microcode()
1006 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); in gfx_v8_0_init_microcode()
1010 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); in gfx_v8_0_init_microcode()
1014 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v8_0_init_microcode()
1015 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1017 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1021 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); in gfx_v8_0_init_microcode()
1024 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); in gfx_v8_0_init_microcode()
1028 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); in gfx_v8_0_init_microcode()
1032 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v8_0_init_microcode()
1033 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1034 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1040 if (adev->gfx.ce_feature_version >= 46 && in gfx_v8_0_init_microcode()
1041 adev->gfx.pfp_feature_version >= 46) { in gfx_v8_0_init_microcode()
1048 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); in gfx_v8_0_init_microcode()
1051 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v8_0_init_microcode()
1052 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1053 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1055 adev->gfx.rlc.save_and_restore_offset = in gfx_v8_0_init_microcode()
1057 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v8_0_init_microcode()
1059 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v8_0_init_microcode()
1061 adev->gfx.rlc.reg_restore_list_size = in gfx_v8_0_init_microcode()
1063 adev->gfx.rlc.reg_list_format_start = in gfx_v8_0_init_microcode()
1065 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v8_0_init_microcode()
1067 adev->gfx.rlc.starting_offsets_start = in gfx_v8_0_init_microcode()
1069 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v8_0_init_microcode()
1071 adev->gfx.rlc.reg_list_size_bytes = in gfx_v8_0_init_microcode()
1074 adev->gfx.rlc.register_list_format = in gfx_v8_0_init_microcode()
1075 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + in gfx_v8_0_init_microcode()
1076 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); in gfx_v8_0_init_microcode()
1078 if (!adev->gfx.rlc.register_list_format) { in gfx_v8_0_init_microcode()
1085 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) in gfx_v8_0_init_microcode()
1086 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); in gfx_v8_0_init_microcode()
1088 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v8_0_init_microcode()
1092 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) in gfx_v8_0_init_microcode()
1093 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); in gfx_v8_0_init_microcode()
1097 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); in gfx_v8_0_init_microcode()
1100 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); in gfx_v8_0_init_microcode()
1104 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); in gfx_v8_0_init_microcode()
1108 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v8_0_init_microcode()
1109 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1110 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1116 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); in gfx_v8_0_init_microcode()
1119 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); in gfx_v8_0_init_microcode()
1123 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); in gfx_v8_0_init_microcode()
1127 adev->gfx.mec2_fw->data; in gfx_v8_0_init_microcode()
1128 adev->gfx.mec2_fw_version = in gfx_v8_0_init_microcode()
1130 adev->gfx.mec2_feature_version = in gfx_v8_0_init_microcode()
1134 adev->gfx.mec2_fw = NULL; in gfx_v8_0_init_microcode()
1140 info->fw = adev->gfx.pfp_fw; in gfx_v8_0_init_microcode()
1147 info->fw = adev->gfx.me_fw; in gfx_v8_0_init_microcode()
1154 info->fw = adev->gfx.ce_fw; in gfx_v8_0_init_microcode()
1161 info->fw = adev->gfx.rlc_fw; in gfx_v8_0_init_microcode()
1168 info->fw = adev->gfx.mec_fw; in gfx_v8_0_init_microcode()
1174 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v8_0_init_microcode()
1181 info->fw = adev->gfx.mec_fw; in gfx_v8_0_init_microcode()
1186 if (adev->gfx.mec2_fw) { in gfx_v8_0_init_microcode()
1189 info->fw = adev->gfx.mec2_fw; in gfx_v8_0_init_microcode()
1200 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v8_0_init_microcode()
1201 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v8_0_init_microcode()
1202 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v8_0_init_microcode()
1203 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v8_0_init_microcode()
1204 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v8_0_init_microcode()
1205 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v8_0_init_microcode()
1217 if (adev->gfx.rlc.cs_data == NULL) in gfx_v8_0_get_csb_buffer()
1229 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v8_0_get_csb_buffer()
1247 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); in gfx_v8_0_get_csb_buffer()
1248 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v8_0_get_csb_buffer()
1270 adev->gfx.rlc.cs_data = vi_cs_data; in gfx_v8_0_rlc_init()
1272 cs_data = adev->gfx.rlc.cs_data; in gfx_v8_0_rlc_init()
1283 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ in gfx_v8_0_rlc_init()
1290 if (adev->gfx.rlc.funcs->update_spm_vmid) in gfx_v8_0_rlc_init()
1291 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); in gfx_v8_0_rlc_init()
1298 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v8_0_mec_fini()
1307 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v8_0_mec_init()
1312 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE; in gfx_v8_0_mec_init()
1317 &adev->gfx.mec.hpd_eop_obj, in gfx_v8_0_mec_init()
1318 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v8_0_mec_init()
1327 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_init()
1328 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_init()
1490 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; in gfx_v8_0_do_edc_gpr_workarounds()
1662 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1663 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1664 adev->gfx.config.max_cu_per_sh = 6; in gfx_v8_0_gpu_early_init()
1665 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1666 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1667 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1668 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1669 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1670 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1672 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1673 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1674 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1675 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1679 adev->gfx.config.max_shader_engines = 4; in gfx_v8_0_gpu_early_init()
1680 adev->gfx.config.max_tile_pipes = 16; in gfx_v8_0_gpu_early_init()
1681 adev->gfx.config.max_cu_per_sh = 16; in gfx_v8_0_gpu_early_init()
1682 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1683 adev->gfx.config.max_backends_per_se = 4; in gfx_v8_0_gpu_early_init()
1684 adev->gfx.config.max_texture_channel_caches = 16; in gfx_v8_0_gpu_early_init()
1685 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1686 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1687 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1689 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1690 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1691 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1692 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1700 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1701 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1702 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1704 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1705 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1706 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1707 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1715 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1716 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1717 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1719 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1720 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1721 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1722 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1726 adev->gfx.config.max_shader_engines = 4; in gfx_v8_0_gpu_early_init()
1727 adev->gfx.config.max_tile_pipes = 8; in gfx_v8_0_gpu_early_init()
1728 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()
1729 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1730 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1731 adev->gfx.config.max_texture_channel_caches = 8; in gfx_v8_0_gpu_early_init()
1732 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1733 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1734 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1736 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1737 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1738 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1739 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1743 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1744 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1745 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1746 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1747 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()
1748 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1749 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1750 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1751 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1753 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1754 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1755 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1756 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1760 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1761 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1762 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1763 adev->gfx.config.max_backends_per_se = 1; in gfx_v8_0_gpu_early_init()
1764 adev->gfx.config.max_cu_per_sh = 3; in gfx_v8_0_gpu_early_init()
1765 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1766 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1767 adev->gfx.config.max_gs_threads = 16; in gfx_v8_0_gpu_early_init()
1768 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1770 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1771 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1772 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1773 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1777 adev->gfx.config.max_shader_engines = 2; in gfx_v8_0_gpu_early_init()
1778 adev->gfx.config.max_tile_pipes = 4; in gfx_v8_0_gpu_early_init()
1779 adev->gfx.config.max_cu_per_sh = 2; in gfx_v8_0_gpu_early_init()
1780 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1781 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1782 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v8_0_gpu_early_init()
1783 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1784 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1785 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1787 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1788 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1789 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1790 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1795 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v8_0_gpu_early_init()
1796 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; in gfx_v8_0_gpu_early_init()
1798 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v8_0_gpu_early_init()
1800 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v8_0_gpu_early_init()
1803 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v8_0_gpu_early_init()
1804 adev->gfx.config.mem_max_burst_length_bytes = 256; in gfx_v8_0_gpu_early_init()
1828 adev->gfx.config.mem_row_size_in_kb = 2; in gfx_v8_0_gpu_early_init()
1830 adev->gfx.config.mem_row_size_in_kb = 1; in gfx_v8_0_gpu_early_init()
1833 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in gfx_v8_0_gpu_early_init()
1834 if (adev->gfx.config.mem_row_size_in_kb > 4) in gfx_v8_0_gpu_early_init()
1835 adev->gfx.config.mem_row_size_in_kb = 4; in gfx_v8_0_gpu_early_init()
1838 adev->gfx.config.shader_engine_tile_size = 32; in gfx_v8_0_gpu_early_init()
1839 adev->gfx.config.num_gpus = 1; in gfx_v8_0_gpu_early_init()
1840 adev->gfx.config.multi_gpu_tile_size = 64; in gfx_v8_0_gpu_early_init()
1843 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v8_0_gpu_early_init()
1855 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v8_0_gpu_early_init()
1865 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v8_0_compute_ring_init()
1868 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v8_0_compute_ring_init()
1878 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v8_0_compute_ring_init()
1883 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v8_0_compute_ring_init()
1889 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v8_0_compute_ring_init()
1915 adev->gfx.mec.num_mec = 2; in gfx_v8_0_sw_init()
1920 adev->gfx.mec.num_mec = 1; in gfx_v8_0_sw_init()
1924 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v8_0_sw_init()
1925 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v8_0_sw_init()
1928 …q_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq); in gfx_v8_0_sw_init()
1934 &adev->gfx.priv_reg_irq); in gfx_v8_0_sw_init()
1940 &adev->gfx.priv_inst_irq); in gfx_v8_0_sw_init()
1946 &adev->gfx.cp_ecc_error_irq); in gfx_v8_0_sw_init()
1952 &adev->gfx.sq_irq); in gfx_v8_0_sw_init()
1958 INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func); in gfx_v8_0_sw_init()
1960 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v8_0_sw_init()
1964 DRM_ERROR("Failed to load gfx firmware!\n"); in gfx_v8_0_sw_init()
1968 r = adev->gfx.rlc.funcs->init(adev); in gfx_v8_0_sw_init()
1980 /* set up the gfx ring */ in gfx_v8_0_sw_init()
1981 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v8_0_sw_init()
1982 ring = &adev->gfx.gfx_ring[i]; in gfx_v8_0_sw_init()
1984 sprintf(ring->name, "gfx"); in gfx_v8_0_sw_init()
1985 /* no gfx doorbells on iceland */ in gfx_v8_0_sw_init()
1991 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, in gfx_v8_0_sw_init()
2001 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v8_0_sw_init()
2002 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v8_0_sw_init()
2003 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v8_0_sw_init()
2025 kiq = &adev->gfx.kiq[0]; in gfx_v8_0_sw_init()
2035 adev->gfx.ce_ram_size = 0x8000; in gfx_v8_0_sw_init()
2049 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_sw_fini()
2050 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v8_0_sw_fini()
2051 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_sw_fini()
2052 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v8_0_sw_fini()
2055 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); in gfx_v8_0_sw_fini()
2060 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v8_0_sw_fini()
2061 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_sw_fini()
2062 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v8_0_sw_fini()
2065 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v8_0_sw_fini()
2066 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v8_0_sw_fini()
2067 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v8_0_sw_fini()
2077 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v8_0_tiling_mode_table_init()
2078 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in gfx_v8_0_tiling_mode_table_init()
2081 modearray = adev->gfx.config.tile_mode_array; in gfx_v8_0_tiling_mode_table_init()
2082 mod2array = adev->gfx.config.macrotile_mode_array; in gfx_v8_0_tiling_mode_table_init()
3436 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v8_0_get_rb_active_bitmap()
3437 adev->gfx.config.max_sh_per_se); in gfx_v8_0_get_rb_active_bitmap()
3488 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v8_0_write_harvested_raster_configs()
3489 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v8_0_write_harvested_raster_configs()
3598 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v8_0_setup_rb()
3599 adev->gfx.config.max_sh_per_se; in gfx_v8_0_setup_rb()
3603 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_setup_rb()
3604 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3607 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v8_0_setup_rb()
3613 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v8_0_setup_rb()
3614 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v8_0_setup_rb()
3616 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v8_0_setup_rb()
3617 adev->gfx.config.max_shader_engines, 16); in gfx_v8_0_setup_rb()
3621 if (!adev->gfx.config.backend_enable_mask || in gfx_v8_0_setup_rb()
3622 adev->gfx.config.num_rbs >= num_rb_pipes) { in gfx_v8_0_setup_rb()
3627 adev->gfx.config.backend_enable_mask, in gfx_v8_0_setup_rb()
3632 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_setup_rb()
3633 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3635 adev->gfx.config.rb_config[i][j].rb_backend_disable = in gfx_v8_0_setup_rb()
3637 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = in gfx_v8_0_setup_rb()
3639 adev->gfx.config.rb_config[i][j].raster_config = in gfx_v8_0_setup_rb()
3641 adev->gfx.config.rb_config[i][j].raster_config_1 = in gfx_v8_0_setup_rb()
3706 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA in gfx_v8_0_init_gds_vmid()
3723 adev->gfx.config.double_offchip_lds_buf = 1; in gfx_v8_0_config_init()
3727 adev->gfx.config.double_offchip_lds_buf = 0; in gfx_v8_0_config_init()
3738 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_constants_init()
3739 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_constants_init()
3740 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); in gfx_v8_0_constants_init()
3795 (adev->gfx.config.sc_prim_fifo_size_frontend << in gfx_v8_0_constants_init()
3797 (adev->gfx.config.sc_prim_fifo_size_backend << in gfx_v8_0_constants_init()
3799 (adev->gfx.config.sc_hiz_tile_fifo_size << in gfx_v8_0_constants_init()
3801 (adev->gfx.config.sc_earlyz_tile_fifo_size << in gfx_v8_0_constants_init()
3821 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_wait_for_rlc_serdes()
3822 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_wait_for_rlc_serdes()
3868 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v8_0_init_csb()
3871 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v8_0_init_csb()
3873 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v8_0_init_csb()
3875 adev->gfx.rlc.clear_state_size); in gfx_v8_0_init_csb()
3938 kmemdup(adev->gfx.rlc.register_list_format, in gfx_v8_0_init_save_restore_list()
3939 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); in gfx_v8_0_init_save_restore_list()
3945 adev->gfx.rlc.reg_list_format_size_bytes >> 2, in gfx_v8_0_init_save_restore_list()
3957 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
3958 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]); in gfx_v8_0_init_save_restore_list()
3961 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start); in gfx_v8_0_init_save_restore_list()
3962 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
3965 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; in gfx_v8_0_init_save_restore_list()
3967 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size); in gfx_v8_0_init_save_restore_list()
3972 adev->gfx.rlc.starting_offsets_start); in gfx_v8_0_init_save_restore_list()
4037 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v8_0_init_pg()
4039 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); in gfx_v8_0_init_pg()
4086 adev->gfx.rlc.funcs->stop(adev); in gfx_v8_0_rlc_resume()
4087 adev->gfx.rlc.funcs->reset(adev); in gfx_v8_0_rlc_resume()
4089 adev->gfx.rlc.funcs->start(adev); in gfx_v8_0_rlc_resume()
4142 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_start()
4148 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v8_0_cp_gfx_start()
4184 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); in gfx_v8_0_cp_gfx_start()
4185 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v8_0_cp_gfx_start()
4206 /* no gfx doorbells on iceland */ in gfx_v8_0_set_cpg_door_bell()
4251 ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_resume()
4296 adev->gfx.kiq[0].ring.sched.ready = false; in gfx_v8_0_cp_compute_enable()
4318 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in gfx_v8_0_kiq_kcq_enable()
4323 if (!test_bit(i, adev->gfx.mec_bitmap[0].queue_bitmap)) in gfx_v8_0_kiq_kcq_enable()
4337 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8); in gfx_v8_0_kiq_kcq_enable()
4351 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kiq_kcq_enable()
4352 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kiq_kcq_enable()
4604 if (adev->gfx.kiq[0].mqd_backup) in gfx_v8_0_kiq_init_queue()
4605 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kiq_init_queue()
4628 if (adev->gfx.kiq[0].mqd_backup) in gfx_v8_0_kiq_init_queue()
4629 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kiq_init_queue()
4639 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v8_0_kcq_init_queue()
4651 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kcq_init_queue()
4652 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kcq_init_queue()
4655 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kcq_init_queue()
4656 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kcq_init_queue()
4679 ring = &adev->gfx.kiq[0].ring; in gfx_v8_0_kiq_resume()
4705 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_resume()
4706 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kcq_resume()
4737 /* collect all the ring_tests here, gfx, kiq, compute */ in gfx_v8_0_cp_test_all_rings()
4738 ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_test_all_rings()
4743 ring = &adev->gfx.kiq[0].ring; in gfx_v8_0_cp_test_all_rings()
4748 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_cp_test_all_rings()
4749 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_cp_test_all_rings()
4798 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v8_0_hw_init()
4810 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in gfx_v8_0_kcq_disable()
4812 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings); in gfx_v8_0_kcq_disable()
4816 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_disable()
4817 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kcq_disable()
4890 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v8_0_hw_fini()
4891 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v8_0_hw_fini()
4893 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v8_0_hw_fini()
4895 amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0); in gfx_v8_0_hw_fini()
4910 adev->gfx.rlc.funcs->stop(adev); in gfx_v8_0_hw_fini()
4980 adev->gfx.grbm_soft_reset = grbm_soft_reset; in gfx_v8_0_check_soft_reset()
4981 adev->gfx.srbm_soft_reset = srbm_soft_reset; in gfx_v8_0_check_soft_reset()
4984 adev->gfx.grbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
4985 adev->gfx.srbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
4995 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_pre_soft_reset()
4996 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_pre_soft_reset()
4999 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_pre_soft_reset()
5002 adev->gfx.rlc.funcs->stop(adev); in gfx_v8_0_pre_soft_reset()
5006 /* Disable GFX parsing/prefetching */ in gfx_v8_0_pre_soft_reset()
5015 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_pre_soft_reset()
5016 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_pre_soft_reset()
5037 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_soft_reset()
5038 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_soft_reset()
5041 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_soft_reset()
5042 srbm_soft_reset = adev->gfx.srbm_soft_reset; in gfx_v8_0_soft_reset()
5098 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_post_soft_reset()
5099 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_post_soft_reset()
5102 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_post_soft_reset()
5110 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_post_soft_reset()
5111 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_post_soft_reset()
5129 adev->gfx.rlc.funcs->start(adev); in gfx_v8_0_post_soft_reset()
5146 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v8_0_get_gpu_clock_counter()
5150 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v8_0_get_gpu_clock_counter()
5265 adev->gfx.xcc_mask = 1; in gfx_v8_0_early_init()
5266 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; in gfx_v8_0_early_init()
5267 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v8_0_early_init()
5269 adev->gfx.funcs = &gfx_v8_0_gfx_funcs; in gfx_v8_0_early_init()
5283 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v8_0_late_init()
5287 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v8_0_late_init()
5296 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v8_0_late_init()
5302 r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0); in gfx_v8_0_late_init()
5348 /* Read any GFX register to wake up GFX. */ in cz_enable_gfx_pipeline_power_gating()
5774 /* disable cntx_empty_int_enable & GFX Idle interrupt */ in gfx_v8_0_update_coarse_grain_clock_gating()
5784 /* read gfx register to wake up cgcg */ in gfx_v8_0_update_coarse_grain_clock_gating()
6311 /* set load_per_context_state & load_gfx_sh_regs for GFX */ in gfx_v8_ring_emit_cntxcntl()
6615 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v8_0_eop_irq()
6619 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_eop_irq()
6620 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_eop_irq()
6645 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); in gfx_v8_0_fault()
6649 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_fault()
6650 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_fault()
6759 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.sq_work.work); in gfx_v8_0_sq_irq_work_func()
6776 if (work_pending(&adev->gfx.sq_work.work)) { in gfx_v8_0_sq_irq()
6779 adev->gfx.sq_work.ih_data = ih_data; in gfx_v8_0_sq_irq()
6780 schedule_work(&adev->gfx.sq_work.work); in gfx_v8_0_sq_irq()
6855 * number of gfx waves. Setting 5 bit will make sure gfx only gets in gfx_v8_0_emit_wave_limit()
6866 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v8_0_emit_wave_limit()
7004 adev->gfx.kiq[0].ring.funcs = &gfx_v8_0_ring_funcs_kiq; in gfx_v8_0_set_ring_funcs()
7006 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_set_ring_funcs()
7007 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx; in gfx_v8_0_set_ring_funcs()
7009 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_set_ring_funcs()
7010 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute; in gfx_v8_0_set_ring_funcs()
7040 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v8_0_set_irq_funcs()
7041 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; in gfx_v8_0_set_irq_funcs()
7043 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7044 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; in gfx_v8_0_set_irq_funcs()
7046 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7047 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs; in gfx_v8_0_set_irq_funcs()
7049 adev->gfx.cp_ecc_error_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7050 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs; in gfx_v8_0_set_irq_funcs()
7052 adev->gfx.sq_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7053 adev->gfx.sq_irq.funcs = &gfx_v8_0_sq_irq_funcs; in gfx_v8_0_set_irq_funcs()
7058 adev->gfx.rlc.funcs = &iceland_rlc_funcs; in gfx_v8_0_set_rlc_funcs()
7091 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v8_0_get_cu_active_bitmap()
7100 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v8_0_get_cu_info()
7109 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v8_0_get_cu_info()
7114 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_get_cu_info()
7115 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_get_cu_info()
7126 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v8_0_get_cu_info()