Lines Matching full:gfx
46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
893 adev->gfx.kiq[0].pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
1083 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
1084 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v9_0_free_microcode()
1085 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
1086 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v9_0_free_microcode()
1087 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v9_0_free_microcode()
1088 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v9_0_free_microcode()
1090 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_0_free_microcode()
1095 adev->gfx.me_fw_write_wait = false; in gfx_v9_0_check_fw_write_wait()
1096 adev->gfx.mec_fw_write_wait = false; in gfx_v9_0_check_fw_write_wait()
1099 ((adev->gfx.mec_fw_version < 0x000001a5) || in gfx_v9_0_check_fw_write_wait()
1100 (adev->gfx.mec_feature_version < 46) || in gfx_v9_0_check_fw_write_wait()
1101 (adev->gfx.pfp_fw_version < 0x000000b7) || in gfx_v9_0_check_fw_write_wait()
1102 (adev->gfx.pfp_feature_version < 46))) in gfx_v9_0_check_fw_write_wait()
1107 if ((adev->gfx.me_fw_version >= 0x0000009c) && in gfx_v9_0_check_fw_write_wait()
1108 (adev->gfx.me_feature_version >= 42) && in gfx_v9_0_check_fw_write_wait()
1109 (adev->gfx.pfp_fw_version >= 0x000000b1) && in gfx_v9_0_check_fw_write_wait()
1110 (adev->gfx.pfp_feature_version >= 42)) in gfx_v9_0_check_fw_write_wait()
1111 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1113 if ((adev->gfx.mec_fw_version >= 0x00000193) && in gfx_v9_0_check_fw_write_wait()
1114 (adev->gfx.mec_feature_version >= 42)) in gfx_v9_0_check_fw_write_wait()
1115 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1118 if ((adev->gfx.me_fw_version >= 0x0000009c) && in gfx_v9_0_check_fw_write_wait()
1119 (adev->gfx.me_feature_version >= 44) && in gfx_v9_0_check_fw_write_wait()
1120 (adev->gfx.pfp_fw_version >= 0x000000b2) && in gfx_v9_0_check_fw_write_wait()
1121 (adev->gfx.pfp_feature_version >= 44)) in gfx_v9_0_check_fw_write_wait()
1122 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1124 if ((adev->gfx.mec_fw_version >= 0x00000196) && in gfx_v9_0_check_fw_write_wait()
1125 (adev->gfx.mec_feature_version >= 44)) in gfx_v9_0_check_fw_write_wait()
1126 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1129 if ((adev->gfx.me_fw_version >= 0x0000009c) && in gfx_v9_0_check_fw_write_wait()
1130 (adev->gfx.me_feature_version >= 44) && in gfx_v9_0_check_fw_write_wait()
1131 (adev->gfx.pfp_fw_version >= 0x000000b2) && in gfx_v9_0_check_fw_write_wait()
1132 (adev->gfx.pfp_feature_version >= 44)) in gfx_v9_0_check_fw_write_wait()
1133 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1135 if ((adev->gfx.mec_fw_version >= 0x00000197) && in gfx_v9_0_check_fw_write_wait()
1136 (adev->gfx.mec_feature_version >= 44)) in gfx_v9_0_check_fw_write_wait()
1137 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1141 if ((adev->gfx.me_fw_version >= 0x0000009c) && in gfx_v9_0_check_fw_write_wait()
1142 (adev->gfx.me_feature_version >= 42) && in gfx_v9_0_check_fw_write_wait()
1143 (adev->gfx.pfp_fw_version >= 0x000000b1) && in gfx_v9_0_check_fw_write_wait()
1144 (adev->gfx.pfp_feature_version >= 42)) in gfx_v9_0_check_fw_write_wait()
1145 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1147 if ((adev->gfx.mec_fw_version >= 0x00000192) && in gfx_v9_0_check_fw_write_wait()
1148 (adev->gfx.mec_feature_version >= 42)) in gfx_v9_0_check_fw_write_wait()
1149 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1152 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1153 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1206 (adev->gfx.me_fw_version >= 0x000000a5) && in check_if_enlarge_doorbell_range()
1207 (adev->gfx.me_feature_version >= 52)) in check_if_enlarge_doorbell_range()
1228 adev->gfx.rlc_fw_version < 531) || in gfx_v9_0_check_if_need_gfxoff()
1229 (adev->gfx.rlc_feature_version < 1) || in gfx_v9_0_check_if_need_gfxoff()
1230 !adev->gfx.rlc.is_rlc_v2_1)) in gfx_v9_0_check_if_need_gfxoff()
1256 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v9_0_init_cp_gfx_microcode()
1262 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); in gfx_v9_0_init_cp_gfx_microcode()
1268 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); in gfx_v9_0_init_cp_gfx_microcode()
1275 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v9_0_init_cp_gfx_microcode()
1276 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v9_0_init_cp_gfx_microcode()
1277 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v9_0_init_cp_gfx_microcode()
1312 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); in gfx_v9_0_init_rlc_microcode()
1315 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v9_0_init_rlc_microcode()
1322 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v9_0_init_rlc_microcode()
1348 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); in gfx_v9_0_init_cp_compute_microcode()
1361 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); in gfx_v9_0_init_cp_compute_microcode()
1367 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v9_0_init_cp_compute_microcode()
1370 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; in gfx_v9_0_init_cp_compute_microcode()
1371 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; in gfx_v9_0_init_cp_compute_microcode()
1379 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v9_0_init_cp_compute_microcode()
1392 if (adev->gfx.num_gfx_rings) { in gfx_v9_0_init_microcode()
1444 if (adev->gfx.rlc.cs_data == NULL) in gfx_v9_0_get_csb_buffer()
1456 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v9_0_get_csb_buffer()
1480 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v9_0_init_always_on_cu_mask()
1494 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_init_always_on_cu_mask()
1495 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_init_always_on_cu_mask()
1501 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v9_0_init_always_on_cu_mask()
1637 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v9_0_init_rlcg_reg_access_ctrl()
1645 adev->gfx.rlc.rlcg_reg_access_supported = true; in gfx_v9_0_init_rlcg_reg_access_ctrl()
1653 adev->gfx.rlc.cs_data = gfx9_cs_data; in gfx_v9_0_rlc_init()
1655 cs_data = adev->gfx.rlc.cs_data; in gfx_v9_0_rlc_init()
1666 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ in gfx_v9_0_rlc_init()
1677 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v9_0_mec_fini()
1678 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v9_0_mec_fini()
1692 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v9_0_mec_init()
1696 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; in gfx_v9_0_mec_init()
1701 &adev->gfx.mec.hpd_eop_obj, in gfx_v9_0_mec_init()
1702 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v9_0_mec_init()
1712 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v9_0_mec_init()
1713 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v9_0_mec_init()
1716 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_0_mec_init()
1719 (adev->gfx.mec_fw->data + in gfx_v9_0_mec_init()
1725 &adev->gfx.mec.mec_fw_obj, in gfx_v9_0_mec_init()
1726 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v9_0_mec_init()
1736 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v9_0_mec_init()
1737 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v9_0_mec_init()
1841 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1842 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1843 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1844 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
1845 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1849 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1850 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1851 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1852 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
1853 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1855 DRM_INFO("fix gfx.config for vega12\n"); in gfx_v9_0_gpu_early_init()
1858 adev->gfx.ras = &gfx_v9_0_ras; in gfx_v9_0_gpu_early_init()
1859 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1860 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1861 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1862 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
1863 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1874 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1875 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1876 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1877 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
1878 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1885 adev->gfx.ras = &gfx_v9_4_ras; in gfx_v9_0_gpu_early_init()
1886 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1887 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1888 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1889 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
1890 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1896 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1897 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1898 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1899 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; in gfx_v9_0_gpu_early_init()
1900 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1906 adev->gfx.ras = &gfx_v9_4_2_ras; in gfx_v9_0_gpu_early_init()
1907 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1908 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1909 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1910 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
1911 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1925 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v9_0_gpu_early_init()
1927 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v9_0_gpu_early_init()
1929 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1933 adev->gfx.config.max_tile_pipes = in gfx_v9_0_gpu_early_init()
1934 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v9_0_gpu_early_init()
1936 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << in gfx_v9_0_gpu_early_init()
1938 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1941 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v9_0_gpu_early_init()
1943 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1946 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v9_0_gpu_early_init()
1948 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1951 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v9_0_gpu_early_init()
1953 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1956 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v9_0_gpu_early_init()
1958 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1969 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v9_0_compute_ring_init()
1972 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v9_0_compute_ring_init()
1982 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v9_0_compute_ring_init()
1988 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v9_0_compute_ring_init()
1993 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v9_0_compute_ring_init()
2014 adev->gfx.mec.num_mec = 2; in gfx_v9_0_sw_init()
2017 adev->gfx.mec.num_mec = 1; in gfx_v9_0_sw_init()
2021 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v9_0_sw_init()
2022 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v9_0_sw_init()
2025 …_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); in gfx_v9_0_sw_init()
2031 &adev->gfx.priv_reg_irq); in gfx_v9_0_sw_init()
2037 &adev->gfx.priv_inst_irq); in gfx_v9_0_sw_init()
2043 &adev->gfx.cp_ecc_error_irq); in gfx_v9_0_sw_init()
2049 &adev->gfx.cp_ecc_error_irq); in gfx_v9_0_sw_init()
2053 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v9_0_sw_init()
2055 if (adev->gfx.rlc.funcs) { in gfx_v9_0_sw_init()
2056 if (adev->gfx.rlc.funcs->init) { in gfx_v9_0_sw_init()
2057 r = adev->gfx.rlc.funcs->init(adev); in gfx_v9_0_sw_init()
2071 /* set up the gfx ring */ in gfx_v9_0_sw_init()
2072 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v9_0_sw_init()
2073 ring = &adev->gfx.gfx_ring[i]; in gfx_v9_0_sw_init()
2076 sprintf(ring->name, "gfx"); in gfx_v9_0_sw_init()
2085 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, in gfx_v9_0_sw_init()
2093 if (adev->gfx.num_gfx_rings) { in gfx_v9_0_sw_init()
2095 ring = &adev->gfx.sw_gfx_ring[i]; in gfx_v9_0_sw_init()
2103 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, in gfx_v9_0_sw_init()
2112 r = amdgpu_ring_mux_init(&adev->gfx.muxer, &adev->gfx.gfx_ring[0], in gfx_v9_0_sw_init()
2119 r = amdgpu_ring_mux_add_sw_ring(&adev->gfx.muxer, in gfx_v9_0_sw_init()
2120 &adev->gfx.sw_gfx_ring[i]); in gfx_v9_0_sw_init()
2130 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v9_0_sw_init()
2131 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v9_0_sw_init()
2132 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v9_0_sw_init()
2154 kiq = &adev->gfx.kiq[0]; in gfx_v9_0_sw_init()
2164 adev->gfx.ce_ram_size = 0x8000; in gfx_v9_0_sw_init()
2171 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); in gfx_v9_0_sw_init()
2184 if (adev->gfx.num_gfx_rings) { in gfx_v9_0_sw_fini()
2186 amdgpu_ring_fini(&adev->gfx.sw_gfx_ring[i]); in gfx_v9_0_sw_fini()
2187 amdgpu_ring_mux_fini(&adev->gfx.muxer); in gfx_v9_0_sw_fini()
2190 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v9_0_sw_fini()
2191 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v9_0_sw_fini()
2192 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_sw_fini()
2193 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v9_0_sw_fini()
2196 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); in gfx_v9_0_sw_fini()
2200 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v9_0_sw_fini()
2201 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v9_0_sw_fini()
2202 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v9_0_sw_fini()
2204 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v9_0_sw_fini()
2205 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v9_0_sw_fini()
2206 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v9_0_sw_fini()
2252 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v9_0_get_rb_active_bitmap()
2253 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_rb_active_bitmap()
2263 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v9_0_setup_rb()
2264 adev->gfx.config.max_sh_per_se; in gfx_v9_0_setup_rb()
2267 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_setup_rb()
2268 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_setup_rb()
2271 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v9_0_setup_rb()
2278 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v9_0_setup_rb()
2279 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v9_0_setup_rb()
2349 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA in gfx_v9_0_init_gds_vmid()
2387 if (adev->gfx.num_gfx_rings) in gfx_v9_0_constants_init()
2389 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); in gfx_v9_0_constants_init()
2390 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); in gfx_v9_0_constants_init()
2433 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_wait_for_rlc_serdes()
2434 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_wait_for_rlc_serdes()
2477 if(adev->gfx.num_gfx_rings) in gfx_v9_0_enable_gui_idle_interrupt()
2485 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v9_0_init_csb()
2488 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v9_0_init_csb()
2490 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v9_0_init_csb()
2492 adev->gfx.rlc.clear_state_size); in gfx_v9_0_init_csb()
2545 kmemdup(adev->gfx.rlc.register_list_format, in gfx_v9_1_init_rlc_save_restore_list()
2546 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); in gfx_v9_1_init_rlc_save_restore_list()
2553 adev->gfx.rlc.reg_list_format_direct_reg_list_length, in gfx_v9_1_init_rlc_save_restore_list()
2554 adev->gfx.rlc.reg_list_format_size_bytes >> 2, in gfx_v9_1_init_rlc_save_restore_list()
2569 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) in gfx_v9_1_init_rlc_save_restore_list()
2571 adev->gfx.rlc.register_restore[i]); in gfx_v9_1_init_rlc_save_restore_list()
2575 adev->gfx.rlc.reg_list_format_start); in gfx_v9_1_init_rlc_save_restore_list()
2578 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) in gfx_v9_1_init_rlc_save_restore_list()
2583 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { in gfx_v9_1_init_rlc_save_restore_list()
2605 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; in gfx_v9_1_init_rlc_save_restore_list()
2608 adev->gfx.rlc.reg_restore_list_size); in gfx_v9_1_init_rlc_save_restore_list()
2613 adev->gfx.rlc.starting_offsets_start); in gfx_v9_1_init_rlc_save_restore_list()
2776 /* read any GFX register to wake up GFX */ in gfx_v9_0_enable_gfx_pipeline_powergating()
2814 if (adev->gfx.rlc.is_rlc_v2_1) { in gfx_v9_0_init_pg()
2828 adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v9_0_init_pg()
2868 rlc_ucode_ver, adev->gfx.rlc_fw_version); in gfx_v9_0_rlc_start()
2886 if (!adev->gfx.rlc_fw) in gfx_v9_0_rlc_load_microcode()
2889 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v9_0_rlc_load_microcode()
2892 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v9_0_rlc_load_microcode()
2900 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v9_0_rlc_load_microcode()
2914 adev->gfx.rlc.funcs->stop(adev); in gfx_v9_0_rlc_resume()
2950 adev->gfx.rlc.funcs->start(adev); in gfx_v9_0_rlc_resume()
2974 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v9_0_cp_gfx_load_microcode()
2978 adev->gfx.pfp_fw->data; in gfx_v9_0_cp_gfx_load_microcode()
2980 adev->gfx.ce_fw->data; in gfx_v9_0_cp_gfx_load_microcode()
2982 adev->gfx.me_fw->data; in gfx_v9_0_cp_gfx_load_microcode()
2992 (adev->gfx.pfp_fw->data + in gfx_v9_0_cp_gfx_load_microcode()
2998 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
3002 (adev->gfx.ce_fw->data + in gfx_v9_0_cp_gfx_load_microcode()
3008 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
3012 (adev->gfx.me_fw->data + in gfx_v9_0_cp_gfx_load_microcode()
3018 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
3025 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_cp_gfx_start()
3031 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v9_0_cp_gfx_start()
3099 ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_cp_gfx_resume()
3161 adev->gfx.kiq[0].ring.sched.ready = false; in gfx_v9_0_cp_compute_enable()
3173 if (!adev->gfx.mec_fw) in gfx_v9_0_cp_compute_load_microcode()
3178 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_0_cp_compute_load_microcode()
3182 (adev->gfx.mec_fw->data + in gfx_v9_0_cp_compute_load_microcode()
3190 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); in gfx_v9_0_cp_compute_load_microcode()
3192 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v9_0_cp_compute_load_microcode()
3202 adev->gfx.mec_fw_version); in gfx_v9_0_cp_compute_load_microcode()
3534 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[0].mqd_backup; in gfx_v9_0_kiq_init_queue()
3537 if (adev->gfx.kiq[0].mqd_backup) in gfx_v9_0_kiq_init_queue()
3538 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kiq_init_queue()
3562 if (adev->gfx.kiq[0].mqd_backup) in gfx_v9_0_kiq_init_queue()
3563 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kiq_init_queue()
3573 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v9_0_kcq_init_queue()
3579 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; in gfx_v9_0_kcq_init_queue()
3592 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kcq_init_queue()
3593 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kcq_init_queue()
3596 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kcq_init_queue()
3597 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kcq_init_queue()
3612 ring = &adev->gfx.kiq[0].ring; in gfx_v9_0_kiq_resume()
3638 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_kcq_resume()
3639 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_kcq_resume()
3669 if (adev->gfx.num_gfx_rings) { in gfx_v9_0_cp_resume()
3685 if (adev->gfx.num_gfx_rings) { in gfx_v9_0_cp_resume()
3695 if (adev->gfx.num_gfx_rings) { in gfx_v9_0_cp_resume()
3696 ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_cp_resume()
3702 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_cp_resume()
3703 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_cp_resume()
3732 if (adev->gfx.num_gfx_rings) in gfx_v9_0_cp_enable()
3749 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v9_0_hw_init()
3768 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v9_0_hw_fini()
3769 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v9_0_hw_fini()
3770 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v9_0_hw_fini()
3793 soc15_grbm_select(adev, adev->gfx.kiq[0].ring.me, in gfx_v9_0_hw_fini()
3794 adev->gfx.kiq[0].ring.pipe, in gfx_v9_0_hw_fini()
3795 adev->gfx.kiq[0].ring.queue, 0, 0); in gfx_v9_0_hw_fini()
3796 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq[0].ring); in gfx_v9_0_hw_fini()
3803 /* Skip stopping RLC with A+A reset or when RLC controls GFX clock */ in gfx_v9_0_hw_fini()
3810 adev->gfx.rlc.funcs->stop(adev); in gfx_v9_0_hw_fini()
3882 adev->gfx.rlc.funcs->stop(adev); in gfx_v9_0_soft_reset()
3884 if (adev->gfx.num_gfx_rings) in gfx_v9_0_soft_reset()
3885 /* Disable GFX parsing/prefetching */ in gfx_v9_0_soft_reset()
3917 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v9_0_kiq_read_clock()
4007 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v9_0_get_gpu_clock_counter()
4015 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v9_0_get_gpu_clock_counter()
4289 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; in gfx_v9_0_do_edc_gds_workarounds()
4336 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; in gfx_v9_0_do_edc_gpr_workarounds()
4343 int compute_dim_x = adev->gfx.config.max_shader_engines * in gfx_v9_0_do_edc_gpr_workarounds()
4344 adev->gfx.config.max_cu_per_sh * in gfx_v9_0_do_edc_gpr_workarounds()
4345 adev->gfx.config.max_sh_per_se; in gfx_v9_0_do_edc_gpr_workarounds()
4347 int gpr_reg_size = adev->gfx.config.max_shader_engines + 6; in gfx_v9_0_do_edc_gpr_workarounds()
4510 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; in gfx_v9_0_early_init()
4514 adev->gfx.num_gfx_rings = 0; in gfx_v9_0_early_init()
4516 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; in gfx_v9_0_early_init()
4517 adev->gfx.xcc_mask = 1; in gfx_v9_0_early_init()
4518 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v9_0_early_init()
4559 if (adev->gfx.ras && in gfx_v9_0_ecc_late_init()
4560 adev->gfx.ras->enable_watchdog_timer) in gfx_v9_0_ecc_late_init()
4561 adev->gfx.ras->enable_watchdog_timer(adev); in gfx_v9_0_ecc_late_init()
4571 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v9_0_late_init()
4575 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v9_0_late_init()
4692 /* MGLS is a global flag to control all MGLS in GFX */ in gfx_v9_0_update_medium_grain_clock_gating()
4747 if (!adev->gfx.num_gfx_rings) in gfx_v9_0_update_3d_clock_gating()
4857 /* === CGCG /CGLS for GFX 3D Only === */ in gfx_v9_0_update_gfx_clock_gating()
4866 /* === CGCG /CGLS for GFX 3D Only === */ in gfx_v9_0_update_gfx_clock_gating()
4974 /* update gfx cgpg state */ in gfx_v9_0_set_powergating_state()
5188 gfx[0].gfx_meta_data) + in gfx_v9_0_ring_patch_ce_meta()
5220 gfx[0].gfx_meta_data) + in gfx_v9_0_ring_patch_de_meta()
5419 gfx[0].gfx_meta_data) + in gfx_v9_0_ring_emit_ce_meta()
5453 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v9_0_ring_preempt_ib()
5517 gfx[0].gfx_meta_data) + in gfx_v9_0_ring_emit_de_meta()
5525 gfx[0].gds_backup) + in gfx_v9_0_ring_emit_de_meta()
5584 /* set load_per_context_state & load_gfx_sh_regs for GFX */ in gfx_v9_ring_emit_cntxcntl()
5681 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; in gfx_v9_0_ring_emit_reg_write_reg_wait()
5902 if (adev->gfx.num_gfx_rings && in gfx_v9_0_eop_irq()
5903 !amdgpu_mcbp_handle_trailing_fence_irq(&adev->gfx.muxer)) { in gfx_v9_0_eop_irq()
5906 amdgpu_fence_process(&adev->gfx.sw_gfx_ring[i]); in gfx_v9_0_eop_irq()
5911 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_eop_irq()
5912 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_eop_irq()
5937 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); in gfx_v9_0_fault()
5941 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_fault()
5942 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_fault()
6429 DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n", in gfx_v9_0_ras_error_inject()
6437 DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n", in gfx_v9_0_ras_error_inject()
6643 dev_info(adev->dev, "GFX SubBlock %s, " in gfx_v9_0_ras_error_count()
6655 dev_info(adev->dev, "GFX SubBlock %s, " in gfx_v9_0_ras_error_count()
6820 * number of gfx waves. Setting 5 bit will make sure gfx only gets in gfx_v9_0_emit_wave_limit()
6833 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v9_0_emit_wave_limit()
7038 adev->gfx.kiq[0].ring.funcs = &gfx_v9_0_ring_funcs_kiq; in gfx_v9_0_set_ring_funcs()
7040 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v9_0_set_ring_funcs()
7041 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; in gfx_v9_0_set_ring_funcs()
7043 if (adev->gfx.num_gfx_rings) { in gfx_v9_0_set_ring_funcs()
7045 adev->gfx.sw_gfx_ring[i].funcs = &gfx_v9_0_sw_ring_funcs_gfx; in gfx_v9_0_set_ring_funcs()
7048 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_set_ring_funcs()
7049 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; in gfx_v9_0_set_ring_funcs()
7075 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v9_0_set_irq_funcs()
7076 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; in gfx_v9_0_set_irq_funcs()
7078 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v9_0_set_irq_funcs()
7079 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; in gfx_v9_0_set_irq_funcs()
7081 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v9_0_set_irq_funcs()
7082 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; in gfx_v9_0_set_irq_funcs()
7084 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/ in gfx_v9_0_set_irq_funcs()
7085 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs; in gfx_v9_0_set_irq_funcs()
7099 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; in gfx_v9_0_set_rlc_funcs()
7187 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v9_0_get_cu_active_bitmap()
7205 if (adev->gfx.config.max_shader_engines * in gfx_v9_0_get_cu_info()
7206 adev->gfx.config.max_sh_per_se > 16) in gfx_v9_0_get_cu_info()
7210 adev->gfx.config.max_shader_engines, in gfx_v9_0_get_cu_info()
7211 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_cu_info()
7214 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_get_cu_info()
7215 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_get_cu_info()
7221 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); in gfx_v9_0_get_cu_info()
7238 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v9_0_get_cu_info()
7240 if (counter < adev->gfx.config.max_cu_per_sh) in gfx_v9_0_get_cu_info()