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/Linux-v5.15/drivers/pinctrl/renesas/
Dsh_pfc.h1 /* SPDX-License-Identifier: GPL-2.0
12 #include <linux/pinctrl/pinconf-generic.h>
46 const char *name; member
54 .name = #alias, \
63 const char *name; member
77 .name = #n#s#__VA_ARGS__, \
108 .name = #n, \
114 const char *name; member
121 const char *name; member
141 * - name: Register name (unused, for documentation purposes only)
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/Linux-v5.15/drivers/pinctrl/samsung/
Dpinctrl-exynos.c1 // SPDX-License-Identifier: GPL-2.0+
27 #include <linux/soc/samsung/exynos-pmu.h>
28 #include <linux/soc/samsung/exynos-regs-pmu.h>
30 #include <dt-bindings/pinctrl/samsung.h>
32 #include "pinctrl-samsung.h"
33 #include "pinctrl-exynos.h"
56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
57 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
61 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
63 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
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Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
57 * enum eint_type - possible external interrupt types.
58 * @EINT_TYPE_NONE: bank does not support external interrupts
59 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
60 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
61 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
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Dpinctrl-samsung.c1 // SPDX-License-Identifier: GPL-2.0+
3 // pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
28 #include <dt-bindings/pinctrl/samsung.h>
31 #include "pinctrl-samsung.h"
41 { "samsung,pin-pud", PINCFG_TYPE_PUD },
42 { "samsung,pin-drv", PINCFG_TYPE_DRV },
43 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
44 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
45 { "samsung,pin-val", PINCFG_TYPE_DAT },
54 return pmx->nr_groups; in samsung_get_group_count()
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Dpinctrl-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
102 .name = id \
112 .eint_mask = (1 << (pins)) - 1, \
114 .name = id \
126 .name = id \
136 .eint_mask = (1 << (pins)) - 1, \
138 .name = id \
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Dpinctrl-s3c24xx.c1 // SPDX-License-Identifier: GPL-2.0+
22 #include "pinctrl-samsung.h"
58 .name = id \
67 .name = id \
79 .name = id \
83 * struct s3c24xx_eint_data - EINT common data
95 * struct s3c24xx_eint_domain_data - per irq-domain data
96 * @bank: pin bank related to the domain
98 * @eint0_3_parent_only: live eints 0-3 only in the main intc
101 struct samsung_pin_bank *bank; member
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/Linux-v5.15/drivers/crypto/qat/qat_common/
Dadf_transport_debug.c1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
15 struct adf_etr_ring_data *ring = sfile->private; in adf_ring_start()
21 if (*pos >= (ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size) / in adf_ring_start()
22 ADF_MSG_SIZE_TO_BYTES(ring->msg_size))) in adf_ring_start()
25 return ring->base_addr + in adf_ring_start()
26 (ADF_MSG_SIZE_TO_BYTES(ring->msg_size) * (*pos)++); in adf_ring_start()
31 struct adf_etr_ring_data *ring = sfile->private; in adf_ring_next()
33 if (*pos >= (ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size) / in adf_ring_next()
34 ADF_MSG_SIZE_TO_BYTES(ring->msg_size))) in adf_ring_next()
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/Linux-v5.15/drivers/pinctrl/
Dpinctrl-equilibrium.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
18 #include "pinctrl-equilibrium.h"
20 #define PIN_NAME_FMT "io-%d"
31 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
32 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
33 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
43 gc->direction_input(gc, offset); in eqbr_gpio_enable_irq()
44 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
45 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); in eqbr_gpio_enable_irq()
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Dpinctrl-st.c1 // SPDX-License-Identifier: GPL-2.0-only
60 * There are two registers cfg0 and cfg1 in this style for each bank.
61 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
96 * (direction, retime-type, retime-clk, retime-delay)
98 * +----------------+
99 *[31:28]| reserved-3 |
100 * +----------------+-------------
102 * +----------------+ v
104 * +----------------+ ^
106 * +----------------+-------------
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Dpinctrl-rockchip.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
74 * @offset: if initialized to -1 it will be autocalculated, by specifying
107 * @offset: if initialized to -1 it will be autocalculated, by specifying
120 * @dev: the pinctrl device bind to the bank
121 * @reg_base: register base of the gpio bank
123 * @clk: clock of the gpio bank
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Dpinctrl-oxnas.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Based on pinctrl-pic32.c
18 #include <linux/pinctrl/pinconf-generic.h>
26 #include "pinctrl-utils.h"
30 #define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK) argument
63 const char *name; member
69 const char *name; member
71 unsigned int bank; member
76 const char *name; member
254 .name = #_name, \
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Dpinctrl-at91-pio4.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/pinctrl/at91.h>
18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
30 * designed the pin id into this bank.
76 * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
78 * @last_bank_count: number of lines in the last bank (can be less than
89 const char *name; member
97 unsigned int bank; member
103 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
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Dpinctrl-equilibrium.h1 /* SPDX-License-Identifier: GPL-2.0 */
72 * @name: name of the pin function, used to lookup the function.
77 const char *name; member
83 * struct eqbr_pin_bank: represent a pin bank.
84 * @membase: base address of the pin bank register.
85 * @id: bank id, to idenify the unique bank.
86 * @pin_base: starting pin number of the pin bank.
87 * @nr_pins: number of the pins of the pin bank.
88 * @aval_pinmap: available pin bitmap of the pin bank.
101 * @bank: pointer to corresponding pin bank.
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Dpinctrl-microchip-sgpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
127 addr->port = pin / priv->bitcount; in sgpio_pin_to_addr()
128 addr->bit = pin % priv->bitcount; in sgpio_pin_to_addr()
133 return bit + port * priv->bitcount; in sgpio_addr_to_pin()
138 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; in sgpio_readl()
146 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; in sgpio_writel()
154 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; in sgpio_clrsetbits()
165 int width = priv->bitcount - 1; in sgpio_configure_bitstream()
168 switch (priv->properties->arch) { in sgpio_configure_bitstream()
194 switch (priv->properties->arch) { in sgpio_configure_clock()
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Dpinctrl-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
31 #include <linux/pinctrl/pinconf-generic.h>
36 #include <dt-bindings/pinctrl/rockchip.h>
40 #include "pinctrl-rockchip.h"
63 .name = label, \
65 { .offset = -1 }, \
66 { .offset = -1 }, \
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/Linux-v5.15/drivers/pinctrl/sunxi/
Dpinctrl-sunxi.h6 * Maxime Ripard <maxime.ripard@free-electrons.com>
32 #define SUNXI_PINCTRL_PIN(bank, pin) \ argument
33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
62 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
66 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
70 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
118 const char *name; member
142 const char *name; member
148 const char *name; member
192 .name = _name, \
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/Linux-v5.15/arch/x86/kernel/cpu/mce/
Damd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
5 * Written by Jacob Shin - AMD, Inc.
75 const char *name; /* Short name for sysfs */ member
76 const char *long_name; /* Long name for pretty-printing */
110 return smca_names[t].name; in smca_get_name()
122 static enum smca_bank_types smca_get_bank_type(unsigned int bank) in smca_get_bank_type() argument
126 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
129 b = &smca_banks[bank]; in smca_get_bank_type()
130 if (!b->hwid) in smca_get_bank_type()
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/Linux-v5.15/arch/arm/mach-omap2/
Dpowerdomain.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
6 * Copyright (C) 2007-2011 Nokia Corporation
65 static struct powerdomain *_pwrdm_lookup(const char *name) in _pwrdm_lookup() argument
72 if (!strcmp(name, temp_pwrdm->name)) { in _pwrdm_lookup()
82 * _pwrdm_register - register a powerdomain
86 * -EINVAL if given a null pointer, -EEXIST if a powerdomain is
87 * already registered by the provided name, or 0 upon success.
94 if (!pwrdm || !pwrdm->name) in _pwrdm_register()
95 return -EINVAL; in _pwrdm_register()
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/Linux-v5.15/drivers/uio/
Duio_fsl_elbc_gpcm.c1 // SPDX-License-Identifier: GPL-2.0
9 using the general purpose chip-select mode (GPCM).
17 compatible = "fsl,elbc-gpcm-uio";
19 elbc-gpcm-br = <0xff810800>;
20 elbc-gpcm-or = <0xffff09f7>;
21 interrupt-parent = <&mpic>;
25 netx5152,init-win0-offset = <0x0>;
29 Only the entries reg (to identify bank) and elbc-gpcm-* (initial BR/OR
31 are optional (as well as any type-specific options such as
32 netx5152,init-win0-offset). As long as no interrupt handler is needed,
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/Linux-v5.15/drivers/pinctrl/stm32/
Dpinctrl-stm32.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/pinctrl/pinconf-generic.h>
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-stm32.h"
79 const char *name; member
145 return function - 1; in stm32_gpio_get_alt()
153 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
156 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
157 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
160 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
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/Linux-v5.15/drivers/pinctrl/meson/
Dpinctrl-meson.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
14 * The AO bank is special because it belongs to the Always-On power
15 * domain which can't be powered off; the bank also uses a set of
31 * For the pull and GPIO configuration every bank uses a contiguous
47 #include <linux/pinctrl/pinconf-generic.h>
56 #include "../pinctrl-utils.h"
57 #include "pinctrl-meson.h"
64 * meson_get_bank() - find the bank containing a given pin
68 * @bank: the found bank
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Dpinctrl-meson.h1 /* SPDX-License-Identifier: GPL-2.0-only */
18 * struct meson_pmx_group - a pinmux group
20 * @name: group name
29 const char *name; member
36 * struct meson_pmx_func - a pinmux function
38 * @name: function name
43 const char *name; member
49 * struct meson_reg_desc - a register descriptor
55 * pull-enable, direction, etc. for a single pin
63 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
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/Linux-v5.15/drivers/leds/
Dleds-tca6507.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * leds-tca6507
9 * blink or double-blink.
12 * out-only (pull-up resistor required) or as an LED with variable
13 * brightness and hardware-assisted blinking.
21 * with separate time for rise, on, fall, off and second-off. Thus if
22 * 3 or more different non-trivial rates are required, software must
25 * support double-blink so 'second-off' always matches 'off'.
42 * delays in the ranges: 56-72, 112-144, 168-216, 224-27504,
43 * 28560-36720.
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/Linux-v5.15/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
28 [irqN]----> [gpio-bank (n)]
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/Linux-v5.15/drivers/gpio/
Dgpio-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include "../pinctrl/pinctrl-rockchip.h"
73 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument
76 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
78 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
84 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, in rockchip_gpio_readl() argument
87 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
90 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_readl()
98 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_writel_bit() argument
102 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel_bit()
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