6  * Maxime Ripard <maxime.ripard@free-electrons.com>
32 #define SUNXI_PINCTRL_PIN(bank, pin)		\  argument
33 	PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
62 #define IRQ_CFG_IRQ_MASK		((1 << IRQ_CFG_IRQ_BITS) - 1)
66 #define IRQ_CTRL_IRQ_MASK		((1 << IRQ_CTRL_IRQ_BITS) - 1)
70 #define IRQ_STATUS_IRQ_MASK		((1 << IRQ_STATUS_IRQ_BITS) - 1)
118 	const char	*name;  member
142 	const char	*name;  member
148 	const char	*name;  member
192 		.name = _name,					\
198 		.name = _name,					\
205 		.name = "irq",					\
212 		.name = "irq",					\
220  * 0x00 - 0x0c	Muxing values.
224  * 0x14 - 0x18	Drive level
226  * 0x1c - 0x20	Pull-Up values
229  * This is for the first bank. Each bank will have the same layout,
237 	u8 bank = pin / PINS_PER_BANK;  in sunxi_mux_reg()  local
238 	u32 offset = bank * BANK_MEM_SIZE;  in sunxi_mux_reg()
252 	u8 bank = pin / PINS_PER_BANK;  in sunxi_data_reg()  local
253 	u32 offset = bank * BANK_MEM_SIZE;  in sunxi_data_reg()
267 	u8 bank = pin / PINS_PER_BANK;  in sunxi_dlevel_reg()  local
268 	u32 offset = bank * BANK_MEM_SIZE;  in sunxi_dlevel_reg()
282 	u8 bank = pin / PINS_PER_BANK;  in sunxi_pull_reg()  local
283 	u32 offset = bank * BANK_MEM_SIZE;  in sunxi_pull_reg()
295 static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)  in sunxi_irq_hw_bank_num()  argument
297 	if (!desc->irq_bank_map)  in sunxi_irq_hw_bank_num()
298 		return bank;  in sunxi_irq_hw_bank_num()
300 		return desc->irq_bank_map[bank];  in sunxi_irq_hw_bank_num()
306 	u8 bank = irq / IRQ_PER_BANK;  in sunxi_irq_cfg_reg()  local
310 	       sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;  in sunxi_irq_cfg_reg()
319 static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)  in sunxi_irq_ctrl_reg_from_bank()  argument
321 	return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;  in sunxi_irq_ctrl_reg_from_bank()
327 	u8 bank = irq / IRQ_PER_BANK;  in sunxi_irq_ctrl_reg()  local
329 	return sunxi_irq_ctrl_reg_from_bank(desc, bank);  in sunxi_irq_ctrl_reg()
338 static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)  in sunxi_irq_debounce_reg_from_bank()  argument
341 	       sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;  in sunxi_irq_debounce_reg_from_bank()
344 static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)  in sunxi_irq_status_reg_from_bank()  argument
347 	       sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;  in sunxi_irq_status_reg_from_bank()
353 	u8 bank = irq / IRQ_PER_BANK;  in sunxi_irq_status_reg()  local
355 	return sunxi_irq_status_reg_from_bank(desc, bank);  in sunxi_irq_status_reg()
366 	u8 bank = pin / PINS_PER_BANK;  in sunxi_grp_config_reg()  local
368 	return GRP_CFG_REG + bank * 0x4;  in sunxi_grp_config_reg()