Lines Matching +full:bank +full:- +full:name
1 // SPDX-License-Identifier: GPL-2.0-only
60 * There are two registers cfg0 and cfg1 in this style for each bank.
61 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
96 * (direction, retime-type, retime-clk, retime-delay)
98 * +----------------+
99 *[31:28]| reserved-3 |
100 * +----------------+-------------
102 * +----------------+ v
104 * +----------------+ ^
106 * +----------------+-------------
107 *[24] | reserved-2 |
108 * +----------------+-------------
110 * +----------------+ |
111 *[22] | retime-invclk | |
112 * +----------------+ v
113 *[21] |retime-clknotdat| [Retime-type ]
114 * +----------------+ ^
115 *[20] | retime-de | |
116 * +----------------+-------------
117 *[19:18]| retime-clk |------>[Retime-Clk ]
118 * +----------------+
119 *[17:16]| reserved-1 |
120 * +----------------+
121 *[15..0]| retime-delay |------>[Retime Delay]
122 * +----------------+
249 const char *name; member
255 const char *name; member
261 const char *name; member
271 * of each gpio pin in a GPIO bank.
273 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
274 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
277 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
278 * --------------------------------------------------------
279 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
280 * --------------------------------------------------------
284 * ------- ----------------------------
285 * [0-3] - Description
286 * ------- ----------------------------
287 * 0000 - No edge IRQ.
288 * 0001 - Falling edge IRQ.
289 * 0010 - Rising edge IRQ.
290 * 0011 - Rising and Falling edge IRQ.
291 * ------- ----------------------------
356 .oe = -1, /* Not Available */
357 .pu = -1, /* Not Available */
367 struct st_gpio_bank *bank = gpio_range_to_bank(range); in st_get_pio_control() local
369 return &bank->pc; in st_get_pio_control()
386 struct regmap_field *output_enable = pc->oe; in st_pinconf_set_config()
387 struct regmap_field *pull_up = pc->pu; in st_pinconf_set_config()
388 struct regmap_field *open_drain = pc->od; in st_pinconf_set_config()
420 struct regmap_field *alt = pc->alt; in st_pctl_set_function()
436 struct regmap_field *alt = pc->alt; in st_pctl_get_pin_function()
452 int num_delay_times, i, closest_index = -1; in st_pinconf_delay_to_bit()
456 delay_times = data->output_delays; in st_pinconf_delay_to_bit()
457 num_delay_times = data->noutput_delays; in st_pinconf_delay_to_bit()
459 delay_times = data->input_delays; in st_pinconf_delay_to_bit()
460 num_delay_times = data->ninput_delays; in st_pinconf_delay_to_bit()
464 unsigned int divergence = abs(delay - delay_times[i]); in st_pinconf_delay_to_bit()
488 delay_times = data->output_delays; in st_pinconf_bit_to_delay()
489 num_delay_times = data->noutput_delays; in st_pinconf_bit_to_delay()
491 delay_times = data->input_delays; in st_pinconf_bit_to_delay()
492 num_delay_times = data->ninput_delays; in st_pinconf_bit_to_delay()
519 const struct st_pctl_data *data = info->data; in st_pinconf_set_retime_packed()
520 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pinconf_set_retime_packed()
523 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, in st_pinconf_set_retime_packed()
526 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, in st_pinconf_set_retime_packed()
529 st_regmap_field_bit_set_clear_pin(rt_p->double_edge, in st_pinconf_set_retime_packed()
532 st_regmap_field_bit_set_clear_pin(rt_p->invertclk, in st_pinconf_set_retime_packed()
535 st_regmap_field_bit_set_clear_pin(rt_p->retime, in st_pinconf_set_retime_packed()
541 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); in st_pinconf_set_retime_packed()
543 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); in st_pinconf_set_retime_packed()
558 info->data, config); in st_pinconf_set_retime_dedicated()
559 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pinconf_set_retime_dedicated()
570 regmap_field_write(rt_d->rt[pin], retime_config); in st_pinconf_set_retime_dedicated()
578 if (pc->oe) { in st_pinconf_get_direction()
579 regmap_field_read(pc->oe, &oe_value); in st_pinconf_get_direction()
584 if (pc->pu) { in st_pinconf_get_direction()
585 regmap_field_read(pc->pu, &pu_value); in st_pinconf_get_direction()
590 if (pc->od) { in st_pinconf_get_direction()
591 regmap_field_read(pc->od, &od_value); in st_pinconf_get_direction()
600 const struct st_pctl_data *data = info->data; in st_pinconf_get_retime_packed()
601 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pinconf_get_retime_packed()
605 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
608 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
611 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
614 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
617 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
620 regmap_field_read(rt_p->delay_0, &delay0); in st_pinconf_get_retime_packed()
621 regmap_field_read(rt_p->delay_1, &delay1); in st_pinconf_get_retime_packed()
636 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pinconf_get_retime_dedicated()
638 regmap_field_read(rt_d->rt[pin], &value); in st_pinconf_get_retime_dedicated()
644 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); in st_pinconf_get_retime_dedicated()
664 static inline void __st_gpio_set(struct st_gpio_bank *bank, in __st_gpio_set() argument
668 writel(BIT(offset), bank->base + REG_PIO_SET_POUT); in __st_gpio_set()
670 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); in __st_gpio_set()
673 static void st_gpio_direction(struct st_gpio_bank *bank, in st_gpio_direction() argument
687 * 0 0 0 [Input Weak pull-up] in st_gpio_direction()
697 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); in st_gpio_direction()
699 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); in st_gpio_direction()
705 struct st_gpio_bank *bank = gpiochip_get_data(chip); in st_gpio_get() local
707 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); in st_gpio_get()
712 struct st_gpio_bank *bank = gpiochip_get_data(chip); in st_gpio_set() local
713 __st_gpio_set(bank, offset, value); in st_gpio_set()
718 pinctrl_gpio_direction_input(chip->base + offset); in st_gpio_direction_input()
726 struct st_gpio_bank *bank = gpiochip_get_data(chip); in st_gpio_direction_output() local
728 __st_gpio_set(bank, offset, value); in st_gpio_direction_output()
729 pinctrl_gpio_direction_output(chip->base + offset); in st_gpio_direction_output()
736 struct st_gpio_bank *bank = gpiochip_get_data(chip); in st_gpio_get_direction() local
737 struct st_pio_control pc = bank->pc; in st_gpio_get_direction()
756 * - See st_gpio_direction() above for an explanation in st_gpio_get_direction()
759 value = readl(bank->base + REG_PIO_PC(i)); in st_gpio_get_direction()
774 return info->ngroups; in st_pctl_get_groups_count()
782 return info->groups[selector].name; in st_pctl_get_group_name()
790 if (selector >= info->ngroups) in st_pctl_get_group_pins()
791 return -EINVAL; in st_pctl_get_group_pins()
793 *pins = info->groups[selector].pins; in st_pctl_get_group_pins()
794 *npins = info->groups[selector].npins; in st_pctl_get_group_pins()
800 const struct st_pinctrl *info, const char *name) in st_pctl_find_group_by_name() argument
804 for (i = 0; i < info->ngroups; i++) { in st_pctl_find_group_by_name()
805 if (!strcmp(info->groups[i].name, name)) in st_pctl_find_group_by_name()
806 return &info->groups[i]; in st_pctl_find_group_by_name()
821 grp = st_pctl_find_group_by_name(info, np->name); in st_pctl_dt_node_to_map()
823 dev_err(info->dev, "unable to find group for node %pOFn\n", in st_pctl_dt_node_to_map()
825 return -EINVAL; in st_pctl_dt_node_to_map()
828 map_num = grp->npins + 1; in st_pctl_dt_node_to_map()
829 new_map = devm_kcalloc(pctldev->dev, in st_pctl_dt_node_to_map()
832 return -ENOMEM; in st_pctl_dt_node_to_map()
836 devm_kfree(pctldev->dev, new_map); in st_pctl_dt_node_to_map()
837 return -EINVAL; in st_pctl_dt_node_to_map()
843 new_map[0].data.mux.function = parent->name; in st_pctl_dt_node_to_map()
844 new_map[0].data.mux.group = np->name; in st_pctl_dt_node_to_map()
849 for (i = 0; i < grp->npins; i++) { in st_pctl_dt_node_to_map()
852 pin_get_name(pctldev, grp->pins[i]); in st_pctl_dt_node_to_map()
853 new_map[i].data.configs.configs = &grp->pin_conf[i].config; in st_pctl_dt_node_to_map()
856 dev_info(pctldev->dev, "maps: function %s group %s num %d\n", in st_pctl_dt_node_to_map()
857 (*map)->data.mux.function, grp->name, map_num); in st_pctl_dt_node_to_map()
880 return info->nfunctions; in st_pmx_get_funcs_count()
888 return info->functions[selector].name; in st_pmx_get_fname()
895 *grps = info->functions[selector].groups; in st_pmx_get_groups()
896 *ngrps = info->functions[selector].ngroups; in st_pmx_get_groups()
905 struct st_pinconf *conf = info->groups[group].pin_conf; in st_pmx_set_mux()
909 for (i = 0; i < info->groups[group].npins; i++) { in st_pmx_set_mux()
921 struct st_gpio_bank *bank = gpio_range_to_bank(range); in st_pmx_set_gpio_direction() local
923 * When a PIO bank is used in its primary function mode (altfunc = 0) in st_pmx_set_gpio_direction()
927 st_pctl_set_function(&bank->pc, gpio, 0); in st_pmx_set_gpio_direction()
928 st_gpio_direction(bank, gpio, input ? in st_pmx_set_gpio_direction()
947 if (info->data->rt_style == st_retime_style_packed) in st_pinconf_get_retime()
949 else if (info->data->rt_style == st_retime_style_dedicated) in st_pinconf_get_retime()
950 if ((BIT(pin) & pc->rt_pin_mask)) in st_pinconf_get_retime()
958 if (info->data->rt_style == st_retime_style_packed) in st_pinconf_set_retime()
960 else if (info->data->rt_style == st_retime_style_dedicated) in st_pinconf_set_retime()
961 if ((BIT(pin) & pc->rt_pin_mask)) in st_pinconf_set_retime()
1006 mutex_unlock(&pctldev->mutex); in st_pinconf_dbg_show()
1009 mutex_lock(&pctldev->mutex); in st_pinconf_dbg_show()
1017 oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset); in st_pinconf_dbg_show()
1020 "de:%ld,rt-clk:%ld,rt-delay:%ld]", in st_pinconf_dbg_show()
1044 if (of_property_read_bool(child, "gpio-controller")) { in st_pctl_dt_child_count()
1045 info->nbanks++; in st_pctl_dt_child_count()
1047 info->nfunctions++; in st_pctl_dt_child_count()
1048 info->ngroups += of_get_child_count(child); in st_pctl_dt_child_count()
1054 int bank, struct st_pio_control *pc) in st_pctl_dt_setup_retime_packed() argument
1056 struct device *dev = info->dev; in st_pctl_dt_setup_retime_packed()
1057 struct regmap *rm = info->regmap; in st_pctl_dt_setup_retime_packed()
1058 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime_packed()
1059 /* 2 registers per bank */ in st_pctl_dt_setup_retime_packed()
1060 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; in st_pctl_dt_setup_retime_packed()
1061 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pctl_dt_setup_retime_packed()
1072 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); in st_pctl_dt_setup_retime_packed()
1073 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); in st_pctl_dt_setup_retime_packed()
1074 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); in st_pctl_dt_setup_retime_packed()
1075 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); in st_pctl_dt_setup_retime_packed()
1076 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); in st_pctl_dt_setup_retime_packed()
1077 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); in st_pctl_dt_setup_retime_packed()
1078 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); in st_pctl_dt_setup_retime_packed()
1080 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || in st_pctl_dt_setup_retime_packed()
1081 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || in st_pctl_dt_setup_retime_packed()
1082 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || in st_pctl_dt_setup_retime_packed()
1083 IS_ERR(rt_p->double_edge)) in st_pctl_dt_setup_retime_packed()
1084 return -EINVAL; in st_pctl_dt_setup_retime_packed()
1090 int bank, struct st_pio_control *pc) in st_pctl_dt_setup_retime_dedicated() argument
1092 struct device *dev = info->dev; in st_pctl_dt_setup_retime_dedicated()
1093 struct regmap *rm = info->regmap; in st_pctl_dt_setup_retime_dedicated()
1094 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime_dedicated()
1095 /* 8 registers per bank */ in st_pctl_dt_setup_retime_dedicated()
1096 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; in st_pctl_dt_setup_retime_dedicated()
1097 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pctl_dt_setup_retime_dedicated()
1099 u32 pin_mask = pc->rt_pin_mask; in st_pctl_dt_setup_retime_dedicated()
1104 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); in st_pctl_dt_setup_retime_dedicated()
1105 if (IS_ERR(rt_d->rt[j])) in st_pctl_dt_setup_retime_dedicated()
1106 return -EINVAL; in st_pctl_dt_setup_retime_dedicated()
1114 int bank, struct st_pio_control *pc) in st_pctl_dt_setup_retime() argument
1116 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime()
1117 if (data->rt_style == st_retime_style_packed) in st_pctl_dt_setup_retime()
1118 return st_pctl_dt_setup_retime_packed(info, bank, pc); in st_pctl_dt_setup_retime()
1119 else if (data->rt_style == st_retime_style_dedicated) in st_pctl_dt_setup_retime()
1120 return st_pctl_dt_setup_retime_dedicated(info, bank, pc); in st_pctl_dt_setup_retime()
1122 return -EINVAL; in st_pctl_dt_setup_retime()
1127 struct regmap *regmap, int bank, in st_pc_get_value() argument
1130 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb); in st_pc_get_value()
1138 static void st_parse_syscfgs(struct st_pinctrl *info, int bank, in st_parse_syscfgs() argument
1141 const struct st_pctl_data *data = info->data; in st_parse_syscfgs()
1143 * For a given shared register like OE/PU/OD, there are 8 bits per bank in st_parse_syscfgs()
1147 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; in st_parse_syscfgs()
1148 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; in st_parse_syscfgs()
1149 struct st_pio_control *pc = &info->banks[bank].pc; in st_parse_syscfgs()
1150 struct device *dev = info->dev; in st_parse_syscfgs()
1151 struct regmap *regmap = info->regmap; in st_parse_syscfgs()
1153 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); in st_parse_syscfgs()
1154 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); in st_parse_syscfgs()
1155 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); in st_parse_syscfgs()
1156 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); in st_parse_syscfgs()
1159 pc->rt_pin_mask = 0xff; in st_parse_syscfgs()
1160 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); in st_parse_syscfgs()
1161 st_pctl_dt_setup_retime(info, bank, pc); in st_parse_syscfgs()
1168 * <bank offset mux direction rt_type rt_delay rt_clk>
1173 /* bank pad direction val altfunction */ in st_pctl_dt_parse_groups()
1182 return -ENODATA; in st_pctl_dt_parse_groups()
1186 if (!strcmp(pp->name, "name")) in st_pctl_dt_parse_groups()
1189 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) { in st_pctl_dt_parse_groups()
1193 ret = -EINVAL; in st_pctl_dt_parse_groups()
1198 grp->npins = npins; in st_pctl_dt_parse_groups()
1199 grp->name = np->name; in st_pctl_dt_parse_groups()
1200 grp->pins = devm_kcalloc(info->dev, npins, sizeof(u32), GFP_KERNEL); in st_pctl_dt_parse_groups()
1201 grp->pin_conf = devm_kcalloc(info->dev, in st_pctl_dt_parse_groups()
1204 if (!grp->pins || !grp->pin_conf) { in st_pctl_dt_parse_groups()
1205 ret = -ENOMEM; in st_pctl_dt_parse_groups()
1209 /* <bank offset mux direction rt_type rt_delay rt_clk> */ in st_pctl_dt_parse_groups()
1211 if (!strcmp(pp->name, "name")) in st_pctl_dt_parse_groups()
1213 nr_props = pp->length/sizeof(u32); in st_pctl_dt_parse_groups()
1214 list = pp->value; in st_pctl_dt_parse_groups()
1215 conf = &grp->pin_conf[i]; in st_pctl_dt_parse_groups()
1217 /* bank & offset */ in st_pctl_dt_parse_groups()
1220 conf->pin = of_get_named_gpio(pins, pp->name, 0); in st_pctl_dt_parse_groups()
1221 conf->name = pp->name; in st_pctl_dt_parse_groups()
1222 grp->pins[i] = conf->pin; in st_pctl_dt_parse_groups()
1224 conf->altfunc = be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1225 conf->config = 0; in st_pctl_dt_parse_groups()
1227 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1231 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1233 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1236 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1255 func = &info->functions[index]; in st_pctl_parse_functions()
1256 func->name = np->name; in st_pctl_parse_functions()
1257 func->ngroups = of_get_child_count(np); in st_pctl_parse_functions()
1258 if (func->ngroups == 0) { in st_pctl_parse_functions()
1259 dev_err(info->dev, "No groups defined\n"); in st_pctl_parse_functions()
1260 return -EINVAL; in st_pctl_parse_functions()
1262 func->groups = devm_kcalloc(info->dev, in st_pctl_parse_functions()
1263 func->ngroups, sizeof(char *), GFP_KERNEL); in st_pctl_parse_functions()
1264 if (!func->groups) in st_pctl_parse_functions()
1265 return -ENOMEM; in st_pctl_parse_functions()
1269 func->groups[i] = child->name; in st_pctl_parse_functions()
1270 grp = &info->groups[*grp_index]; in st_pctl_parse_functions()
1278 dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n", in st_pctl_parse_functions()
1279 index, func->name, func->ngroups); in st_pctl_parse_functions()
1287 struct st_gpio_bank *bank = gpiochip_get_data(gc); in st_gpio_irq_mask() local
1289 writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); in st_gpio_irq_mask()
1295 struct st_gpio_bank *bank = gpiochip_get_data(gc); in st_gpio_irq_unmask() local
1297 writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); in st_gpio_irq_unmask()
1304 st_gpio_direction_input(gc, d->hwirq); in st_gpio_irq_request_resources()
1306 return gpiochip_lock_as_irq(gc, d->hwirq); in st_gpio_irq_request_resources()
1313 gpiochip_unlock_as_irq(gc, d->hwirq); in st_gpio_irq_release_resources()
1319 struct st_gpio_bank *bank = gpiochip_get_data(gc); in st_gpio_irq_set_type() local
1321 int comp, pin = d->hwirq; in st_gpio_irq_set_type()
1341 comp = st_gpio_get(&bank->gpio_chip, pin); in st_gpio_irq_set_type()
1345 return -EINVAL; in st_gpio_irq_set_type()
1348 spin_lock_irqsave(&bank->lock, flags); in st_gpio_irq_set_type()
1349 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( in st_gpio_irq_set_type()
1351 bank->irq_edge_conf |= pin_edge_conf; in st_gpio_irq_set_type()
1352 spin_unlock_irqrestore(&bank->lock, flags); in st_gpio_irq_set_type()
1354 val = readl(bank->base + REG_PIO_PCOMP); in st_gpio_irq_set_type()
1357 writel(val, bank->base + REG_PIO_PCOMP); in st_gpio_irq_set_type()
1370 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
1374 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
1378 * step-1 ________ __________
1379 * | | step - 3
1381 * step -2 |_____|
1386 static void __gpio_irq_handler(struct st_gpio_bank *bank) in __gpio_irq_handler() argument
1392 spin_lock_irqsave(&bank->lock, flags); in __gpio_irq_handler()
1393 bank_edge_mask = bank->irq_edge_conf; in __gpio_irq_handler()
1394 spin_unlock_irqrestore(&bank->lock, flags); in __gpio_irq_handler()
1397 port_in = readl(bank->base + REG_PIO_PIN); in __gpio_irq_handler()
1398 port_comp = readl(bank->base + REG_PIO_PCOMP); in __gpio_irq_handler()
1399 port_mask = readl(bank->base + REG_PIO_PMASK); in __gpio_irq_handler()
1412 val = st_gpio_get(&bank->gpio_chip, n); in __gpio_irq_handler()
1415 val ? bank->base + REG_PIO_SET_PCOMP : in __gpio_irq_handler()
1416 bank->base + REG_PIO_CLR_PCOMP); in __gpio_irq_handler()
1423 generic_handle_domain_irq(bank->gpio_chip.irq.domain, n); in __gpio_irq_handler()
1430 /* interrupt dedicated per bank */ in st_gpio_irq_handler()
1433 struct st_gpio_bank *bank = gpiochip_get_data(gc); in st_gpio_irq_handler() local
1436 __gpio_irq_handler(bank); in st_gpio_irq_handler()
1449 status = readl(info->irqmux_base); in st_gpio_irqmux_handler()
1451 for_each_set_bit(n, &status, info->nbanks) in st_gpio_irqmux_handler()
1452 __gpio_irq_handler(&info->banks[n]); in st_gpio_irqmux_handler()
1469 .name = "GPIO",
1482 struct st_gpio_bank *bank = &info->banks[bank_nr]; in st_gpiolib_register_bank() local
1483 struct pinctrl_gpio_range *range = &bank->range; in st_gpiolib_register_bank()
1484 struct device *dev = info->dev; in st_gpiolib_register_bank()
1490 return -ENODEV; in st_gpiolib_register_bank()
1492 bank->base = devm_ioremap_resource(dev, &res); in st_gpiolib_register_bank()
1493 if (IS_ERR(bank->base)) in st_gpiolib_register_bank()
1494 return PTR_ERR(bank->base); in st_gpiolib_register_bank()
1496 bank->gpio_chip = st_gpio_template; in st_gpiolib_register_bank()
1497 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1498 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1499 bank->gpio_chip.of_node = np; in st_gpiolib_register_bank()
1500 bank->gpio_chip.parent = dev; in st_gpiolib_register_bank()
1501 spin_lock_init(&bank->lock); in st_gpiolib_register_bank()
1503 of_property_read_string(np, "st,bank-name", &range->name); in st_gpiolib_register_bank()
1504 bank->gpio_chip.label = range->name; in st_gpiolib_register_bank()
1506 range->id = bank_num; in st_gpiolib_register_bank()
1507 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1508 range->npins = bank->gpio_chip.ngpio; in st_gpiolib_register_bank()
1509 range->gc = &bank->gpio_chip; in st_gpiolib_register_bank()
1512 * GPIO bank can have one of the two possible types of in st_gpiolib_register_bank()
1513 * interrupt-wirings. in st_gpiolib_register_bank()
1519 * | |----> [gpio-bank (n) ] in st_gpiolib_register_bank()
1520 * | |----> [gpio-bank (n + 1)] in st_gpiolib_register_bank()
1521 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] in st_gpiolib_register_bank()
1522 * | |----> [gpio-bank (... )] in st_gpiolib_register_bank()
1523 * |_________|----> [gpio-bank (n + 7)] in st_gpiolib_register_bank()
1525 * Second type has a dedicated interrupt per each gpio bank. in st_gpiolib_register_bank()
1527 * [irqN]----> [gpio-bank (n)] in st_gpiolib_register_bank()
1536 dev_err(dev, "invalid IRQ for %pOF bank\n", np); in st_gpiolib_register_bank()
1540 if (!info->irqmux_base) { in st_gpiolib_register_bank()
1541 dev_err(dev, "no irqmux for %pOF bank\n", np); in st_gpiolib_register_bank()
1545 girq = &bank->gpio_chip.irq; in st_gpiolib_register_bank()
1546 girq->chip = &st_gpio_irqchip; in st_gpiolib_register_bank()
1547 girq->parent_handler = st_gpio_irq_handler; in st_gpiolib_register_bank()
1548 girq->num_parents = 1; in st_gpiolib_register_bank()
1549 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), in st_gpiolib_register_bank()
1551 if (!girq->parents) in st_gpiolib_register_bank()
1552 return -ENOMEM; in st_gpiolib_register_bank()
1553 girq->parents[0] = gpio_irq; in st_gpiolib_register_bank()
1554 girq->default_type = IRQ_TYPE_NONE; in st_gpiolib_register_bank()
1555 girq->handler = handle_simple_irq; in st_gpiolib_register_bank()
1559 err = gpiochip_add_data(&bank->gpio_chip, bank); in st_gpiolib_register_bank()
1564 dev_info(dev, "%s bank added.\n", range->name); in st_gpiolib_register_bank()
1570 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data},
1571 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data},
1572 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data},
1573 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
1581 int i = 0, j = 0, k = 0, bank; in st_pctl_probe_dt() local
1583 struct device_node *np = pdev->dev.of_node; in st_pctl_probe_dt()
1590 if (!info->nbanks) { in st_pctl_probe_dt()
1591 dev_err(&pdev->dev, "you need atleast one gpio bank\n"); in st_pctl_probe_dt()
1592 return -EINVAL; in st_pctl_probe_dt()
1595 dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks); in st_pctl_probe_dt()
1596 dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions); in st_pctl_probe_dt()
1597 dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups); in st_pctl_probe_dt()
1599 info->functions = devm_kcalloc(&pdev->dev, in st_pctl_probe_dt()
1600 info->nfunctions, sizeof(*info->functions), GFP_KERNEL); in st_pctl_probe_dt()
1602 info->groups = devm_kcalloc(&pdev->dev, in st_pctl_probe_dt()
1603 info->ngroups, sizeof(*info->groups), in st_pctl_probe_dt()
1606 info->banks = devm_kcalloc(&pdev->dev, in st_pctl_probe_dt()
1607 info->nbanks, sizeof(*info->banks), GFP_KERNEL); in st_pctl_probe_dt()
1609 if (!info->functions || !info->groups || !info->banks) in st_pctl_probe_dt()
1610 return -ENOMEM; in st_pctl_probe_dt()
1612 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in st_pctl_probe_dt()
1613 if (IS_ERR(info->regmap)) { in st_pctl_probe_dt()
1614 dev_err(info->dev, "No syscfg phandle specified\n"); in st_pctl_probe_dt()
1615 return PTR_ERR(info->regmap); in st_pctl_probe_dt()
1617 info->data = of_match_node(st_pctl_of_match, np)->data; in st_pctl_probe_dt()
1624 info->irqmux_base = devm_ioremap_resource(&pdev->dev, res); in st_pctl_probe_dt()
1626 if (IS_ERR(info->irqmux_base)) in st_pctl_probe_dt()
1627 return PTR_ERR(info->irqmux_base); in st_pctl_probe_dt()
1634 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; in st_pctl_probe_dt()
1635 pdesc = devm_kcalloc(&pdev->dev, in st_pctl_probe_dt()
1636 pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); in st_pctl_probe_dt()
1638 return -ENOMEM; in st_pctl_probe_dt()
1640 pctl_desc->pins = pdesc; in st_pctl_probe_dt()
1642 bank = 0; in st_pctl_probe_dt()
1644 if (of_property_read_bool(child, "gpio-controller")) { in st_pctl_probe_dt()
1646 ret = st_gpiolib_register_bank(info, bank, child); in st_pctl_probe_dt()
1652 k = info->banks[bank].range.pin_base; in st_pctl_probe_dt()
1653 bank_name = info->banks[bank].range.name; in st_pctl_probe_dt()
1655 pdesc->number = k; in st_pctl_probe_dt()
1656 pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]", in st_pctl_probe_dt()
1660 st_parse_syscfgs(info, bank, child); in st_pctl_probe_dt()
1661 bank++; in st_pctl_probe_dt()
1666 dev_err(&pdev->dev, "No functions found.\n"); in st_pctl_probe_dt()
1682 if (!pdev->dev.of_node) { in st_pctl_probe()
1683 dev_err(&pdev->dev, "device node not found.\n"); in st_pctl_probe()
1684 return -EINVAL; in st_pctl_probe()
1687 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); in st_pctl_probe()
1689 return -ENOMEM; in st_pctl_probe()
1691 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); in st_pctl_probe()
1693 return -ENOMEM; in st_pctl_probe()
1695 info->dev = &pdev->dev; in st_pctl_probe()
1701 pctl_desc->owner = THIS_MODULE; in st_pctl_probe()
1702 pctl_desc->pctlops = &st_pctlops; in st_pctl_probe()
1703 pctl_desc->pmxops = &st_pmxops; in st_pctl_probe()
1704 pctl_desc->confops = &st_confops; in st_pctl_probe()
1705 pctl_desc->name = dev_name(&pdev->dev); in st_pctl_probe()
1707 info->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, info); in st_pctl_probe()
1708 if (IS_ERR(info->pctl)) { in st_pctl_probe()
1709 dev_err(&pdev->dev, "Failed pinctrl registration\n"); in st_pctl_probe()
1710 return PTR_ERR(info->pctl); in st_pctl_probe()
1713 for (i = 0; i < info->nbanks; i++) in st_pctl_probe()
1714 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); in st_pctl_probe()
1721 .name = "st-pinctrl",