Lines Matching +full:bank +full:- +full:name
1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
31 #include <linux/pinctrl/pinconf-generic.h>
36 #include <dt-bindings/pinctrl/rockchip.h>
40 #include "pinctrl-rockchip.h"
63 .name = label, \
65 { .offset = -1 }, \
66 { .offset = -1 }, \
67 { .offset = -1 }, \
68 { .offset = -1 }, \
76 .name = label, \
78 { .type = iom0, .offset = -1 }, \
79 { .type = iom1, .offset = -1 }, \
80 { .type = iom2, .offset = -1 }, \
81 { .type = iom3, .offset = -1 }, \
89 .name = label, \
91 { .offset = -1 }, \
92 { .offset = -1 }, \
93 { .offset = -1 }, \
94 { .offset = -1 }, \
97 { .drv_type = type0, .offset = -1 }, \
98 { .drv_type = type1, .offset = -1 }, \
99 { .drv_type = type2, .offset = -1 }, \
100 { .drv_type = type3, .offset = -1 }, \
110 .name = label, \
112 { .offset = -1 }, \
113 { .offset = -1 }, \
114 { .offset = -1 }, \
115 { .offset = -1 }, \
118 { .drv_type = drv0, .offset = -1 }, \
119 { .drv_type = drv1, .offset = -1 }, \
120 { .drv_type = drv2, .offset = -1 }, \
121 { .drv_type = drv3, .offset = -1 }, \
136 .name = label, \
138 { .type = iom0, .offset = -1 }, \
139 { .type = iom1, .offset = -1 }, \
140 { .type = iom2, .offset = -1 }, \
141 { .type = iom3, .offset = -1 }, \
160 .name = label, \
162 { .type = iom0, .offset = -1 }, \
163 { .type = iom1, .offset = -1 }, \
164 { .type = iom2, .offset = -1 }, \
165 { .type = iom3, .offset = -1 }, \
206 const char *name) in pinctrl_name_to_group() argument
210 for (i = 0; i < info->ngroups; i++) { in pinctrl_name_to_group()
211 if (!strcmp(info->groups[i].name, name)) in pinctrl_name_to_group()
212 return &info->groups[i]; in pinctrl_name_to_group()
219 * given a pin number that is local to a pin controller, find out the pin bank
220 * and the register base of the pin bank.
225 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in pin_to_bank()
227 while (pin >= (b->pin_base + b->nr_pins)) in pin_to_bank()
237 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in bank_num_to_bank()
240 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { in bank_num_to_bank()
241 if (b->bank_num == num) in bank_num_to_bank()
245 return ERR_PTR(-EINVAL); in bank_num_to_bank()
256 return info->ngroups; in rockchip_get_groups_count()
264 return info->groups[selector].name; in rockchip_get_group_name()
273 if (selector >= info->ngroups) in rockchip_get_group_pins()
274 return -EINVAL; in rockchip_get_group_pins()
276 *pins = info->groups[selector].pins; in rockchip_get_group_pins()
277 *npins = info->groups[selector].npins; in rockchip_get_group_pins()
297 grp = pinctrl_name_to_group(info, np->name); in rockchip_dt_node_to_map()
299 dev_err(info->dev, "unable to find group for node %pOFn\n", in rockchip_dt_node_to_map()
301 return -EINVAL; in rockchip_dt_node_to_map()
304 map_num += grp->npins; in rockchip_dt_node_to_map()
308 return -ENOMEM; in rockchip_dt_node_to_map()
317 return -EINVAL; in rockchip_dt_node_to_map()
320 new_map[0].data.mux.function = parent->name; in rockchip_dt_node_to_map()
321 new_map[0].data.mux.group = np->name; in rockchip_dt_node_to_map()
326 for (i = 0; i < grp->npins; i++) { in rockchip_dt_node_to_map()
329 pin_get_name(pctldev, grp->pins[i]); in rockchip_dt_node_to_map()
330 new_map[i].data.configs.configs = grp->data[i].configs; in rockchip_dt_node_to_map()
331 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; in rockchip_dt_node_to_map()
334 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", in rockchip_dt_node_to_map()
335 (*map)->data.mux.function, (*map)->data.mux.group, map_num); in rockchip_dt_node_to_map()
572 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument
575 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
576 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_recalced_mux()
580 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux()
581 data = &ctrl->iomux_recalced[i]; in rockchip_get_recalced_mux()
582 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
583 data->pin == pin) in rockchip_get_recalced_mux()
587 if (i >= ctrl->niomux_recalced) in rockchip_get_recalced_mux()
590 *reg = data->reg; in rockchip_get_recalced_mux()
591 *mask = data->mask; in rockchip_get_recalced_mux()
592 *bit = data->bit; in rockchip_get_recalced_mux()
596 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
597 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
598 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
599 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
600 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
601 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
602 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
603 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
607 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
608 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
609 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
610 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
611 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
612 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
613 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
617 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
618 …UTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
622 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
623 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
624 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
625 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
626 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
627 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
628 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
629 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
630 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
631 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
632 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
633 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
634 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
635 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
636 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
637 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
638 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
639 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
654 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
655 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
656 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
657 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
658 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
659 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
660 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
661 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
679 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
680 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
795 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument
798 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
799 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_mux_route()
803 for (i = 0; i < ctrl->niomux_routes; i++) { in rockchip_get_mux_route()
804 data = &ctrl->iomux_routes[i]; in rockchip_get_mux_route()
805 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
806 (data->pin == pin) && (data->func == mux)) in rockchip_get_mux_route()
810 if (i >= ctrl->niomux_routes) in rockchip_get_mux_route()
813 *loc = data->route_location; in rockchip_get_mux_route()
814 *reg = data->route_offset; in rockchip_get_mux_route()
815 *value = data->route_val; in rockchip_get_mux_route()
820 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) in rockchip_get_mux() argument
822 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux()
830 return -EINVAL; in rockchip_get_mux()
832 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
833 dev_err(info->dev, "pin %d is unrouted\n", pin); in rockchip_get_mux()
834 return -EINVAL; in rockchip_get_mux()
837 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
840 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_get_mux()
841 ? info->regmap_pmu : info->regmap_base; in rockchip_get_mux()
844 mux_type = bank->iomux[iomux_num].type; in rockchip_get_mux()
845 reg = bank->iomux[iomux_num].offset; in rockchip_get_mux()
861 if (bank->recalced_mask & BIT(pin)) in rockchip_get_mux()
862 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); in rockchip_get_mux()
871 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, in rockchip_verify_mux() argument
874 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_verify_mux()
878 return -EINVAL; in rockchip_verify_mux()
880 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_verify_mux()
881 dev_err(info->dev, "pin %d is unrouted\n", pin); in rockchip_verify_mux()
882 return -EINVAL; in rockchip_verify_mux()
885 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { in rockchip_verify_mux()
887 dev_err(info->dev, in rockchip_verify_mux()
889 return -ENOTSUPP; in rockchip_verify_mux()
905 * @bank: pin bank to change
909 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rockchip_set_mux() argument
911 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_mux()
918 ret = rockchip_verify_mux(bank, pin, mux); in rockchip_set_mux()
922 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_set_mux()
925 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", in rockchip_set_mux()
926 bank->bank_num, pin, mux); in rockchip_set_mux()
928 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_set_mux()
929 ? info->regmap_pmu : info->regmap_base; in rockchip_set_mux()
932 mux_type = bank->iomux[iomux_num].type; in rockchip_set_mux()
933 reg = bank->iomux[iomux_num].offset; in rockchip_set_mux()
949 if (bank->recalced_mask & BIT(pin)) in rockchip_set_mux()
950 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); in rockchip_set_mux()
952 if (bank->route_mask & BIT(pin)) { in rockchip_set_mux()
953 if (rockchip_get_mux_route(bank, pin, mux, &route_location, in rockchip_set_mux()
960 route_regmap = info->regmap_pmu; in rockchip_set_mux()
963 route_regmap = info->regmap_base; in rockchip_set_mux()
987 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in px30_calc_pull_reg_and_bit() argument
991 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_pull_reg_and_bit()
993 /* The first 32 pins of the first bank are located in PMU */ in px30_calc_pull_reg_and_bit()
994 if (bank->bank_num == 0) { in px30_calc_pull_reg_and_bit()
995 *regmap = info->regmap_pmu; in px30_calc_pull_reg_and_bit()
998 *regmap = info->regmap_base; in px30_calc_pull_reg_and_bit()
1001 /* correct the offset, as we're starting with the 2nd bank */ in px30_calc_pull_reg_and_bit()
1002 *reg -= 0x10; in px30_calc_pull_reg_and_bit()
1003 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; in px30_calc_pull_reg_and_bit()
1017 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in px30_calc_drv_reg_and_bit() argument
1021 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_drv_reg_and_bit()
1023 /* The first 32 pins of the first bank are located in PMU */ in px30_calc_drv_reg_and_bit()
1024 if (bank->bank_num == 0) { in px30_calc_drv_reg_and_bit()
1025 *regmap = info->regmap_pmu; in px30_calc_drv_reg_and_bit()
1028 *regmap = info->regmap_base; in px30_calc_drv_reg_and_bit()
1031 /* correct the offset, as we're starting with the 2nd bank */ in px30_calc_drv_reg_and_bit()
1032 *reg -= 0x10; in px30_calc_drv_reg_and_bit()
1033 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; in px30_calc_drv_reg_and_bit()
1047 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, in px30_calc_schmitt_reg_and_bit() argument
1052 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_schmitt_reg_and_bit()
1055 if (bank->bank_num == 0) { in px30_calc_schmitt_reg_and_bit()
1056 *regmap = info->regmap_pmu; in px30_calc_schmitt_reg_and_bit()
1060 *regmap = info->regmap_base; in px30_calc_schmitt_reg_and_bit()
1063 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; in px30_calc_schmitt_reg_and_bit()
1078 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rv1108_calc_pull_reg_and_bit() argument
1082 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_pull_reg_and_bit()
1084 /* The first 24 pins of the first bank are located in PMU */ in rv1108_calc_pull_reg_and_bit()
1085 if (bank->bank_num == 0) { in rv1108_calc_pull_reg_and_bit()
1086 *regmap = info->regmap_pmu; in rv1108_calc_pull_reg_and_bit()
1090 *regmap = info->regmap_base; in rv1108_calc_pull_reg_and_bit()
1091 /* correct the offset, as we're starting with the 2nd bank */ in rv1108_calc_pull_reg_and_bit()
1092 *reg -= 0x10; in rv1108_calc_pull_reg_and_bit()
1093 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; in rv1108_calc_pull_reg_and_bit()
1107 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rv1108_calc_drv_reg_and_bit() argument
1111 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_drv_reg_and_bit()
1113 /* The first 24 pins of the first bank are located in PMU */ in rv1108_calc_drv_reg_and_bit()
1114 if (bank->bank_num == 0) { in rv1108_calc_drv_reg_and_bit()
1115 *regmap = info->regmap_pmu; in rv1108_calc_drv_reg_and_bit()
1118 *regmap = info->regmap_base; in rv1108_calc_drv_reg_and_bit()
1121 /* correct the offset, as we're starting with the 2nd bank */ in rv1108_calc_drv_reg_and_bit()
1122 *reg -= 0x10; in rv1108_calc_drv_reg_and_bit()
1123 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; in rv1108_calc_drv_reg_and_bit()
1137 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, in rv1108_calc_schmitt_reg_and_bit() argument
1142 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_schmitt_reg_and_bit()
1145 if (bank->bank_num == 0) { in rv1108_calc_schmitt_reg_and_bit()
1146 *regmap = info->regmap_pmu; in rv1108_calc_schmitt_reg_and_bit()
1150 *regmap = info->regmap_base; in rv1108_calc_schmitt_reg_and_bit()
1153 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; in rv1108_calc_schmitt_reg_and_bit()
1165 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, in rk3308_calc_schmitt_reg_and_bit() argument
1169 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_schmitt_reg_and_bit()
1171 *regmap = info->regmap_base; in rk3308_calc_schmitt_reg_and_bit()
1174 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; in rk3308_calc_schmitt_reg_and_bit()
1185 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk2928_calc_pull_reg_and_bit() argument
1189 struct rockchip_pinctrl *info = bank->drvdata; in rk2928_calc_pull_reg_and_bit()
1191 *regmap = info->regmap_base; in rk2928_calc_pull_reg_and_bit()
1193 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk2928_calc_pull_reg_and_bit()
1201 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3128_calc_pull_reg_and_bit() argument
1205 struct rockchip_pinctrl *info = bank->drvdata; in rk3128_calc_pull_reg_and_bit()
1207 *regmap = info->regmap_base; in rk3128_calc_pull_reg_and_bit()
1209 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk3128_calc_pull_reg_and_bit()
1221 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3188_calc_pull_reg_and_bit() argument
1225 struct rockchip_pinctrl *info = bank->drvdata; in rk3188_calc_pull_reg_and_bit()
1227 /* The first 12 pins of the first bank are located elsewhere */ in rk3188_calc_pull_reg_and_bit()
1228 if (bank->bank_num == 0 && pin_num < 12) { in rk3188_calc_pull_reg_and_bit()
1229 *regmap = info->regmap_pmu ? info->regmap_pmu in rk3188_calc_pull_reg_and_bit()
1230 : bank->regmap_pull; in rk3188_calc_pull_reg_and_bit()
1231 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; in rk3188_calc_pull_reg_and_bit()
1236 *regmap = info->regmap_pull ? info->regmap_pull in rk3188_calc_pull_reg_and_bit()
1237 : info->regmap_base; in rk3188_calc_pull_reg_and_bit()
1238 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; in rk3188_calc_pull_reg_and_bit()
1241 *reg -= 4; in rk3188_calc_pull_reg_and_bit()
1242 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3188_calc_pull_reg_and_bit()
1250 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); in rk3188_calc_pull_reg_and_bit()
1256 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3288_calc_pull_reg_and_bit() argument
1260 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_pull_reg_and_bit()
1262 /* The first 24 pins of the first bank are located in PMU */ in rk3288_calc_pull_reg_and_bit()
1263 if (bank->bank_num == 0) { in rk3288_calc_pull_reg_and_bit()
1264 *regmap = info->regmap_pmu; in rk3288_calc_pull_reg_and_bit()
1271 *regmap = info->regmap_base; in rk3288_calc_pull_reg_and_bit()
1274 /* correct the offset, as we're starting with the 2nd bank */ in rk3288_calc_pull_reg_and_bit()
1275 *reg -= 0x10; in rk3288_calc_pull_reg_and_bit()
1276 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3288_calc_pull_reg_and_bit()
1290 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3288_calc_drv_reg_and_bit() argument
1294 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_drv_reg_and_bit()
1296 /* The first 24 pins of the first bank are located in PMU */ in rk3288_calc_drv_reg_and_bit()
1297 if (bank->bank_num == 0) { in rk3288_calc_drv_reg_and_bit()
1298 *regmap = info->regmap_pmu; in rk3288_calc_drv_reg_and_bit()
1305 *regmap = info->regmap_base; in rk3288_calc_drv_reg_and_bit()
1308 /* correct the offset, as we're starting with the 2nd bank */ in rk3288_calc_drv_reg_and_bit()
1309 *reg -= 0x10; in rk3288_calc_drv_reg_and_bit()
1310 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3288_calc_drv_reg_and_bit()
1320 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3228_calc_pull_reg_and_bit() argument
1324 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_pull_reg_and_bit()
1326 *regmap = info->regmap_base; in rk3228_calc_pull_reg_and_bit()
1328 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3228_calc_pull_reg_and_bit()
1337 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3228_calc_drv_reg_and_bit() argument
1341 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_drv_reg_and_bit()
1343 *regmap = info->regmap_base; in rk3228_calc_drv_reg_and_bit()
1345 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3228_calc_drv_reg_and_bit()
1354 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3308_calc_pull_reg_and_bit() argument
1358 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_pull_reg_and_bit()
1360 *regmap = info->regmap_base; in rk3308_calc_pull_reg_and_bit()
1362 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3308_calc_pull_reg_and_bit()
1371 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3308_calc_drv_reg_and_bit() argument
1375 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_drv_reg_and_bit()
1377 *regmap = info->regmap_base; in rk3308_calc_drv_reg_and_bit()
1379 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3308_calc_drv_reg_and_bit()
1389 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3368_calc_pull_reg_and_bit() argument
1393 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_pull_reg_and_bit()
1395 /* The first 32 pins of the first bank are located in PMU */ in rk3368_calc_pull_reg_and_bit()
1396 if (bank->bank_num == 0) { in rk3368_calc_pull_reg_and_bit()
1397 *regmap = info->regmap_pmu; in rk3368_calc_pull_reg_and_bit()
1404 *regmap = info->regmap_base; in rk3368_calc_pull_reg_and_bit()
1407 /* correct the offset, as we're starting with the 2nd bank */ in rk3368_calc_pull_reg_and_bit()
1408 *reg -= 0x10; in rk3368_calc_pull_reg_and_bit()
1409 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3368_calc_pull_reg_and_bit()
1420 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3368_calc_drv_reg_and_bit() argument
1424 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_drv_reg_and_bit()
1426 /* The first 32 pins of the first bank are located in PMU */ in rk3368_calc_drv_reg_and_bit()
1427 if (bank->bank_num == 0) { in rk3368_calc_drv_reg_and_bit()
1428 *regmap = info->regmap_pmu; in rk3368_calc_drv_reg_and_bit()
1435 *regmap = info->regmap_base; in rk3368_calc_drv_reg_and_bit()
1438 /* correct the offset, as we're starting with the 2nd bank */ in rk3368_calc_drv_reg_and_bit()
1439 *reg -= 0x10; in rk3368_calc_drv_reg_and_bit()
1440 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3368_calc_drv_reg_and_bit()
1452 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3399_calc_pull_reg_and_bit() argument
1456 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_pull_reg_and_bit()
1459 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { in rk3399_calc_pull_reg_and_bit()
1460 *regmap = info->regmap_pmu; in rk3399_calc_pull_reg_and_bit()
1463 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
1469 *regmap = info->regmap_base; in rk3399_calc_pull_reg_and_bit()
1472 /* correct the offset, as we're starting with the 3rd bank */ in rk3399_calc_pull_reg_and_bit()
1473 *reg -= 0x20; in rk3399_calc_pull_reg_and_bit()
1474 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
1482 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3399_calc_drv_reg_and_bit() argument
1486 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_drv_reg_and_bit()
1490 if ((bank->bank_num == 0) || (bank->bank_num == 1)) in rk3399_calc_drv_reg_and_bit()
1491 *regmap = info->regmap_pmu; in rk3399_calc_drv_reg_and_bit()
1493 *regmap = info->regmap_base; in rk3399_calc_drv_reg_and_bit()
1495 *reg = bank->drv[drv_num].offset; in rk3399_calc_drv_reg_and_bit()
1496 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rk3399_calc_drv_reg_and_bit()
1497 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) in rk3399_calc_drv_reg_and_bit()
1509 static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3568_calc_pull_reg_and_bit() argument
1513 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_pull_reg_and_bit()
1515 if (bank->bank_num == 0) { in rk3568_calc_pull_reg_and_bit()
1516 *regmap = info->regmap_pmu; in rk3568_calc_pull_reg_and_bit()
1518 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; in rk3568_calc_pull_reg_and_bit()
1524 *regmap = info->regmap_base; in rk3568_calc_pull_reg_and_bit()
1526 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; in rk3568_calc_pull_reg_and_bit()
1540 static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3568_calc_drv_reg_and_bit() argument
1544 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_drv_reg_and_bit()
1546 /* The first 32 pins of the first bank are located in PMU */ in rk3568_calc_drv_reg_and_bit()
1547 if (bank->bank_num == 0) { in rk3568_calc_drv_reg_and_bit()
1548 *regmap = info->regmap_pmu; in rk3568_calc_drv_reg_and_bit()
1555 *regmap = info->regmap_base; in rk3568_calc_drv_reg_and_bit()
1557 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; in rk3568_calc_drv_reg_and_bit()
1566 { 2, 4, 8, 12, -1, -1, -1, -1 },
1567 { 3, 6, 9, 12, -1, -1, -1, -1 },
1568 { 5, 10, 15, 20, -1, -1, -1, -1 },
1573 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, in rockchip_get_drive_perpin() argument
1576 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_drive_perpin()
1577 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_drive_perpin()
1582 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_get_drive_perpin()
1584 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_drive_perpin()
1596 * drive-strength offset is special, as it is in rockchip_get_drive_perpin()
1620 bit -= 16; in rockchip_get_drive_perpin()
1623 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", in rockchip_get_drive_perpin()
1625 return -EINVAL; in rockchip_get_drive_perpin()
1635 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", in rockchip_get_drive_perpin()
1637 return -EINVAL; in rockchip_get_drive_perpin()
1645 data &= (1 << rmask_bits) - 1; in rockchip_get_drive_perpin()
1650 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, in rockchip_set_drive_perpin() argument
1653 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_drive_perpin()
1654 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_drive_perpin()
1659 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_set_drive_perpin()
1661 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", in rockchip_set_drive_perpin()
1662 bank->bank_num, pin_num, strength); in rockchip_set_drive_perpin()
1664 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_drive_perpin()
1665 if (ctrl->type == RK3568) { in rockchip_set_drive_perpin()
1667 ret = (1 << (strength + 1)) - 1; in rockchip_set_drive_perpin()
1671 ret = -EINVAL; in rockchip_set_drive_perpin()
1683 dev_err(info->dev, "unsupported driver strength %d\n", in rockchip_set_drive_perpin()
1698 * drive-strength offset is special, as it is spread in rockchip_set_drive_perpin()
1720 bit -= 16; in rockchip_set_drive_perpin()
1723 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", in rockchip_set_drive_perpin()
1725 return -EINVAL; in rockchip_set_drive_perpin()
1734 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", in rockchip_set_drive_perpin()
1736 return -EINVAL; in rockchip_set_drive_perpin()
1741 data = ((1 << rmask_bits) - 1) << (bit + 16); in rockchip_set_drive_perpin()
1765 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) in rockchip_get_pull() argument
1767 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_pull()
1768 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_pull()
1775 if (ctrl->type == RK3066B) in rockchip_get_pull()
1778 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_pull()
1784 switch (ctrl->type) { in rockchip_get_pull()
1797 pull_type = bank->pull_type[pin_num / 8]; in rockchip_get_pull()
1799 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; in rockchip_get_pull()
1803 dev_err(info->dev, "unsupported pinctrl type\n"); in rockchip_get_pull()
1804 return -EINVAL; in rockchip_get_pull()
1808 static int rockchip_set_pull(struct rockchip_pin_bank *bank, in rockchip_set_pull() argument
1811 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_pull()
1812 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_pull()
1818 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", in rockchip_set_pull()
1819 bank->bank_num, pin_num, pull); in rockchip_set_pull()
1822 if (ctrl->type == RK3066B) in rockchip_set_pull()
1823 return pull ? -EINVAL : 0; in rockchip_set_pull()
1825 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_pull()
1827 switch (ctrl->type) { in rockchip_set_pull()
1843 pull_type = bank->pull_type[pin_num / 8]; in rockchip_set_pull()
1844 ret = -EINVAL; in rockchip_set_pull()
1853 * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6, in rockchip_set_pull()
1856 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { in rockchip_set_pull()
1862 dev_err(info->dev, "unsupported pull setting %d\n", in rockchip_set_pull()
1868 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); in rockchip_set_pull()
1875 dev_err(info->dev, "unsupported pinctrl type\n"); in rockchip_set_pull()
1876 return -EINVAL; in rockchip_set_pull()
1887 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, in rk3328_calc_schmitt_reg_and_bit() argument
1892 struct rockchip_pinctrl *info = bank->drvdata; in rk3328_calc_schmitt_reg_and_bit()
1894 *regmap = info->regmap_base; in rk3328_calc_schmitt_reg_and_bit()
1897 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; in rk3328_calc_schmitt_reg_and_bit()
1910 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, in rk3568_calc_schmitt_reg_and_bit() argument
1915 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_schmitt_reg_and_bit()
1917 if (bank->bank_num == 0) { in rk3568_calc_schmitt_reg_and_bit()
1918 *regmap = info->regmap_pmu; in rk3568_calc_schmitt_reg_and_bit()
1921 *regmap = info->regmap_base; in rk3568_calc_schmitt_reg_and_bit()
1923 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; in rk3568_calc_schmitt_reg_and_bit()
1933 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) in rockchip_get_schmitt() argument
1935 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_schmitt()
1936 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_schmitt()
1942 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_schmitt()
1951 switch (ctrl->type) { in rockchip_get_schmitt()
1953 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); in rockchip_get_schmitt()
1961 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, in rockchip_set_schmitt() argument
1964 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_schmitt()
1965 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_schmitt()
1971 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", in rockchip_set_schmitt()
1972 bank->bank_num, pin_num, enable); in rockchip_set_schmitt()
1974 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_schmitt()
1979 switch (ctrl->type) { in rockchip_set_schmitt()
1981 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); in rockchip_set_schmitt()
2002 return info->nfunctions; in rockchip_pmx_get_funcs_count()
2010 return info->functions[selector].name; in rockchip_pmx_get_func_name()
2019 *groups = info->functions[selector].groups; in rockchip_pmx_get_groups()
2020 *num_groups = info->functions[selector].ngroups; in rockchip_pmx_get_groups()
2029 const unsigned int *pins = info->groups[group].pins; in rockchip_pmx_set()
2030 const struct rockchip_pin_config *data = info->groups[group].data; in rockchip_pmx_set()
2031 struct rockchip_pin_bank *bank; in rockchip_pmx_set() local
2034 dev_dbg(info->dev, "enable function %s group %s\n", in rockchip_pmx_set()
2035 info->functions[selector].name, info->groups[group].name); in rockchip_pmx_set()
2041 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { in rockchip_pmx_set()
2042 bank = pin_to_bank(info, pins[cnt]); in rockchip_pmx_set()
2043 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, in rockchip_pmx_set()
2051 for (cnt--; cnt >= 0; cnt--) in rockchip_pmx_set()
2052 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); in rockchip_pmx_set()
2074 switch (ctrl->type) { in rockchip_pinconf_pull_valid()
2095 static int rockchip_pinconf_defer_output(struct rockchip_pin_bank *bank, in rockchip_pinconf_defer_output() argument
2102 return -ENOMEM; in rockchip_pinconf_defer_output()
2104 cfg->pin = pin; in rockchip_pinconf_defer_output()
2105 cfg->arg = arg; in rockchip_pinconf_defer_output()
2107 list_add_tail(&cfg->head, &bank->deferred_output); in rockchip_pinconf_defer_output()
2117 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); in rockchip_pinconf_set() local
2118 struct gpio_chip *gpio = &bank->gpio_chip; in rockchip_pinconf_set()
2130 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2139 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) in rockchip_pinconf_set()
2140 return -ENOTSUPP; in rockchip_pinconf_set()
2143 return -EINVAL; in rockchip_pinconf_set()
2145 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2151 rc = rockchip_set_mux(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2154 return -EINVAL; in rockchip_pinconf_set()
2158 * The lock makes sure that either gpio-probe has completed in rockchip_pinconf_set()
2161 mutex_lock(&bank->deferred_lock); in rockchip_pinconf_set()
2162 if (!gpio || !gpio->direction_output) { in rockchip_pinconf_set()
2163 rc = rockchip_pinconf_defer_output(bank, pin - bank->pin_base, arg); in rockchip_pinconf_set()
2164 mutex_unlock(&bank->deferred_lock); in rockchip_pinconf_set()
2170 mutex_unlock(&bank->deferred_lock); in rockchip_pinconf_set()
2172 rc = gpio->direction_output(gpio, pin - bank->pin_base, in rockchip_pinconf_set()
2178 /* rk3288 is the first with per-pin drive-strength */ in rockchip_pinconf_set()
2179 if (!info->ctrl->drv_calc_reg) in rockchip_pinconf_set()
2180 return -ENOTSUPP; in rockchip_pinconf_set()
2182 rc = rockchip_set_drive_perpin(bank, in rockchip_pinconf_set()
2183 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2188 if (!info->ctrl->schmitt_calc_reg) in rockchip_pinconf_set()
2189 return -ENOTSUPP; in rockchip_pinconf_set()
2191 rc = rockchip_set_schmitt(bank, in rockchip_pinconf_set()
2192 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2197 return -ENOTSUPP; in rockchip_pinconf_set()
2210 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); in rockchip_pinconf_get() local
2211 struct gpio_chip *gpio = &bank->gpio_chip; in rockchip_pinconf_get()
2218 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
2219 return -EINVAL; in rockchip_pinconf_get()
2227 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) in rockchip_pinconf_get()
2228 return -ENOTSUPP; in rockchip_pinconf_get()
2230 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
2231 return -EINVAL; in rockchip_pinconf_get()
2236 rc = rockchip_get_mux(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2238 return -EINVAL; in rockchip_pinconf_get()
2240 if (!gpio || !gpio->get) { in rockchip_pinconf_get()
2245 rc = gpio->get(gpio, pin - bank->pin_base); in rockchip_pinconf_get()
2252 /* rk3288 is the first with per-pin drive-strength */ in rockchip_pinconf_get()
2253 if (!info->ctrl->drv_calc_reg) in rockchip_pinconf_get()
2254 return -ENOTSUPP; in rockchip_pinconf_get()
2256 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2263 if (!info->ctrl->schmitt_calc_reg) in rockchip_pinconf_get()
2264 return -ENOTSUPP; in rockchip_pinconf_get()
2266 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2273 return -ENOTSUPP; in rockchip_pinconf_get()
2289 { .compatible = "rockchip,gpio-bank" },
2290 { .compatible = "rockchip,rk3188-gpio-bank0" },
2303 info->nfunctions++; in rockchip_pinctrl_child_count()
2304 info->ngroups += of_get_child_count(child); in rockchip_pinctrl_child_count()
2313 struct rockchip_pin_bank *bank; in rockchip_pinctrl_parse_groups() local
2320 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); in rockchip_pinctrl_parse_groups()
2323 grp->name = np->name; in rockchip_pinctrl_parse_groups()
2326 * the binding format is rockchip,pins = <bank pin mux CONFIG>, in rockchip_pinctrl_parse_groups()
2333 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); in rockchip_pinctrl_parse_groups()
2334 return -EINVAL; in rockchip_pinctrl_parse_groups()
2337 grp->npins = size / 4; in rockchip_pinctrl_parse_groups()
2339 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), in rockchip_pinctrl_parse_groups()
2341 grp->data = devm_kcalloc(info->dev, in rockchip_pinctrl_parse_groups()
2342 grp->npins, in rockchip_pinctrl_parse_groups()
2345 if (!grp->pins || !grp->data) in rockchip_pinctrl_parse_groups()
2346 return -ENOMEM; in rockchip_pinctrl_parse_groups()
2353 bank = bank_num_to_bank(info, num); in rockchip_pinctrl_parse_groups()
2354 if (IS_ERR(bank)) in rockchip_pinctrl_parse_groups()
2355 return PTR_ERR(bank); in rockchip_pinctrl_parse_groups()
2357 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
2358 grp->data[j].func = be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
2362 return -EINVAL; in rockchip_pinctrl_parse_groups()
2366 &grp->data[j].configs, &grp->data[j].nconfigs); in rockchip_pinctrl_parse_groups()
2385 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); in rockchip_pinctrl_parse_functions()
2387 func = &info->functions[index]; in rockchip_pinctrl_parse_functions()
2390 func->name = np->name; in rockchip_pinctrl_parse_functions()
2391 func->ngroups = of_get_child_count(np); in rockchip_pinctrl_parse_functions()
2392 if (func->ngroups <= 0) in rockchip_pinctrl_parse_functions()
2395 func->groups = devm_kcalloc(info->dev, in rockchip_pinctrl_parse_functions()
2396 func->ngroups, sizeof(char *), GFP_KERNEL); in rockchip_pinctrl_parse_functions()
2397 if (!func->groups) in rockchip_pinctrl_parse_functions()
2398 return -ENOMEM; in rockchip_pinctrl_parse_functions()
2401 func->groups[i] = child->name; in rockchip_pinctrl_parse_functions()
2402 grp = &info->groups[grp_index++]; in rockchip_pinctrl_parse_functions()
2416 struct device *dev = &pdev->dev; in rockchip_pinctrl_parse_dt()
2417 struct device_node *np = dev->of_node; in rockchip_pinctrl_parse_dt()
2424 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); in rockchip_pinctrl_parse_dt()
2425 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); in rockchip_pinctrl_parse_dt()
2427 info->functions = devm_kcalloc(dev, in rockchip_pinctrl_parse_dt()
2428 info->nfunctions, in rockchip_pinctrl_parse_dt()
2431 if (!info->functions) in rockchip_pinctrl_parse_dt()
2432 return -ENOMEM; in rockchip_pinctrl_parse_dt()
2434 info->groups = devm_kcalloc(dev, in rockchip_pinctrl_parse_dt()
2435 info->ngroups, in rockchip_pinctrl_parse_dt()
2438 if (!info->groups) in rockchip_pinctrl_parse_dt()
2439 return -ENOMEM; in rockchip_pinctrl_parse_dt()
2449 dev_err(&pdev->dev, "failed to parse function\n"); in rockchip_pinctrl_parse_dt()
2461 struct pinctrl_desc *ctrldesc = &info->pctl; in rockchip_pinctrl_register()
2464 int pin, bank, ret; in rockchip_pinctrl_register() local
2467 ctrldesc->name = "rockchip-pinctrl"; in rockchip_pinctrl_register()
2468 ctrldesc->owner = THIS_MODULE; in rockchip_pinctrl_register()
2469 ctrldesc->pctlops = &rockchip_pctrl_ops; in rockchip_pinctrl_register()
2470 ctrldesc->pmxops = &rockchip_pmx_ops; in rockchip_pinctrl_register()
2471 ctrldesc->confops = &rockchip_pinconf_ops; in rockchip_pinctrl_register()
2473 pindesc = devm_kcalloc(&pdev->dev, in rockchip_pinctrl_register()
2474 info->ctrl->nr_pins, sizeof(*pindesc), in rockchip_pinctrl_register()
2477 return -ENOMEM; in rockchip_pinctrl_register()
2479 ctrldesc->pins = pindesc; in rockchip_pinctrl_register()
2480 ctrldesc->npins = info->ctrl->nr_pins; in rockchip_pinctrl_register()
2483 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { in rockchip_pinctrl_register()
2484 pin_bank = &info->ctrl->pin_banks[bank]; in rockchip_pinctrl_register()
2485 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { in rockchip_pinctrl_register()
2486 pdesc->number = k; in rockchip_pinctrl_register()
2487 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", in rockchip_pinctrl_register()
2488 pin_bank->name, pin); in rockchip_pinctrl_register()
2492 INIT_LIST_HEAD(&pin_bank->deferred_output); in rockchip_pinctrl_register()
2493 mutex_init(&pin_bank->deferred_lock); in rockchip_pinctrl_register()
2500 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); in rockchip_pinctrl_register()
2501 if (IS_ERR(info->pctl_dev)) { in rockchip_pinctrl_register()
2502 dev_err(&pdev->dev, "could not register pinctrl driver\n"); in rockchip_pinctrl_register()
2503 return PTR_ERR(info->pctl_dev); in rockchip_pinctrl_register()
2517 struct device_node *node = pdev->dev.of_node; in rockchip_pinctrl_get_soc_data()
2519 struct rockchip_pin_bank *bank; in rockchip_pinctrl_get_soc_data() local
2523 ctrl = (struct rockchip_pin_ctrl *)match->data; in rockchip_pinctrl_get_soc_data()
2525 grf_offs = ctrl->grf_mux_offset; in rockchip_pinctrl_get_soc_data()
2526 pmu_offs = ctrl->pmu_mux_offset; in rockchip_pinctrl_get_soc_data()
2527 drv_pmu_offs = ctrl->pmu_drv_offset; in rockchip_pinctrl_get_soc_data()
2528 drv_grf_offs = ctrl->grf_drv_offset; in rockchip_pinctrl_get_soc_data()
2529 bank = ctrl->pin_banks; in rockchip_pinctrl_get_soc_data()
2530 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
2533 raw_spin_lock_init(&bank->slock); in rockchip_pinctrl_get_soc_data()
2534 bank->drvdata = d; in rockchip_pinctrl_get_soc_data()
2535 bank->pin_base = ctrl->nr_pins; in rockchip_pinctrl_get_soc_data()
2536 ctrl->nr_pins += bank->nr_pins; in rockchip_pinctrl_get_soc_data()
2540 struct rockchip_iomux *iom = &bank->iomux[j]; in rockchip_pinctrl_get_soc_data()
2541 struct rockchip_drv *drv = &bank->drv[j]; in rockchip_pinctrl_get_soc_data()
2544 if (bank_pins >= bank->nr_pins) in rockchip_pinctrl_get_soc_data()
2548 if (iom->offset >= 0) { in rockchip_pinctrl_get_soc_data()
2549 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
2550 pmu_offs = iom->offset; in rockchip_pinctrl_get_soc_data()
2552 grf_offs = iom->offset; in rockchip_pinctrl_get_soc_data()
2554 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? in rockchip_pinctrl_get_soc_data()
2559 if (drv->offset >= 0) { in rockchip_pinctrl_get_soc_data()
2560 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
2561 drv_pmu_offs = drv->offset; in rockchip_pinctrl_get_soc_data()
2563 drv_grf_offs = drv->offset; in rockchip_pinctrl_get_soc_data()
2565 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? in rockchip_pinctrl_get_soc_data()
2569 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", in rockchip_pinctrl_get_soc_data()
2570 i, j, iom->offset, drv->offset); in rockchip_pinctrl_get_soc_data()
2576 inc = (iom->type & (IOMUX_WIDTH_4BIT | in rockchip_pinctrl_get_soc_data()
2579 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
2586 * 3bit drive-strenth'es are spread over two registers. in rockchip_pinctrl_get_soc_data()
2588 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rockchip_pinctrl_get_soc_data()
2589 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) in rockchip_pinctrl_get_soc_data()
2594 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
2602 /* calculate the per-bank recalced_mask */ in rockchip_pinctrl_get_soc_data()
2603 for (j = 0; j < ctrl->niomux_recalced; j++) { in rockchip_pinctrl_get_soc_data()
2606 if (ctrl->iomux_recalced[j].num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
2607 pin = ctrl->iomux_recalced[j].pin; in rockchip_pinctrl_get_soc_data()
2608 bank->recalced_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
2612 /* calculate the per-bank route_mask */ in rockchip_pinctrl_get_soc_data()
2613 for (j = 0; j < ctrl->niomux_routes; j++) { in rockchip_pinctrl_get_soc_data()
2616 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
2617 pin = ctrl->iomux_routes[j].pin; in rockchip_pinctrl_get_soc_data()
2618 bank->route_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
2634 int ret = pinctrl_force_sleep(info->pctl_dev); in rockchip_pinctrl_suspend()
2643 if (info->ctrl->type == RK3288) { in rockchip_pinctrl_suspend()
2644 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, in rockchip_pinctrl_suspend()
2647 pinctrl_force_default(info->pctl_dev); in rockchip_pinctrl_suspend()
2660 if (info->ctrl->type == RK3288) { in rockchip_pinctrl_resume()
2661 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, in rockchip_pinctrl_resume()
2668 return pinctrl_force_default(info->pctl_dev); in rockchip_pinctrl_resume()
2677 struct device *dev = &pdev->dev; in rockchip_pinctrl_probe()
2679 struct device_node *np = pdev->dev.of_node, *node; in rockchip_pinctrl_probe()
2684 if (!dev->of_node) { in rockchip_pinctrl_probe()
2686 return -ENODEV; in rockchip_pinctrl_probe()
2691 return -ENOMEM; in rockchip_pinctrl_probe()
2693 info->dev = dev; in rockchip_pinctrl_probe()
2698 return -EINVAL; in rockchip_pinctrl_probe()
2700 info->ctrl = ctrl; in rockchip_pinctrl_probe()
2704 info->regmap_base = syscon_node_to_regmap(node); in rockchip_pinctrl_probe()
2705 if (IS_ERR(info->regmap_base)) in rockchip_pinctrl_probe()
2706 return PTR_ERR(info->regmap_base); in rockchip_pinctrl_probe()
2709 base = devm_ioremap_resource(&pdev->dev, res); in rockchip_pinctrl_probe()
2713 rockchip_regmap_config.max_register = resource_size(res) - 4; in rockchip_pinctrl_probe()
2714 rockchip_regmap_config.name = "rockchip,pinctrl"; in rockchip_pinctrl_probe()
2715 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, in rockchip_pinctrl_probe()
2718 /* to check for the old dt-bindings */ in rockchip_pinctrl_probe()
2719 info->reg_size = resource_size(res); in rockchip_pinctrl_probe()
2722 if (ctrl->type == RK3188 && info->reg_size < 0x200) { in rockchip_pinctrl_probe()
2724 base = devm_ioremap_resource(&pdev->dev, res); in rockchip_pinctrl_probe()
2729 resource_size(res) - 4; in rockchip_pinctrl_probe()
2730 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; in rockchip_pinctrl_probe()
2731 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, in rockchip_pinctrl_probe()
2740 info->regmap_pmu = syscon_node_to_regmap(node); in rockchip_pinctrl_probe()
2741 if (IS_ERR(info->regmap_pmu)) in rockchip_pinctrl_probe()
2742 return PTR_ERR(info->regmap_pmu); in rockchip_pinctrl_probe()
2753 dev_err(&pdev->dev, "failed to register gpio device\n"); in rockchip_pinctrl_probe()
2763 struct rockchip_pin_bank *bank; in rockchip_pinctrl_remove() local
2767 of_platform_depopulate(&pdev->dev); in rockchip_pinctrl_remove()
2769 for (i = 0; i < info->ctrl->nr_banks; i++) { in rockchip_pinctrl_remove()
2770 bank = &info->ctrl->pin_banks[i]; in rockchip_pinctrl_remove()
2772 mutex_lock(&bank->deferred_lock); in rockchip_pinctrl_remove()
2773 while (!list_empty(&bank->deferred_output)) { in rockchip_pinctrl_remove()
2774 cfg = list_first_entry(&bank->deferred_output, in rockchip_pinctrl_remove()
2776 list_del(&cfg->head); in rockchip_pinctrl_remove()
2779 mutex_unlock(&bank->deferred_lock); in rockchip_pinctrl_remove()
2811 .label = "PX30-GPIO",
2835 .label = "RV1108-GPIO",
2856 .label = "RK2928-GPIO",
2871 .label = "RK3036-GPIO",
2889 .label = "RK3066a-GPIO",
2905 .label = "RK3066b-GPIO",
2920 .label = "RK3128-GPIO",
2940 .label = "RK3188-GPIO",
2958 .label = "RK3228-GPIO",
3002 .label = "RK3288-GPIO",
3038 .label = "RK3308-GPIO",
3067 .label = "RK3328-GPIO",
3093 .label = "RK3368-GPIO",
3113 -1,
3114 -1,
3157 .label = "RK3399-GPIO",
3195 .label = "RK3568-GPIO",
3209 { .compatible = "rockchip,px30-pinctrl",
3211 { .compatible = "rockchip,rv1108-pinctrl",
3213 { .compatible = "rockchip,rk2928-pinctrl",
3215 { .compatible = "rockchip,rk3036-pinctrl",
3217 { .compatible = "rockchip,rk3066a-pinctrl",
3219 { .compatible = "rockchip,rk3066b-pinctrl",
3221 { .compatible = "rockchip,rk3128-pinctrl",
3223 { .compatible = "rockchip,rk3188-pinctrl",
3225 { .compatible = "rockchip,rk3228-pinctrl",
3227 { .compatible = "rockchip,rk3288-pinctrl",
3229 { .compatible = "rockchip,rk3308-pinctrl",
3231 { .compatible = "rockchip,rk3328-pinctrl",
3233 { .compatible = "rockchip,rk3368-pinctrl",
3235 { .compatible = "rockchip,rk3399-pinctrl",
3237 { .compatible = "rockchip,rk3568-pinctrl",
3246 .name = "rockchip-pinctrl",
3266 MODULE_ALIAS("platform:pinctrl-rockchip");