1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Pinctrl driver for Rockchip SoCs
4 *
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
7 *
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * https://www.linaro.org
13 *
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/io.h>
22 #include <linux/bitops.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/of_address.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/irqchip/chained_irq.h>
33 #include <linux/clk.h>
34 #include <linux/regmap.h>
35 #include <linux/mfd/syscon.h>
36 #include <dt-bindings/pinctrl/rockchip.h>
37
38 #include "core.h"
39 #include "pinconf.h"
40 #include "pinctrl-rockchip.h"
41
42 /**
43 * Generate a bitmask for setting a value (v) with a write mask bit in hiword
44 * register 31:16 area.
45 */
46 #define WRITE_MASK_VAL(h, l, v) \
47 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
48
49 /*
50 * Encode variants of iomux registers into a type variable
51 */
52 #define IOMUX_GPIO_ONLY BIT(0)
53 #define IOMUX_WIDTH_4BIT BIT(1)
54 #define IOMUX_SOURCE_PMU BIT(2)
55 #define IOMUX_UNROUTED BIT(3)
56 #define IOMUX_WIDTH_3BIT BIT(4)
57 #define IOMUX_WIDTH_2BIT BIT(5)
58
59 #define PIN_BANK(id, pins, label) \
60 { \
61 .bank_num = id, \
62 .nr_pins = pins, \
63 .name = label, \
64 .iomux = { \
65 { .offset = -1 }, \
66 { .offset = -1 }, \
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 }, \
70 }
71
72 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
73 { \
74 .bank_num = id, \
75 .nr_pins = pins, \
76 .name = label, \
77 .iomux = { \
78 { .type = iom0, .offset = -1 }, \
79 { .type = iom1, .offset = -1 }, \
80 { .type = iom2, .offset = -1 }, \
81 { .type = iom3, .offset = -1 }, \
82 }, \
83 }
84
85 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
86 { \
87 .bank_num = id, \
88 .nr_pins = pins, \
89 .name = label, \
90 .iomux = { \
91 { .offset = -1 }, \
92 { .offset = -1 }, \
93 { .offset = -1 }, \
94 { .offset = -1 }, \
95 }, \
96 .drv = { \
97 { .drv_type = type0, .offset = -1 }, \
98 { .drv_type = type1, .offset = -1 }, \
99 { .drv_type = type2, .offset = -1 }, \
100 { .drv_type = type3, .offset = -1 }, \
101 }, \
102 }
103
104 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
105 drv2, drv3, pull0, pull1, \
106 pull2, pull3) \
107 { \
108 .bank_num = id, \
109 .nr_pins = pins, \
110 .name = label, \
111 .iomux = { \
112 { .offset = -1 }, \
113 { .offset = -1 }, \
114 { .offset = -1 }, \
115 { .offset = -1 }, \
116 }, \
117 .drv = { \
118 { .drv_type = drv0, .offset = -1 }, \
119 { .drv_type = drv1, .offset = -1 }, \
120 { .drv_type = drv2, .offset = -1 }, \
121 { .drv_type = drv3, .offset = -1 }, \
122 }, \
123 .pull_type[0] = pull0, \
124 .pull_type[1] = pull1, \
125 .pull_type[2] = pull2, \
126 .pull_type[3] = pull3, \
127 }
128
129 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
130 iom2, iom3, drv0, drv1, drv2, \
131 drv3, offset0, offset1, \
132 offset2, offset3) \
133 { \
134 .bank_num = id, \
135 .nr_pins = pins, \
136 .name = label, \
137 .iomux = { \
138 { .type = iom0, .offset = -1 }, \
139 { .type = iom1, .offset = -1 }, \
140 { .type = iom2, .offset = -1 }, \
141 { .type = iom3, .offset = -1 }, \
142 }, \
143 .drv = { \
144 { .drv_type = drv0, .offset = offset0 }, \
145 { .drv_type = drv1, .offset = offset1 }, \
146 { .drv_type = drv2, .offset = offset2 }, \
147 { .drv_type = drv3, .offset = offset3 }, \
148 }, \
149 }
150
151 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
152 label, iom0, iom1, iom2, \
153 iom3, drv0, drv1, drv2, \
154 drv3, offset0, offset1, \
155 offset2, offset3, pull0, \
156 pull1, pull2, pull3) \
157 { \
158 .bank_num = id, \
159 .nr_pins = pins, \
160 .name = label, \
161 .iomux = { \
162 { .type = iom0, .offset = -1 }, \
163 { .type = iom1, .offset = -1 }, \
164 { .type = iom2, .offset = -1 }, \
165 { .type = iom3, .offset = -1 }, \
166 }, \
167 .drv = { \
168 { .drv_type = drv0, .offset = offset0 }, \
169 { .drv_type = drv1, .offset = offset1 }, \
170 { .drv_type = drv2, .offset = offset2 }, \
171 { .drv_type = drv3, .offset = offset3 }, \
172 }, \
173 .pull_type[0] = pull0, \
174 .pull_type[1] = pull1, \
175 .pull_type[2] = pull2, \
176 .pull_type[3] = pull3, \
177 }
178
179 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
180 { \
181 .bank_num = ID, \
182 .pin = PIN, \
183 .func = FUNC, \
184 .route_offset = REG, \
185 .route_val = VAL, \
186 .route_location = FLAG, \
187 }
188
189 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \
190 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
191
192 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \
193 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
194
195 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
196 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
197
198 static struct regmap_config rockchip_regmap_config = {
199 .reg_bits = 32,
200 .val_bits = 32,
201 .reg_stride = 4,
202 };
203
pinctrl_name_to_group(const struct rockchip_pinctrl * info,const char * name)204 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
205 const struct rockchip_pinctrl *info,
206 const char *name)
207 {
208 int i;
209
210 for (i = 0; i < info->ngroups; i++) {
211 if (!strcmp(info->groups[i].name, name))
212 return &info->groups[i];
213 }
214
215 return NULL;
216 }
217
218 /*
219 * given a pin number that is local to a pin controller, find out the pin bank
220 * and the register base of the pin bank.
221 */
pin_to_bank(struct rockchip_pinctrl * info,unsigned pin)222 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
223 unsigned pin)
224 {
225 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
226
227 while (pin >= (b->pin_base + b->nr_pins))
228 b++;
229
230 return b;
231 }
232
bank_num_to_bank(struct rockchip_pinctrl * info,unsigned num)233 static struct rockchip_pin_bank *bank_num_to_bank(
234 struct rockchip_pinctrl *info,
235 unsigned num)
236 {
237 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
238 int i;
239
240 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
241 if (b->bank_num == num)
242 return b;
243 }
244
245 return ERR_PTR(-EINVAL);
246 }
247
248 /*
249 * Pinctrl_ops handling
250 */
251
rockchip_get_groups_count(struct pinctrl_dev * pctldev)252 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
253 {
254 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
255
256 return info->ngroups;
257 }
258
rockchip_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)259 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
260 unsigned selector)
261 {
262 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
263
264 return info->groups[selector].name;
265 }
266
rockchip_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * npins)267 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
268 unsigned selector, const unsigned **pins,
269 unsigned *npins)
270 {
271 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
272
273 if (selector >= info->ngroups)
274 return -EINVAL;
275
276 *pins = info->groups[selector].pins;
277 *npins = info->groups[selector].npins;
278
279 return 0;
280 }
281
rockchip_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned * num_maps)282 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
283 struct device_node *np,
284 struct pinctrl_map **map, unsigned *num_maps)
285 {
286 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
287 const struct rockchip_pin_group *grp;
288 struct pinctrl_map *new_map;
289 struct device_node *parent;
290 int map_num = 1;
291 int i;
292
293 /*
294 * first find the group of this node and check if we need to create
295 * config maps for pins
296 */
297 grp = pinctrl_name_to_group(info, np->name);
298 if (!grp) {
299 dev_err(info->dev, "unable to find group for node %pOFn\n",
300 np);
301 return -EINVAL;
302 }
303
304 map_num += grp->npins;
305
306 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
307 if (!new_map)
308 return -ENOMEM;
309
310 *map = new_map;
311 *num_maps = map_num;
312
313 /* create mux map */
314 parent = of_get_parent(np);
315 if (!parent) {
316 kfree(new_map);
317 return -EINVAL;
318 }
319 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
320 new_map[0].data.mux.function = parent->name;
321 new_map[0].data.mux.group = np->name;
322 of_node_put(parent);
323
324 /* create config map */
325 new_map++;
326 for (i = 0; i < grp->npins; i++) {
327 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
328 new_map[i].data.configs.group_or_pin =
329 pin_get_name(pctldev, grp->pins[i]);
330 new_map[i].data.configs.configs = grp->data[i].configs;
331 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
332 }
333
334 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
335 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
336
337 return 0;
338 }
339
rockchip_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned num_maps)340 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
341 struct pinctrl_map *map, unsigned num_maps)
342 {
343 kfree(map);
344 }
345
346 static const struct pinctrl_ops rockchip_pctrl_ops = {
347 .get_groups_count = rockchip_get_groups_count,
348 .get_group_name = rockchip_get_group_name,
349 .get_group_pins = rockchip_get_group_pins,
350 .dt_node_to_map = rockchip_dt_node_to_map,
351 .dt_free_map = rockchip_dt_free_map,
352 };
353
354 /*
355 * Hardware access
356 */
357
358 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
359 {
360 .num = 1,
361 .pin = 0,
362 .reg = 0x418,
363 .bit = 0,
364 .mask = 0x3
365 }, {
366 .num = 1,
367 .pin = 1,
368 .reg = 0x418,
369 .bit = 2,
370 .mask = 0x3
371 }, {
372 .num = 1,
373 .pin = 2,
374 .reg = 0x418,
375 .bit = 4,
376 .mask = 0x3
377 }, {
378 .num = 1,
379 .pin = 3,
380 .reg = 0x418,
381 .bit = 6,
382 .mask = 0x3
383 }, {
384 .num = 1,
385 .pin = 4,
386 .reg = 0x418,
387 .bit = 8,
388 .mask = 0x3
389 }, {
390 .num = 1,
391 .pin = 5,
392 .reg = 0x418,
393 .bit = 10,
394 .mask = 0x3
395 }, {
396 .num = 1,
397 .pin = 6,
398 .reg = 0x418,
399 .bit = 12,
400 .mask = 0x3
401 }, {
402 .num = 1,
403 .pin = 7,
404 .reg = 0x418,
405 .bit = 14,
406 .mask = 0x3
407 }, {
408 .num = 1,
409 .pin = 8,
410 .reg = 0x41c,
411 .bit = 0,
412 .mask = 0x3
413 }, {
414 .num = 1,
415 .pin = 9,
416 .reg = 0x41c,
417 .bit = 2,
418 .mask = 0x3
419 },
420 };
421
422 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
423 {
424 .num = 2,
425 .pin = 20,
426 .reg = 0xe8,
427 .bit = 0,
428 .mask = 0x7
429 }, {
430 .num = 2,
431 .pin = 21,
432 .reg = 0xe8,
433 .bit = 4,
434 .mask = 0x7
435 }, {
436 .num = 2,
437 .pin = 22,
438 .reg = 0xe8,
439 .bit = 8,
440 .mask = 0x7
441 }, {
442 .num = 2,
443 .pin = 23,
444 .reg = 0xe8,
445 .bit = 12,
446 .mask = 0x7
447 }, {
448 .num = 2,
449 .pin = 24,
450 .reg = 0xd4,
451 .bit = 12,
452 .mask = 0x7
453 },
454 };
455
456 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
457 {
458 .num = 1,
459 .pin = 14,
460 .reg = 0x28,
461 .bit = 12,
462 .mask = 0xf
463 }, {
464 .num = 1,
465 .pin = 15,
466 .reg = 0x2c,
467 .bit = 0,
468 .mask = 0x3
469 }, {
470 .num = 1,
471 .pin = 18,
472 .reg = 0x30,
473 .bit = 4,
474 .mask = 0xf
475 }, {
476 .num = 1,
477 .pin = 19,
478 .reg = 0x30,
479 .bit = 8,
480 .mask = 0xf
481 }, {
482 .num = 1,
483 .pin = 20,
484 .reg = 0x30,
485 .bit = 12,
486 .mask = 0xf
487 }, {
488 .num = 1,
489 .pin = 21,
490 .reg = 0x34,
491 .bit = 0,
492 .mask = 0xf
493 }, {
494 .num = 1,
495 .pin = 22,
496 .reg = 0x34,
497 .bit = 4,
498 .mask = 0xf
499 }, {
500 .num = 1,
501 .pin = 23,
502 .reg = 0x34,
503 .bit = 8,
504 .mask = 0xf
505 }, {
506 .num = 3,
507 .pin = 12,
508 .reg = 0x68,
509 .bit = 8,
510 .mask = 0xf
511 }, {
512 .num = 3,
513 .pin = 13,
514 .reg = 0x68,
515 .bit = 12,
516 .mask = 0xf
517 }, {
518 .num = 2,
519 .pin = 2,
520 .reg = 0x608,
521 .bit = 0,
522 .mask = 0x7
523 }, {
524 .num = 2,
525 .pin = 3,
526 .reg = 0x608,
527 .bit = 4,
528 .mask = 0x7
529 }, {
530 .num = 2,
531 .pin = 16,
532 .reg = 0x610,
533 .bit = 8,
534 .mask = 0x7
535 }, {
536 .num = 3,
537 .pin = 10,
538 .reg = 0x610,
539 .bit = 0,
540 .mask = 0x7
541 }, {
542 .num = 3,
543 .pin = 11,
544 .reg = 0x610,
545 .bit = 4,
546 .mask = 0x7
547 },
548 };
549
550 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
551 {
552 .num = 2,
553 .pin = 12,
554 .reg = 0x24,
555 .bit = 8,
556 .mask = 0x3
557 }, {
558 .num = 2,
559 .pin = 15,
560 .reg = 0x28,
561 .bit = 0,
562 .mask = 0x7
563 }, {
564 .num = 2,
565 .pin = 23,
566 .reg = 0x30,
567 .bit = 14,
568 .mask = 0x3
569 },
570 };
571
rockchip_get_recalced_mux(struct rockchip_pin_bank * bank,int pin,int * reg,u8 * bit,int * mask)572 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
573 int *reg, u8 *bit, int *mask)
574 {
575 struct rockchip_pinctrl *info = bank->drvdata;
576 struct rockchip_pin_ctrl *ctrl = info->ctrl;
577 struct rockchip_mux_recalced_data *data;
578 int i;
579
580 for (i = 0; i < ctrl->niomux_recalced; i++) {
581 data = &ctrl->iomux_recalced[i];
582 if (data->num == bank->bank_num &&
583 data->pin == pin)
584 break;
585 }
586
587 if (i >= ctrl->niomux_recalced)
588 return;
589
590 *reg = data->reg;
591 *mask = data->mask;
592 *bit = data->bit;
593 }
594
595 static struct rockchip_mux_route_data px30_mux_route_data[] = {
596 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
597 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
598 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
599 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
600 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
601 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
602 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
603 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
604 };
605
606 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
607 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
608 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
609 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
610 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
611 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
612 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
613 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
614 };
615
616 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
617 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
618 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
619 };
620
621 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
622 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
623 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
624 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
625 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
626 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
627 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
628 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
629 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
630 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
631 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
632 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
633 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
634 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
635 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
636 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
637 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
638 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
639 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
640 };
641
642 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
643 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
644 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
645 };
646
647 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
648 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
649 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
650 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
651 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
652 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
653 RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
654 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
655 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
656 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
657 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
658 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
659 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
660 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
661 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
662 RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
663 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
664 RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
665 RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
666 RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
667 RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
668 RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
669 RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
670 RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
671 RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
672 RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
673 RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
674 };
675
676 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
677 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
678 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
679 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
680 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
681 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
682 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
683 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
684 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
685 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
686 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
687 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
688 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
689 };
690
691 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
692 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
693 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
694 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
695 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
696 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
697 };
698
699 static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
700 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
701 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
702 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
703 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
704 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
705 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
706 RK_MUXROUTE_PMU(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
707 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
708 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
709 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
710 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
711 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
712 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
713 RK_MUXROUTE_PMU(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
714 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
715 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
716 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
717 RK_MUXROUTE_PMU(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
718 RK_MUXROUTE_PMU(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
719 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
720 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
721 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
722 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
723 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
724 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
725 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
726 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
727 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
728 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
729 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
730 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
731 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
732 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
733 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
734 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
735 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
736 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
737 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
738 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
739 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
740 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
741 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
742 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
743 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
744 RK_MUXROUTE_PMU(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
745 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
746 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
747 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
748 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
749 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
750 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
751 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
752 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
753 RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
754 RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
755 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
756 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
757 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
758 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
759 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
760 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
761 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
762 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
763 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
764 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
765 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
766 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
767 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
768 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
769 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
770 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
771 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
772 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
773 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
774 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
775 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
776 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
777 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
778 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
779 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
780 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
781 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
782 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
783 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
784 RK_MUXROUTE_PMU(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
785 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
786 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
787 RK_MUXROUTE_PMU(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
788 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
789 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
790 RK_MUXROUTE_PMU(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
791 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
792 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
793 };
794
rockchip_get_mux_route(struct rockchip_pin_bank * bank,int pin,int mux,u32 * loc,u32 * reg,u32 * value)795 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
796 int mux, u32 *loc, u32 *reg, u32 *value)
797 {
798 struct rockchip_pinctrl *info = bank->drvdata;
799 struct rockchip_pin_ctrl *ctrl = info->ctrl;
800 struct rockchip_mux_route_data *data;
801 int i;
802
803 for (i = 0; i < ctrl->niomux_routes; i++) {
804 data = &ctrl->iomux_routes[i];
805 if ((data->bank_num == bank->bank_num) &&
806 (data->pin == pin) && (data->func == mux))
807 break;
808 }
809
810 if (i >= ctrl->niomux_routes)
811 return false;
812
813 *loc = data->route_location;
814 *reg = data->route_offset;
815 *value = data->route_val;
816
817 return true;
818 }
819
rockchip_get_mux(struct rockchip_pin_bank * bank,int pin)820 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
821 {
822 struct rockchip_pinctrl *info = bank->drvdata;
823 int iomux_num = (pin / 8);
824 struct regmap *regmap;
825 unsigned int val;
826 int reg, ret, mask, mux_type;
827 u8 bit;
828
829 if (iomux_num > 3)
830 return -EINVAL;
831
832 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
833 dev_err(info->dev, "pin %d is unrouted\n", pin);
834 return -EINVAL;
835 }
836
837 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
838 return RK_FUNC_GPIO;
839
840 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
841 ? info->regmap_pmu : info->regmap_base;
842
843 /* get basic quadrupel of mux registers and the correct reg inside */
844 mux_type = bank->iomux[iomux_num].type;
845 reg = bank->iomux[iomux_num].offset;
846 if (mux_type & IOMUX_WIDTH_4BIT) {
847 if ((pin % 8) >= 4)
848 reg += 0x4;
849 bit = (pin % 4) * 4;
850 mask = 0xf;
851 } else if (mux_type & IOMUX_WIDTH_3BIT) {
852 if ((pin % 8) >= 5)
853 reg += 0x4;
854 bit = (pin % 8 % 5) * 3;
855 mask = 0x7;
856 } else {
857 bit = (pin % 8) * 2;
858 mask = 0x3;
859 }
860
861 if (bank->recalced_mask & BIT(pin))
862 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
863
864 ret = regmap_read(regmap, reg, &val);
865 if (ret)
866 return ret;
867
868 return ((val >> bit) & mask);
869 }
870
rockchip_verify_mux(struct rockchip_pin_bank * bank,int pin,int mux)871 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
872 int pin, int mux)
873 {
874 struct rockchip_pinctrl *info = bank->drvdata;
875 int iomux_num = (pin / 8);
876
877 if (iomux_num > 3)
878 return -EINVAL;
879
880 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
881 dev_err(info->dev, "pin %d is unrouted\n", pin);
882 return -EINVAL;
883 }
884
885 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
886 if (mux != RK_FUNC_GPIO) {
887 dev_err(info->dev,
888 "pin %d only supports a gpio mux\n", pin);
889 return -ENOTSUPP;
890 }
891 }
892
893 return 0;
894 }
895
896 /*
897 * Set a new mux function for a pin.
898 *
899 * The register is divided into the upper and lower 16 bit. When changing
900 * a value, the previous register value is not read and changed. Instead
901 * it seems the changed bits are marked in the upper 16 bit, while the
902 * changed value gets set in the same offset in the lower 16 bit.
903 * All pin settings seem to be 2 bit wide in both the upper and lower
904 * parts.
905 * @bank: pin bank to change
906 * @pin: pin to change
907 * @mux: new mux function to set
908 */
rockchip_set_mux(struct rockchip_pin_bank * bank,int pin,int mux)909 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
910 {
911 struct rockchip_pinctrl *info = bank->drvdata;
912 int iomux_num = (pin / 8);
913 struct regmap *regmap;
914 int reg, ret, mask, mux_type;
915 u8 bit;
916 u32 data, rmask, route_location, route_reg, route_val;
917
918 ret = rockchip_verify_mux(bank, pin, mux);
919 if (ret < 0)
920 return ret;
921
922 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
923 return 0;
924
925 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
926 bank->bank_num, pin, mux);
927
928 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
929 ? info->regmap_pmu : info->regmap_base;
930
931 /* get basic quadrupel of mux registers and the correct reg inside */
932 mux_type = bank->iomux[iomux_num].type;
933 reg = bank->iomux[iomux_num].offset;
934 if (mux_type & IOMUX_WIDTH_4BIT) {
935 if ((pin % 8) >= 4)
936 reg += 0x4;
937 bit = (pin % 4) * 4;
938 mask = 0xf;
939 } else if (mux_type & IOMUX_WIDTH_3BIT) {
940 if ((pin % 8) >= 5)
941 reg += 0x4;
942 bit = (pin % 8 % 5) * 3;
943 mask = 0x7;
944 } else {
945 bit = (pin % 8) * 2;
946 mask = 0x3;
947 }
948
949 if (bank->recalced_mask & BIT(pin))
950 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
951
952 if (bank->route_mask & BIT(pin)) {
953 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
954 &route_reg, &route_val)) {
955 struct regmap *route_regmap = regmap;
956
957 /* handle special locations */
958 switch (route_location) {
959 case ROCKCHIP_ROUTE_PMU:
960 route_regmap = info->regmap_pmu;
961 break;
962 case ROCKCHIP_ROUTE_GRF:
963 route_regmap = info->regmap_base;
964 break;
965 }
966
967 ret = regmap_write(route_regmap, route_reg, route_val);
968 if (ret)
969 return ret;
970 }
971 }
972
973 data = (mask << (bit + 16));
974 rmask = data | (data >> 16);
975 data |= (mux & mask) << bit;
976 ret = regmap_update_bits(regmap, reg, rmask, data);
977
978 return ret;
979 }
980
981 #define PX30_PULL_PMU_OFFSET 0x10
982 #define PX30_PULL_GRF_OFFSET 0x60
983 #define PX30_PULL_BITS_PER_PIN 2
984 #define PX30_PULL_PINS_PER_REG 8
985 #define PX30_PULL_BANK_STRIDE 16
986
px30_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)987 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
988 int pin_num, struct regmap **regmap,
989 int *reg, u8 *bit)
990 {
991 struct rockchip_pinctrl *info = bank->drvdata;
992
993 /* The first 32 pins of the first bank are located in PMU */
994 if (bank->bank_num == 0) {
995 *regmap = info->regmap_pmu;
996 *reg = PX30_PULL_PMU_OFFSET;
997 } else {
998 *regmap = info->regmap_base;
999 *reg = PX30_PULL_GRF_OFFSET;
1000
1001 /* correct the offset, as we're starting with the 2nd bank */
1002 *reg -= 0x10;
1003 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1004 }
1005
1006 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1007 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1008 *bit *= PX30_PULL_BITS_PER_PIN;
1009 }
1010
1011 #define PX30_DRV_PMU_OFFSET 0x20
1012 #define PX30_DRV_GRF_OFFSET 0xf0
1013 #define PX30_DRV_BITS_PER_PIN 2
1014 #define PX30_DRV_PINS_PER_REG 8
1015 #define PX30_DRV_BANK_STRIDE 16
1016
px30_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1017 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1018 int pin_num, struct regmap **regmap,
1019 int *reg, u8 *bit)
1020 {
1021 struct rockchip_pinctrl *info = bank->drvdata;
1022
1023 /* The first 32 pins of the first bank are located in PMU */
1024 if (bank->bank_num == 0) {
1025 *regmap = info->regmap_pmu;
1026 *reg = PX30_DRV_PMU_OFFSET;
1027 } else {
1028 *regmap = info->regmap_base;
1029 *reg = PX30_DRV_GRF_OFFSET;
1030
1031 /* correct the offset, as we're starting with the 2nd bank */
1032 *reg -= 0x10;
1033 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1034 }
1035
1036 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1037 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1038 *bit *= PX30_DRV_BITS_PER_PIN;
1039 }
1040
1041 #define PX30_SCHMITT_PMU_OFFSET 0x38
1042 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1043 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1044 #define PX30_SCHMITT_BANK_STRIDE 16
1045 #define PX30_SCHMITT_PINS_PER_GRF_REG 8
1046
px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1047 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1048 int pin_num,
1049 struct regmap **regmap,
1050 int *reg, u8 *bit)
1051 {
1052 struct rockchip_pinctrl *info = bank->drvdata;
1053 int pins_per_reg;
1054
1055 if (bank->bank_num == 0) {
1056 *regmap = info->regmap_pmu;
1057 *reg = PX30_SCHMITT_PMU_OFFSET;
1058 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1059 } else {
1060 *regmap = info->regmap_base;
1061 *reg = PX30_SCHMITT_GRF_OFFSET;
1062 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1063 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1064 }
1065
1066 *reg += ((pin_num / pins_per_reg) * 4);
1067 *bit = pin_num % pins_per_reg;
1068
1069 return 0;
1070 }
1071
1072 #define RV1108_PULL_PMU_OFFSET 0x10
1073 #define RV1108_PULL_OFFSET 0x110
1074 #define RV1108_PULL_PINS_PER_REG 8
1075 #define RV1108_PULL_BITS_PER_PIN 2
1076 #define RV1108_PULL_BANK_STRIDE 16
1077
rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1078 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1079 int pin_num, struct regmap **regmap,
1080 int *reg, u8 *bit)
1081 {
1082 struct rockchip_pinctrl *info = bank->drvdata;
1083
1084 /* The first 24 pins of the first bank are located in PMU */
1085 if (bank->bank_num == 0) {
1086 *regmap = info->regmap_pmu;
1087 *reg = RV1108_PULL_PMU_OFFSET;
1088 } else {
1089 *reg = RV1108_PULL_OFFSET;
1090 *regmap = info->regmap_base;
1091 /* correct the offset, as we're starting with the 2nd bank */
1092 *reg -= 0x10;
1093 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1094 }
1095
1096 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1097 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1098 *bit *= RV1108_PULL_BITS_PER_PIN;
1099 }
1100
1101 #define RV1108_DRV_PMU_OFFSET 0x20
1102 #define RV1108_DRV_GRF_OFFSET 0x210
1103 #define RV1108_DRV_BITS_PER_PIN 2
1104 #define RV1108_DRV_PINS_PER_REG 8
1105 #define RV1108_DRV_BANK_STRIDE 16
1106
rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1107 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1108 int pin_num, struct regmap **regmap,
1109 int *reg, u8 *bit)
1110 {
1111 struct rockchip_pinctrl *info = bank->drvdata;
1112
1113 /* The first 24 pins of the first bank are located in PMU */
1114 if (bank->bank_num == 0) {
1115 *regmap = info->regmap_pmu;
1116 *reg = RV1108_DRV_PMU_OFFSET;
1117 } else {
1118 *regmap = info->regmap_base;
1119 *reg = RV1108_DRV_GRF_OFFSET;
1120
1121 /* correct the offset, as we're starting with the 2nd bank */
1122 *reg -= 0x10;
1123 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1124 }
1125
1126 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1127 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1128 *bit *= RV1108_DRV_BITS_PER_PIN;
1129 }
1130
1131 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1132 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1133 #define RV1108_SCHMITT_BANK_STRIDE 8
1134 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1135 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1136
rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1137 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1138 int pin_num,
1139 struct regmap **regmap,
1140 int *reg, u8 *bit)
1141 {
1142 struct rockchip_pinctrl *info = bank->drvdata;
1143 int pins_per_reg;
1144
1145 if (bank->bank_num == 0) {
1146 *regmap = info->regmap_pmu;
1147 *reg = RV1108_SCHMITT_PMU_OFFSET;
1148 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1149 } else {
1150 *regmap = info->regmap_base;
1151 *reg = RV1108_SCHMITT_GRF_OFFSET;
1152 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1153 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1154 }
1155 *reg += ((pin_num / pins_per_reg) * 4);
1156 *bit = pin_num % pins_per_reg;
1157
1158 return 0;
1159 }
1160
1161 #define RK3308_SCHMITT_PINS_PER_REG 8
1162 #define RK3308_SCHMITT_BANK_STRIDE 16
1163 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0
1164
rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1165 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1166 int pin_num, struct regmap **regmap,
1167 int *reg, u8 *bit)
1168 {
1169 struct rockchip_pinctrl *info = bank->drvdata;
1170
1171 *regmap = info->regmap_base;
1172 *reg = RK3308_SCHMITT_GRF_OFFSET;
1173
1174 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1175 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1176 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1177
1178 return 0;
1179 }
1180
1181 #define RK2928_PULL_OFFSET 0x118
1182 #define RK2928_PULL_PINS_PER_REG 16
1183 #define RK2928_PULL_BANK_STRIDE 8
1184
rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1185 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1186 int pin_num, struct regmap **regmap,
1187 int *reg, u8 *bit)
1188 {
1189 struct rockchip_pinctrl *info = bank->drvdata;
1190
1191 *regmap = info->regmap_base;
1192 *reg = RK2928_PULL_OFFSET;
1193 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1194 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1195
1196 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1197 };
1198
1199 #define RK3128_PULL_OFFSET 0x118
1200
rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1201 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1202 int pin_num, struct regmap **regmap,
1203 int *reg, u8 *bit)
1204 {
1205 struct rockchip_pinctrl *info = bank->drvdata;
1206
1207 *regmap = info->regmap_base;
1208 *reg = RK3128_PULL_OFFSET;
1209 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1210 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1211
1212 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1213 }
1214
1215 #define RK3188_PULL_OFFSET 0x164
1216 #define RK3188_PULL_BITS_PER_PIN 2
1217 #define RK3188_PULL_PINS_PER_REG 8
1218 #define RK3188_PULL_BANK_STRIDE 16
1219 #define RK3188_PULL_PMU_OFFSET 0x64
1220
rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1221 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1222 int pin_num, struct regmap **regmap,
1223 int *reg, u8 *bit)
1224 {
1225 struct rockchip_pinctrl *info = bank->drvdata;
1226
1227 /* The first 12 pins of the first bank are located elsewhere */
1228 if (bank->bank_num == 0 && pin_num < 12) {
1229 *regmap = info->regmap_pmu ? info->regmap_pmu
1230 : bank->regmap_pull;
1231 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1232 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1233 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1234 *bit *= RK3188_PULL_BITS_PER_PIN;
1235 } else {
1236 *regmap = info->regmap_pull ? info->regmap_pull
1237 : info->regmap_base;
1238 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1239
1240 /* correct the offset, as it is the 2nd pull register */
1241 *reg -= 4;
1242 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1243 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1244
1245 /*
1246 * The bits in these registers have an inverse ordering
1247 * with the lowest pin being in bits 15:14 and the highest
1248 * pin in bits 1:0
1249 */
1250 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1251 *bit *= RK3188_PULL_BITS_PER_PIN;
1252 }
1253 }
1254
1255 #define RK3288_PULL_OFFSET 0x140
rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1256 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1257 int pin_num, struct regmap **regmap,
1258 int *reg, u8 *bit)
1259 {
1260 struct rockchip_pinctrl *info = bank->drvdata;
1261
1262 /* The first 24 pins of the first bank are located in PMU */
1263 if (bank->bank_num == 0) {
1264 *regmap = info->regmap_pmu;
1265 *reg = RK3188_PULL_PMU_OFFSET;
1266
1267 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1268 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1269 *bit *= RK3188_PULL_BITS_PER_PIN;
1270 } else {
1271 *regmap = info->regmap_base;
1272 *reg = RK3288_PULL_OFFSET;
1273
1274 /* correct the offset, as we're starting with the 2nd bank */
1275 *reg -= 0x10;
1276 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1277 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1278
1279 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1280 *bit *= RK3188_PULL_BITS_PER_PIN;
1281 }
1282 }
1283
1284 #define RK3288_DRV_PMU_OFFSET 0x70
1285 #define RK3288_DRV_GRF_OFFSET 0x1c0
1286 #define RK3288_DRV_BITS_PER_PIN 2
1287 #define RK3288_DRV_PINS_PER_REG 8
1288 #define RK3288_DRV_BANK_STRIDE 16
1289
rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1290 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1291 int pin_num, struct regmap **regmap,
1292 int *reg, u8 *bit)
1293 {
1294 struct rockchip_pinctrl *info = bank->drvdata;
1295
1296 /* The first 24 pins of the first bank are located in PMU */
1297 if (bank->bank_num == 0) {
1298 *regmap = info->regmap_pmu;
1299 *reg = RK3288_DRV_PMU_OFFSET;
1300
1301 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1302 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1303 *bit *= RK3288_DRV_BITS_PER_PIN;
1304 } else {
1305 *regmap = info->regmap_base;
1306 *reg = RK3288_DRV_GRF_OFFSET;
1307
1308 /* correct the offset, as we're starting with the 2nd bank */
1309 *reg -= 0x10;
1310 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1311 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1312
1313 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1314 *bit *= RK3288_DRV_BITS_PER_PIN;
1315 }
1316 }
1317
1318 #define RK3228_PULL_OFFSET 0x100
1319
rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1320 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1321 int pin_num, struct regmap **regmap,
1322 int *reg, u8 *bit)
1323 {
1324 struct rockchip_pinctrl *info = bank->drvdata;
1325
1326 *regmap = info->regmap_base;
1327 *reg = RK3228_PULL_OFFSET;
1328 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1329 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1330
1331 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1332 *bit *= RK3188_PULL_BITS_PER_PIN;
1333 }
1334
1335 #define RK3228_DRV_GRF_OFFSET 0x200
1336
rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1337 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1338 int pin_num, struct regmap **regmap,
1339 int *reg, u8 *bit)
1340 {
1341 struct rockchip_pinctrl *info = bank->drvdata;
1342
1343 *regmap = info->regmap_base;
1344 *reg = RK3228_DRV_GRF_OFFSET;
1345 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1346 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1347
1348 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1349 *bit *= RK3288_DRV_BITS_PER_PIN;
1350 }
1351
1352 #define RK3308_PULL_OFFSET 0xa0
1353
rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1354 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1355 int pin_num, struct regmap **regmap,
1356 int *reg, u8 *bit)
1357 {
1358 struct rockchip_pinctrl *info = bank->drvdata;
1359
1360 *regmap = info->regmap_base;
1361 *reg = RK3308_PULL_OFFSET;
1362 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1363 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1364
1365 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1366 *bit *= RK3188_PULL_BITS_PER_PIN;
1367 }
1368
1369 #define RK3308_DRV_GRF_OFFSET 0x100
1370
rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1371 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1372 int pin_num, struct regmap **regmap,
1373 int *reg, u8 *bit)
1374 {
1375 struct rockchip_pinctrl *info = bank->drvdata;
1376
1377 *regmap = info->regmap_base;
1378 *reg = RK3308_DRV_GRF_OFFSET;
1379 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1380 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1381
1382 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1383 *bit *= RK3288_DRV_BITS_PER_PIN;
1384 }
1385
1386 #define RK3368_PULL_GRF_OFFSET 0x100
1387 #define RK3368_PULL_PMU_OFFSET 0x10
1388
rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1389 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1390 int pin_num, struct regmap **regmap,
1391 int *reg, u8 *bit)
1392 {
1393 struct rockchip_pinctrl *info = bank->drvdata;
1394
1395 /* The first 32 pins of the first bank are located in PMU */
1396 if (bank->bank_num == 0) {
1397 *regmap = info->regmap_pmu;
1398 *reg = RK3368_PULL_PMU_OFFSET;
1399
1400 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1401 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1402 *bit *= RK3188_PULL_BITS_PER_PIN;
1403 } else {
1404 *regmap = info->regmap_base;
1405 *reg = RK3368_PULL_GRF_OFFSET;
1406
1407 /* correct the offset, as we're starting with the 2nd bank */
1408 *reg -= 0x10;
1409 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1410 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1411
1412 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1413 *bit *= RK3188_PULL_BITS_PER_PIN;
1414 }
1415 }
1416
1417 #define RK3368_DRV_PMU_OFFSET 0x20
1418 #define RK3368_DRV_GRF_OFFSET 0x200
1419
rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1420 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1421 int pin_num, struct regmap **regmap,
1422 int *reg, u8 *bit)
1423 {
1424 struct rockchip_pinctrl *info = bank->drvdata;
1425
1426 /* The first 32 pins of the first bank are located in PMU */
1427 if (bank->bank_num == 0) {
1428 *regmap = info->regmap_pmu;
1429 *reg = RK3368_DRV_PMU_OFFSET;
1430
1431 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1432 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1433 *bit *= RK3288_DRV_BITS_PER_PIN;
1434 } else {
1435 *regmap = info->regmap_base;
1436 *reg = RK3368_DRV_GRF_OFFSET;
1437
1438 /* correct the offset, as we're starting with the 2nd bank */
1439 *reg -= 0x10;
1440 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1441 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1442
1443 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1444 *bit *= RK3288_DRV_BITS_PER_PIN;
1445 }
1446 }
1447
1448 #define RK3399_PULL_GRF_OFFSET 0xe040
1449 #define RK3399_PULL_PMU_OFFSET 0x40
1450 #define RK3399_DRV_3BITS_PER_PIN 3
1451
rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1452 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1453 int pin_num, struct regmap **regmap,
1454 int *reg, u8 *bit)
1455 {
1456 struct rockchip_pinctrl *info = bank->drvdata;
1457
1458 /* The bank0:16 and bank1:32 pins are located in PMU */
1459 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1460 *regmap = info->regmap_pmu;
1461 *reg = RK3399_PULL_PMU_OFFSET;
1462
1463 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1464
1465 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1466 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1467 *bit *= RK3188_PULL_BITS_PER_PIN;
1468 } else {
1469 *regmap = info->regmap_base;
1470 *reg = RK3399_PULL_GRF_OFFSET;
1471
1472 /* correct the offset, as we're starting with the 3rd bank */
1473 *reg -= 0x20;
1474 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1475 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1476
1477 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1478 *bit *= RK3188_PULL_BITS_PER_PIN;
1479 }
1480 }
1481
rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1482 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1483 int pin_num, struct regmap **regmap,
1484 int *reg, u8 *bit)
1485 {
1486 struct rockchip_pinctrl *info = bank->drvdata;
1487 int drv_num = (pin_num / 8);
1488
1489 /* The bank0:16 and bank1:32 pins are located in PMU */
1490 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1491 *regmap = info->regmap_pmu;
1492 else
1493 *regmap = info->regmap_base;
1494
1495 *reg = bank->drv[drv_num].offset;
1496 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1497 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1498 *bit = (pin_num % 8) * 3;
1499 else
1500 *bit = (pin_num % 8) * 2;
1501 }
1502
1503 #define RK3568_PULL_PMU_OFFSET 0x20
1504 #define RK3568_PULL_GRF_OFFSET 0x80
1505 #define RK3568_PULL_BITS_PER_PIN 2
1506 #define RK3568_PULL_PINS_PER_REG 8
1507 #define RK3568_PULL_BANK_STRIDE 0x10
1508
rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1509 static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1510 int pin_num, struct regmap **regmap,
1511 int *reg, u8 *bit)
1512 {
1513 struct rockchip_pinctrl *info = bank->drvdata;
1514
1515 if (bank->bank_num == 0) {
1516 *regmap = info->regmap_pmu;
1517 *reg = RK3568_PULL_PMU_OFFSET;
1518 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
1519 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1520
1521 *bit = pin_num % RK3568_PULL_PINS_PER_REG;
1522 *bit *= RK3568_PULL_BITS_PER_PIN;
1523 } else {
1524 *regmap = info->regmap_base;
1525 *reg = RK3568_PULL_GRF_OFFSET;
1526 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
1527 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1528
1529 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
1530 *bit *= RK3568_PULL_BITS_PER_PIN;
1531 }
1532 }
1533
1534 #define RK3568_DRV_PMU_OFFSET 0x70
1535 #define RK3568_DRV_GRF_OFFSET 0x200
1536 #define RK3568_DRV_BITS_PER_PIN 8
1537 #define RK3568_DRV_PINS_PER_REG 2
1538 #define RK3568_DRV_BANK_STRIDE 0x40
1539
rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1540 static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1541 int pin_num, struct regmap **regmap,
1542 int *reg, u8 *bit)
1543 {
1544 struct rockchip_pinctrl *info = bank->drvdata;
1545
1546 /* The first 32 pins of the first bank are located in PMU */
1547 if (bank->bank_num == 0) {
1548 *regmap = info->regmap_pmu;
1549 *reg = RK3568_DRV_PMU_OFFSET;
1550 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1551
1552 *bit = pin_num % RK3568_DRV_PINS_PER_REG;
1553 *bit *= RK3568_DRV_BITS_PER_PIN;
1554 } else {
1555 *regmap = info->regmap_base;
1556 *reg = RK3568_DRV_GRF_OFFSET;
1557 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
1558 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1559
1560 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
1561 *bit *= RK3568_DRV_BITS_PER_PIN;
1562 }
1563 }
1564
1565 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1566 { 2, 4, 8, 12, -1, -1, -1, -1 },
1567 { 3, 6, 9, 12, -1, -1, -1, -1 },
1568 { 5, 10, 15, 20, -1, -1, -1, -1 },
1569 { 4, 6, 8, 10, 12, 14, 16, 18 },
1570 { 4, 7, 10, 13, 16, 19, 22, 26 }
1571 };
1572
rockchip_get_drive_perpin(struct rockchip_pin_bank * bank,int pin_num)1573 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1574 int pin_num)
1575 {
1576 struct rockchip_pinctrl *info = bank->drvdata;
1577 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1578 struct regmap *regmap;
1579 int reg, ret;
1580 u32 data, temp, rmask_bits;
1581 u8 bit;
1582 int drv_type = bank->drv[pin_num / 8].drv_type;
1583
1584 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1585
1586 switch (drv_type) {
1587 case DRV_TYPE_IO_1V8_3V0_AUTO:
1588 case DRV_TYPE_IO_3V3_ONLY:
1589 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1590 switch (bit) {
1591 case 0 ... 12:
1592 /* regular case, nothing to do */
1593 break;
1594 case 15:
1595 /*
1596 * drive-strength offset is special, as it is
1597 * spread over 2 registers
1598 */
1599 ret = regmap_read(regmap, reg, &data);
1600 if (ret)
1601 return ret;
1602
1603 ret = regmap_read(regmap, reg + 0x4, &temp);
1604 if (ret)
1605 return ret;
1606
1607 /*
1608 * the bit data[15] contains bit 0 of the value
1609 * while temp[1:0] contains bits 2 and 1
1610 */
1611 data >>= 15;
1612 temp &= 0x3;
1613 temp <<= 1;
1614 data |= temp;
1615
1616 return rockchip_perpin_drv_list[drv_type][data];
1617 case 18 ... 21:
1618 /* setting fully enclosed in the second register */
1619 reg += 4;
1620 bit -= 16;
1621 break;
1622 default:
1623 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1624 bit, drv_type);
1625 return -EINVAL;
1626 }
1627
1628 break;
1629 case DRV_TYPE_IO_DEFAULT:
1630 case DRV_TYPE_IO_1V8_OR_3V0:
1631 case DRV_TYPE_IO_1V8_ONLY:
1632 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1633 break;
1634 default:
1635 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1636 drv_type);
1637 return -EINVAL;
1638 }
1639
1640 ret = regmap_read(regmap, reg, &data);
1641 if (ret)
1642 return ret;
1643
1644 data >>= bit;
1645 data &= (1 << rmask_bits) - 1;
1646
1647 return rockchip_perpin_drv_list[drv_type][data];
1648 }
1649
rockchip_set_drive_perpin(struct rockchip_pin_bank * bank,int pin_num,int strength)1650 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1651 int pin_num, int strength)
1652 {
1653 struct rockchip_pinctrl *info = bank->drvdata;
1654 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1655 struct regmap *regmap;
1656 int reg, ret, i;
1657 u32 data, rmask, rmask_bits, temp;
1658 u8 bit;
1659 int drv_type = bank->drv[pin_num / 8].drv_type;
1660
1661 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1662 bank->bank_num, pin_num, strength);
1663
1664 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1665 if (ctrl->type == RK3568) {
1666 rmask_bits = RK3568_DRV_BITS_PER_PIN;
1667 ret = (1 << (strength + 1)) - 1;
1668 goto config;
1669 }
1670
1671 ret = -EINVAL;
1672 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1673 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1674 ret = i;
1675 break;
1676 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1677 ret = rockchip_perpin_drv_list[drv_type][i];
1678 break;
1679 }
1680 }
1681
1682 if (ret < 0) {
1683 dev_err(info->dev, "unsupported driver strength %d\n",
1684 strength);
1685 return ret;
1686 }
1687
1688 switch (drv_type) {
1689 case DRV_TYPE_IO_1V8_3V0_AUTO:
1690 case DRV_TYPE_IO_3V3_ONLY:
1691 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1692 switch (bit) {
1693 case 0 ... 12:
1694 /* regular case, nothing to do */
1695 break;
1696 case 15:
1697 /*
1698 * drive-strength offset is special, as it is spread
1699 * over 2 registers, the bit data[15] contains bit 0
1700 * of the value while temp[1:0] contains bits 2 and 1
1701 */
1702 data = (ret & 0x1) << 15;
1703 temp = (ret >> 0x1) & 0x3;
1704
1705 rmask = BIT(15) | BIT(31);
1706 data |= BIT(31);
1707 ret = regmap_update_bits(regmap, reg, rmask, data);
1708 if (ret)
1709 return ret;
1710
1711 rmask = 0x3 | (0x3 << 16);
1712 temp |= (0x3 << 16);
1713 reg += 0x4;
1714 ret = regmap_update_bits(regmap, reg, rmask, temp);
1715
1716 return ret;
1717 case 18 ... 21:
1718 /* setting fully enclosed in the second register */
1719 reg += 4;
1720 bit -= 16;
1721 break;
1722 default:
1723 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1724 bit, drv_type);
1725 return -EINVAL;
1726 }
1727 break;
1728 case DRV_TYPE_IO_DEFAULT:
1729 case DRV_TYPE_IO_1V8_OR_3V0:
1730 case DRV_TYPE_IO_1V8_ONLY:
1731 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1732 break;
1733 default:
1734 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1735 drv_type);
1736 return -EINVAL;
1737 }
1738
1739 config:
1740 /* enable the write to the equivalent lower bits */
1741 data = ((1 << rmask_bits) - 1) << (bit + 16);
1742 rmask = data | (data >> 16);
1743 data |= (ret << bit);
1744
1745 ret = regmap_update_bits(regmap, reg, rmask, data);
1746
1747 return ret;
1748 }
1749
1750 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1751 {
1752 PIN_CONFIG_BIAS_DISABLE,
1753 PIN_CONFIG_BIAS_PULL_UP,
1754 PIN_CONFIG_BIAS_PULL_DOWN,
1755 PIN_CONFIG_BIAS_BUS_HOLD
1756 },
1757 {
1758 PIN_CONFIG_BIAS_DISABLE,
1759 PIN_CONFIG_BIAS_PULL_DOWN,
1760 PIN_CONFIG_BIAS_DISABLE,
1761 PIN_CONFIG_BIAS_PULL_UP
1762 },
1763 };
1764
rockchip_get_pull(struct rockchip_pin_bank * bank,int pin_num)1765 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1766 {
1767 struct rockchip_pinctrl *info = bank->drvdata;
1768 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1769 struct regmap *regmap;
1770 int reg, ret, pull_type;
1771 u8 bit;
1772 u32 data;
1773
1774 /* rk3066b does support any pulls */
1775 if (ctrl->type == RK3066B)
1776 return PIN_CONFIG_BIAS_DISABLE;
1777
1778 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1779
1780 ret = regmap_read(regmap, reg, &data);
1781 if (ret)
1782 return ret;
1783
1784 switch (ctrl->type) {
1785 case RK2928:
1786 case RK3128:
1787 return !(data & BIT(bit))
1788 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1789 : PIN_CONFIG_BIAS_DISABLE;
1790 case PX30:
1791 case RV1108:
1792 case RK3188:
1793 case RK3288:
1794 case RK3308:
1795 case RK3368:
1796 case RK3399:
1797 pull_type = bank->pull_type[pin_num / 8];
1798 data >>= bit;
1799 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1800
1801 return rockchip_pull_list[pull_type][data];
1802 default:
1803 dev_err(info->dev, "unsupported pinctrl type\n");
1804 return -EINVAL;
1805 };
1806 }
1807
rockchip_set_pull(struct rockchip_pin_bank * bank,int pin_num,int pull)1808 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1809 int pin_num, int pull)
1810 {
1811 struct rockchip_pinctrl *info = bank->drvdata;
1812 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1813 struct regmap *regmap;
1814 int reg, ret, i, pull_type;
1815 u8 bit;
1816 u32 data, rmask;
1817
1818 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1819 bank->bank_num, pin_num, pull);
1820
1821 /* rk3066b does support any pulls */
1822 if (ctrl->type == RK3066B)
1823 return pull ? -EINVAL : 0;
1824
1825 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1826
1827 switch (ctrl->type) {
1828 case RK2928:
1829 case RK3128:
1830 data = BIT(bit + 16);
1831 if (pull == PIN_CONFIG_BIAS_DISABLE)
1832 data |= BIT(bit);
1833 ret = regmap_write(regmap, reg, data);
1834 break;
1835 case PX30:
1836 case RV1108:
1837 case RK3188:
1838 case RK3288:
1839 case RK3308:
1840 case RK3368:
1841 case RK3399:
1842 case RK3568:
1843 pull_type = bank->pull_type[pin_num / 8];
1844 ret = -EINVAL;
1845 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1846 i++) {
1847 if (rockchip_pull_list[pull_type][i] == pull) {
1848 ret = i;
1849 break;
1850 }
1851 }
1852 /*
1853 * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6,
1854 * where that pull up value becomes 3.
1855 */
1856 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
1857 if (ret == 1)
1858 ret = 3;
1859 }
1860
1861 if (ret < 0) {
1862 dev_err(info->dev, "unsupported pull setting %d\n",
1863 pull);
1864 return ret;
1865 }
1866
1867 /* enable the write to the equivalent lower bits */
1868 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1869 rmask = data | (data >> 16);
1870 data |= (ret << bit);
1871
1872 ret = regmap_update_bits(regmap, reg, rmask, data);
1873 break;
1874 default:
1875 dev_err(info->dev, "unsupported pinctrl type\n");
1876 return -EINVAL;
1877 }
1878
1879 return ret;
1880 }
1881
1882 #define RK3328_SCHMITT_BITS_PER_PIN 1
1883 #define RK3328_SCHMITT_PINS_PER_REG 16
1884 #define RK3328_SCHMITT_BANK_STRIDE 8
1885 #define RK3328_SCHMITT_GRF_OFFSET 0x380
1886
rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1887 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1888 int pin_num,
1889 struct regmap **regmap,
1890 int *reg, u8 *bit)
1891 {
1892 struct rockchip_pinctrl *info = bank->drvdata;
1893
1894 *regmap = info->regmap_base;
1895 *reg = RK3328_SCHMITT_GRF_OFFSET;
1896
1897 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
1898 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
1899 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
1900
1901 return 0;
1902 }
1903
1904 #define RK3568_SCHMITT_BITS_PER_PIN 2
1905 #define RK3568_SCHMITT_PINS_PER_REG 8
1906 #define RK3568_SCHMITT_BANK_STRIDE 0x10
1907 #define RK3568_SCHMITT_GRF_OFFSET 0xc0
1908 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
1909
rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1910 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1911 int pin_num,
1912 struct regmap **regmap,
1913 int *reg, u8 *bit)
1914 {
1915 struct rockchip_pinctrl *info = bank->drvdata;
1916
1917 if (bank->bank_num == 0) {
1918 *regmap = info->regmap_pmu;
1919 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
1920 } else {
1921 *regmap = info->regmap_base;
1922 *reg = RK3568_SCHMITT_GRF_OFFSET;
1923 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
1924 }
1925
1926 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
1927 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
1928 *bit *= RK3568_SCHMITT_BITS_PER_PIN;
1929
1930 return 0;
1931 }
1932
rockchip_get_schmitt(struct rockchip_pin_bank * bank,int pin_num)1933 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
1934 {
1935 struct rockchip_pinctrl *info = bank->drvdata;
1936 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1937 struct regmap *regmap;
1938 int reg, ret;
1939 u8 bit;
1940 u32 data;
1941
1942 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
1943 if (ret)
1944 return ret;
1945
1946 ret = regmap_read(regmap, reg, &data);
1947 if (ret)
1948 return ret;
1949
1950 data >>= bit;
1951 switch (ctrl->type) {
1952 case RK3568:
1953 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
1954 default:
1955 break;
1956 }
1957
1958 return data & 0x1;
1959 }
1960
rockchip_set_schmitt(struct rockchip_pin_bank * bank,int pin_num,int enable)1961 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
1962 int pin_num, int enable)
1963 {
1964 struct rockchip_pinctrl *info = bank->drvdata;
1965 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1966 struct regmap *regmap;
1967 int reg, ret;
1968 u8 bit;
1969 u32 data, rmask;
1970
1971 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
1972 bank->bank_num, pin_num, enable);
1973
1974 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
1975 if (ret)
1976 return ret;
1977
1978 /* enable the write to the equivalent lower bits */
1979 switch (ctrl->type) {
1980 case RK3568:
1981 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
1982 rmask = data | (data >> 16);
1983 data |= ((enable ? 0x2 : 0x1) << bit);
1984 break;
1985 default:
1986 data = BIT(bit + 16) | (enable << bit);
1987 rmask = BIT(bit + 16) | BIT(bit);
1988 break;
1989 }
1990
1991 return regmap_update_bits(regmap, reg, rmask, data);
1992 }
1993
1994 /*
1995 * Pinmux_ops handling
1996 */
1997
rockchip_pmx_get_funcs_count(struct pinctrl_dev * pctldev)1998 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1999 {
2000 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2001
2002 return info->nfunctions;
2003 }
2004
rockchip_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned selector)2005 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2006 unsigned selector)
2007 {
2008 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2009
2010 return info->functions[selector].name;
2011 }
2012
rockchip_pmx_get_groups(struct pinctrl_dev * pctldev,unsigned selector,const char * const ** groups,unsigned * const num_groups)2013 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2014 unsigned selector, const char * const **groups,
2015 unsigned * const num_groups)
2016 {
2017 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2018
2019 *groups = info->functions[selector].groups;
2020 *num_groups = info->functions[selector].ngroups;
2021
2022 return 0;
2023 }
2024
rockchip_pmx_set(struct pinctrl_dev * pctldev,unsigned selector,unsigned group)2025 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2026 unsigned group)
2027 {
2028 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2029 const unsigned int *pins = info->groups[group].pins;
2030 const struct rockchip_pin_config *data = info->groups[group].data;
2031 struct rockchip_pin_bank *bank;
2032 int cnt, ret = 0;
2033
2034 dev_dbg(info->dev, "enable function %s group %s\n",
2035 info->functions[selector].name, info->groups[group].name);
2036
2037 /*
2038 * for each pin in the pin group selected, program the corresponding
2039 * pin function number in the config register.
2040 */
2041 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2042 bank = pin_to_bank(info, pins[cnt]);
2043 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2044 data[cnt].func);
2045 if (ret)
2046 break;
2047 }
2048
2049 if (ret) {
2050 /* revert the already done pin settings */
2051 for (cnt--; cnt >= 0; cnt--)
2052 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2053
2054 return ret;
2055 }
2056
2057 return 0;
2058 }
2059
2060 static const struct pinmux_ops rockchip_pmx_ops = {
2061 .get_functions_count = rockchip_pmx_get_funcs_count,
2062 .get_function_name = rockchip_pmx_get_func_name,
2063 .get_function_groups = rockchip_pmx_get_groups,
2064 .set_mux = rockchip_pmx_set,
2065 };
2066
2067 /*
2068 * Pinconf_ops handling
2069 */
2070
rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl * ctrl,enum pin_config_param pull)2071 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2072 enum pin_config_param pull)
2073 {
2074 switch (ctrl->type) {
2075 case RK2928:
2076 case RK3128:
2077 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2078 pull == PIN_CONFIG_BIAS_DISABLE);
2079 case RK3066B:
2080 return pull ? false : true;
2081 case PX30:
2082 case RV1108:
2083 case RK3188:
2084 case RK3288:
2085 case RK3308:
2086 case RK3368:
2087 case RK3399:
2088 case RK3568:
2089 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2090 }
2091
2092 return false;
2093 }
2094
rockchip_pinconf_defer_output(struct rockchip_pin_bank * bank,unsigned int pin,u32 arg)2095 static int rockchip_pinconf_defer_output(struct rockchip_pin_bank *bank,
2096 unsigned int pin, u32 arg)
2097 {
2098 struct rockchip_pin_output_deferred *cfg;
2099
2100 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
2101 if (!cfg)
2102 return -ENOMEM;
2103
2104 cfg->pin = pin;
2105 cfg->arg = arg;
2106
2107 list_add_tail(&cfg->head, &bank->deferred_output);
2108
2109 return 0;
2110 }
2111
2112 /* set the pin config settings for a specified pin */
rockchip_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned num_configs)2113 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2114 unsigned long *configs, unsigned num_configs)
2115 {
2116 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2117 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2118 struct gpio_chip *gpio = &bank->gpio_chip;
2119 enum pin_config_param param;
2120 u32 arg;
2121 int i;
2122 int rc;
2123
2124 for (i = 0; i < num_configs; i++) {
2125 param = pinconf_to_config_param(configs[i]);
2126 arg = pinconf_to_config_argument(configs[i]);
2127
2128 switch (param) {
2129 case PIN_CONFIG_BIAS_DISABLE:
2130 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2131 param);
2132 if (rc)
2133 return rc;
2134 break;
2135 case PIN_CONFIG_BIAS_PULL_UP:
2136 case PIN_CONFIG_BIAS_PULL_DOWN:
2137 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2138 case PIN_CONFIG_BIAS_BUS_HOLD:
2139 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2140 return -ENOTSUPP;
2141
2142 if (!arg)
2143 return -EINVAL;
2144
2145 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2146 param);
2147 if (rc)
2148 return rc;
2149 break;
2150 case PIN_CONFIG_OUTPUT:
2151 rc = rockchip_set_mux(bank, pin - bank->pin_base,
2152 RK_FUNC_GPIO);
2153 if (rc != RK_FUNC_GPIO)
2154 return -EINVAL;
2155
2156 /*
2157 * Check for gpio driver not being probed yet.
2158 * The lock makes sure that either gpio-probe has completed
2159 * or the gpio driver hasn't probed yet.
2160 */
2161 mutex_lock(&bank->deferred_lock);
2162 if (!gpio || !gpio->direction_output) {
2163 rc = rockchip_pinconf_defer_output(bank, pin - bank->pin_base, arg);
2164 mutex_unlock(&bank->deferred_lock);
2165 if (rc)
2166 return rc;
2167
2168 break;
2169 }
2170 mutex_unlock(&bank->deferred_lock);
2171
2172 rc = gpio->direction_output(gpio, pin - bank->pin_base,
2173 arg);
2174 if (rc)
2175 return rc;
2176 break;
2177 case PIN_CONFIG_DRIVE_STRENGTH:
2178 /* rk3288 is the first with per-pin drive-strength */
2179 if (!info->ctrl->drv_calc_reg)
2180 return -ENOTSUPP;
2181
2182 rc = rockchip_set_drive_perpin(bank,
2183 pin - bank->pin_base, arg);
2184 if (rc < 0)
2185 return rc;
2186 break;
2187 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2188 if (!info->ctrl->schmitt_calc_reg)
2189 return -ENOTSUPP;
2190
2191 rc = rockchip_set_schmitt(bank,
2192 pin - bank->pin_base, arg);
2193 if (rc < 0)
2194 return rc;
2195 break;
2196 default:
2197 return -ENOTSUPP;
2198 break;
2199 }
2200 } /* for each config */
2201
2202 return 0;
2203 }
2204
2205 /* get the pin config settings for a specified pin */
rockchip_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)2206 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2207 unsigned long *config)
2208 {
2209 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2210 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2211 struct gpio_chip *gpio = &bank->gpio_chip;
2212 enum pin_config_param param = pinconf_to_config_param(*config);
2213 u16 arg;
2214 int rc;
2215
2216 switch (param) {
2217 case PIN_CONFIG_BIAS_DISABLE:
2218 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2219 return -EINVAL;
2220
2221 arg = 0;
2222 break;
2223 case PIN_CONFIG_BIAS_PULL_UP:
2224 case PIN_CONFIG_BIAS_PULL_DOWN:
2225 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2226 case PIN_CONFIG_BIAS_BUS_HOLD:
2227 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2228 return -ENOTSUPP;
2229
2230 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2231 return -EINVAL;
2232
2233 arg = 1;
2234 break;
2235 case PIN_CONFIG_OUTPUT:
2236 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2237 if (rc != RK_FUNC_GPIO)
2238 return -EINVAL;
2239
2240 if (!gpio || !gpio->get) {
2241 arg = 0;
2242 break;
2243 }
2244
2245 rc = gpio->get(gpio, pin - bank->pin_base);
2246 if (rc < 0)
2247 return rc;
2248
2249 arg = rc ? 1 : 0;
2250 break;
2251 case PIN_CONFIG_DRIVE_STRENGTH:
2252 /* rk3288 is the first with per-pin drive-strength */
2253 if (!info->ctrl->drv_calc_reg)
2254 return -ENOTSUPP;
2255
2256 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2257 if (rc < 0)
2258 return rc;
2259
2260 arg = rc;
2261 break;
2262 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2263 if (!info->ctrl->schmitt_calc_reg)
2264 return -ENOTSUPP;
2265
2266 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2267 if (rc < 0)
2268 return rc;
2269
2270 arg = rc;
2271 break;
2272 default:
2273 return -ENOTSUPP;
2274 break;
2275 }
2276
2277 *config = pinconf_to_config_packed(param, arg);
2278
2279 return 0;
2280 }
2281
2282 static const struct pinconf_ops rockchip_pinconf_ops = {
2283 .pin_config_get = rockchip_pinconf_get,
2284 .pin_config_set = rockchip_pinconf_set,
2285 .is_generic = true,
2286 };
2287
2288 static const struct of_device_id rockchip_bank_match[] = {
2289 { .compatible = "rockchip,gpio-bank" },
2290 { .compatible = "rockchip,rk3188-gpio-bank0" },
2291 {},
2292 };
2293
rockchip_pinctrl_child_count(struct rockchip_pinctrl * info,struct device_node * np)2294 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2295 struct device_node *np)
2296 {
2297 struct device_node *child;
2298
2299 for_each_child_of_node(np, child) {
2300 if (of_match_node(rockchip_bank_match, child))
2301 continue;
2302
2303 info->nfunctions++;
2304 info->ngroups += of_get_child_count(child);
2305 }
2306 }
2307
rockchip_pinctrl_parse_groups(struct device_node * np,struct rockchip_pin_group * grp,struct rockchip_pinctrl * info,u32 index)2308 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2309 struct rockchip_pin_group *grp,
2310 struct rockchip_pinctrl *info,
2311 u32 index)
2312 {
2313 struct rockchip_pin_bank *bank;
2314 int size;
2315 const __be32 *list;
2316 int num;
2317 int i, j;
2318 int ret;
2319
2320 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
2321
2322 /* Initialise group */
2323 grp->name = np->name;
2324
2325 /*
2326 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2327 * do sanity check and calculate pins number
2328 */
2329 list = of_get_property(np, "rockchip,pins", &size);
2330 /* we do not check return since it's safe node passed down */
2331 size /= sizeof(*list);
2332 if (!size || size % 4) {
2333 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2334 return -EINVAL;
2335 }
2336
2337 grp->npins = size / 4;
2338
2339 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
2340 GFP_KERNEL);
2341 grp->data = devm_kcalloc(info->dev,
2342 grp->npins,
2343 sizeof(struct rockchip_pin_config),
2344 GFP_KERNEL);
2345 if (!grp->pins || !grp->data)
2346 return -ENOMEM;
2347
2348 for (i = 0, j = 0; i < size; i += 4, j++) {
2349 const __be32 *phandle;
2350 struct device_node *np_config;
2351
2352 num = be32_to_cpu(*list++);
2353 bank = bank_num_to_bank(info, num);
2354 if (IS_ERR(bank))
2355 return PTR_ERR(bank);
2356
2357 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2358 grp->data[j].func = be32_to_cpu(*list++);
2359
2360 phandle = list++;
2361 if (!phandle)
2362 return -EINVAL;
2363
2364 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2365 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2366 &grp->data[j].configs, &grp->data[j].nconfigs);
2367 if (ret)
2368 return ret;
2369 }
2370
2371 return 0;
2372 }
2373
rockchip_pinctrl_parse_functions(struct device_node * np,struct rockchip_pinctrl * info,u32 index)2374 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2375 struct rockchip_pinctrl *info,
2376 u32 index)
2377 {
2378 struct device_node *child;
2379 struct rockchip_pmx_func *func;
2380 struct rockchip_pin_group *grp;
2381 int ret;
2382 static u32 grp_index;
2383 u32 i = 0;
2384
2385 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
2386
2387 func = &info->functions[index];
2388
2389 /* Initialise function */
2390 func->name = np->name;
2391 func->ngroups = of_get_child_count(np);
2392 if (func->ngroups <= 0)
2393 return 0;
2394
2395 func->groups = devm_kcalloc(info->dev,
2396 func->ngroups, sizeof(char *), GFP_KERNEL);
2397 if (!func->groups)
2398 return -ENOMEM;
2399
2400 for_each_child_of_node(np, child) {
2401 func->groups[i] = child->name;
2402 grp = &info->groups[grp_index++];
2403 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2404 if (ret) {
2405 of_node_put(child);
2406 return ret;
2407 }
2408 }
2409
2410 return 0;
2411 }
2412
rockchip_pinctrl_parse_dt(struct platform_device * pdev,struct rockchip_pinctrl * info)2413 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2414 struct rockchip_pinctrl *info)
2415 {
2416 struct device *dev = &pdev->dev;
2417 struct device_node *np = dev->of_node;
2418 struct device_node *child;
2419 int ret;
2420 int i;
2421
2422 rockchip_pinctrl_child_count(info, np);
2423
2424 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2425 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2426
2427 info->functions = devm_kcalloc(dev,
2428 info->nfunctions,
2429 sizeof(struct rockchip_pmx_func),
2430 GFP_KERNEL);
2431 if (!info->functions)
2432 return -ENOMEM;
2433
2434 info->groups = devm_kcalloc(dev,
2435 info->ngroups,
2436 sizeof(struct rockchip_pin_group),
2437 GFP_KERNEL);
2438 if (!info->groups)
2439 return -ENOMEM;
2440
2441 i = 0;
2442
2443 for_each_child_of_node(np, child) {
2444 if (of_match_node(rockchip_bank_match, child))
2445 continue;
2446
2447 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2448 if (ret) {
2449 dev_err(&pdev->dev, "failed to parse function\n");
2450 of_node_put(child);
2451 return ret;
2452 }
2453 }
2454
2455 return 0;
2456 }
2457
rockchip_pinctrl_register(struct platform_device * pdev,struct rockchip_pinctrl * info)2458 static int rockchip_pinctrl_register(struct platform_device *pdev,
2459 struct rockchip_pinctrl *info)
2460 {
2461 struct pinctrl_desc *ctrldesc = &info->pctl;
2462 struct pinctrl_pin_desc *pindesc, *pdesc;
2463 struct rockchip_pin_bank *pin_bank;
2464 int pin, bank, ret;
2465 int k;
2466
2467 ctrldesc->name = "rockchip-pinctrl";
2468 ctrldesc->owner = THIS_MODULE;
2469 ctrldesc->pctlops = &rockchip_pctrl_ops;
2470 ctrldesc->pmxops = &rockchip_pmx_ops;
2471 ctrldesc->confops = &rockchip_pinconf_ops;
2472
2473 pindesc = devm_kcalloc(&pdev->dev,
2474 info->ctrl->nr_pins, sizeof(*pindesc),
2475 GFP_KERNEL);
2476 if (!pindesc)
2477 return -ENOMEM;
2478
2479 ctrldesc->pins = pindesc;
2480 ctrldesc->npins = info->ctrl->nr_pins;
2481
2482 pdesc = pindesc;
2483 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
2484 pin_bank = &info->ctrl->pin_banks[bank];
2485 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2486 pdesc->number = k;
2487 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2488 pin_bank->name, pin);
2489 pdesc++;
2490 }
2491
2492 INIT_LIST_HEAD(&pin_bank->deferred_output);
2493 mutex_init(&pin_bank->deferred_lock);
2494 }
2495
2496 ret = rockchip_pinctrl_parse_dt(pdev, info);
2497 if (ret)
2498 return ret;
2499
2500 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
2501 if (IS_ERR(info->pctl_dev)) {
2502 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2503 return PTR_ERR(info->pctl_dev);
2504 }
2505
2506 return 0;
2507 }
2508
2509 static const struct of_device_id rockchip_pinctrl_dt_match[];
2510
2511 /* retrieve the soc specific data */
rockchip_pinctrl_get_soc_data(struct rockchip_pinctrl * d,struct platform_device * pdev)2512 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2513 struct rockchip_pinctrl *d,
2514 struct platform_device *pdev)
2515 {
2516 const struct of_device_id *match;
2517 struct device_node *node = pdev->dev.of_node;
2518 struct rockchip_pin_ctrl *ctrl;
2519 struct rockchip_pin_bank *bank;
2520 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2521
2522 match = of_match_node(rockchip_pinctrl_dt_match, node);
2523 ctrl = (struct rockchip_pin_ctrl *)match->data;
2524
2525 grf_offs = ctrl->grf_mux_offset;
2526 pmu_offs = ctrl->pmu_mux_offset;
2527 drv_pmu_offs = ctrl->pmu_drv_offset;
2528 drv_grf_offs = ctrl->grf_drv_offset;
2529 bank = ctrl->pin_banks;
2530 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2531 int bank_pins = 0;
2532
2533 raw_spin_lock_init(&bank->slock);
2534 bank->drvdata = d;
2535 bank->pin_base = ctrl->nr_pins;
2536 ctrl->nr_pins += bank->nr_pins;
2537
2538 /* calculate iomux and drv offsets */
2539 for (j = 0; j < 4; j++) {
2540 struct rockchip_iomux *iom = &bank->iomux[j];
2541 struct rockchip_drv *drv = &bank->drv[j];
2542 int inc;
2543
2544 if (bank_pins >= bank->nr_pins)
2545 break;
2546
2547 /* preset iomux offset value, set new start value */
2548 if (iom->offset >= 0) {
2549 if (iom->type & IOMUX_SOURCE_PMU)
2550 pmu_offs = iom->offset;
2551 else
2552 grf_offs = iom->offset;
2553 } else { /* set current iomux offset */
2554 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2555 pmu_offs : grf_offs;
2556 }
2557
2558 /* preset drv offset value, set new start value */
2559 if (drv->offset >= 0) {
2560 if (iom->type & IOMUX_SOURCE_PMU)
2561 drv_pmu_offs = drv->offset;
2562 else
2563 drv_grf_offs = drv->offset;
2564 } else { /* set current drv offset */
2565 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2566 drv_pmu_offs : drv_grf_offs;
2567 }
2568
2569 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2570 i, j, iom->offset, drv->offset);
2571
2572 /*
2573 * Increase offset according to iomux width.
2574 * 4bit iomux'es are spread over two registers.
2575 */
2576 inc = (iom->type & (IOMUX_WIDTH_4BIT |
2577 IOMUX_WIDTH_3BIT |
2578 IOMUX_WIDTH_2BIT)) ? 8 : 4;
2579 if (iom->type & IOMUX_SOURCE_PMU)
2580 pmu_offs += inc;
2581 else
2582 grf_offs += inc;
2583
2584 /*
2585 * Increase offset according to drv width.
2586 * 3bit drive-strenth'es are spread over two registers.
2587 */
2588 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2589 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2590 inc = 8;
2591 else
2592 inc = 4;
2593
2594 if (iom->type & IOMUX_SOURCE_PMU)
2595 drv_pmu_offs += inc;
2596 else
2597 drv_grf_offs += inc;
2598
2599 bank_pins += 8;
2600 }
2601
2602 /* calculate the per-bank recalced_mask */
2603 for (j = 0; j < ctrl->niomux_recalced; j++) {
2604 int pin = 0;
2605
2606 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
2607 pin = ctrl->iomux_recalced[j].pin;
2608 bank->recalced_mask |= BIT(pin);
2609 }
2610 }
2611
2612 /* calculate the per-bank route_mask */
2613 for (j = 0; j < ctrl->niomux_routes; j++) {
2614 int pin = 0;
2615
2616 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
2617 pin = ctrl->iomux_routes[j].pin;
2618 bank->route_mask |= BIT(pin);
2619 }
2620 }
2621 }
2622
2623 return ctrl;
2624 }
2625
2626 #define RK3288_GRF_GPIO6C_IOMUX 0x64
2627 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
2628
2629 static u32 rk3288_grf_gpio6c_iomux;
2630
rockchip_pinctrl_suspend(struct device * dev)2631 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2632 {
2633 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2634 int ret = pinctrl_force_sleep(info->pctl_dev);
2635
2636 if (ret)
2637 return ret;
2638
2639 /*
2640 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2641 * the setting here, and restore it at resume.
2642 */
2643 if (info->ctrl->type == RK3288) {
2644 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2645 &rk3288_grf_gpio6c_iomux);
2646 if (ret) {
2647 pinctrl_force_default(info->pctl_dev);
2648 return ret;
2649 }
2650 }
2651
2652 return 0;
2653 }
2654
rockchip_pinctrl_resume(struct device * dev)2655 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2656 {
2657 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2658 int ret;
2659
2660 if (info->ctrl->type == RK3288) {
2661 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2662 rk3288_grf_gpio6c_iomux |
2663 GPIO6C6_SEL_WRITE_ENABLE);
2664 if (ret)
2665 return ret;
2666 }
2667
2668 return pinctrl_force_default(info->pctl_dev);
2669 }
2670
2671 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2672 rockchip_pinctrl_resume);
2673
rockchip_pinctrl_probe(struct platform_device * pdev)2674 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2675 {
2676 struct rockchip_pinctrl *info;
2677 struct device *dev = &pdev->dev;
2678 struct rockchip_pin_ctrl *ctrl;
2679 struct device_node *np = pdev->dev.of_node, *node;
2680 struct resource *res;
2681 void __iomem *base;
2682 int ret;
2683
2684 if (!dev->of_node) {
2685 dev_err(dev, "device tree node not found\n");
2686 return -ENODEV;
2687 }
2688
2689 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
2690 if (!info)
2691 return -ENOMEM;
2692
2693 info->dev = dev;
2694
2695 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2696 if (!ctrl) {
2697 dev_err(dev, "driver data not available\n");
2698 return -EINVAL;
2699 }
2700 info->ctrl = ctrl;
2701
2702 node = of_parse_phandle(np, "rockchip,grf", 0);
2703 if (node) {
2704 info->regmap_base = syscon_node_to_regmap(node);
2705 if (IS_ERR(info->regmap_base))
2706 return PTR_ERR(info->regmap_base);
2707 } else {
2708 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2709 base = devm_ioremap_resource(&pdev->dev, res);
2710 if (IS_ERR(base))
2711 return PTR_ERR(base);
2712
2713 rockchip_regmap_config.max_register = resource_size(res) - 4;
2714 rockchip_regmap_config.name = "rockchip,pinctrl";
2715 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2716 &rockchip_regmap_config);
2717
2718 /* to check for the old dt-bindings */
2719 info->reg_size = resource_size(res);
2720
2721 /* Honor the old binding, with pull registers as 2nd resource */
2722 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2723 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2724 base = devm_ioremap_resource(&pdev->dev, res);
2725 if (IS_ERR(base))
2726 return PTR_ERR(base);
2727
2728 rockchip_regmap_config.max_register =
2729 resource_size(res) - 4;
2730 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2731 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2732 base,
2733 &rockchip_regmap_config);
2734 }
2735 }
2736
2737 /* try to find the optional reference to the pmu syscon */
2738 node = of_parse_phandle(np, "rockchip,pmu", 0);
2739 if (node) {
2740 info->regmap_pmu = syscon_node_to_regmap(node);
2741 if (IS_ERR(info->regmap_pmu))
2742 return PTR_ERR(info->regmap_pmu);
2743 }
2744
2745 ret = rockchip_pinctrl_register(pdev, info);
2746 if (ret)
2747 return ret;
2748
2749 platform_set_drvdata(pdev, info);
2750
2751 ret = of_platform_populate(np, rockchip_bank_match, NULL, NULL);
2752 if (ret) {
2753 dev_err(&pdev->dev, "failed to register gpio device\n");
2754 return ret;
2755 }
2756
2757 return 0;
2758 }
2759
rockchip_pinctrl_remove(struct platform_device * pdev)2760 static int rockchip_pinctrl_remove(struct platform_device *pdev)
2761 {
2762 struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
2763 struct rockchip_pin_bank *bank;
2764 struct rockchip_pin_output_deferred *cfg;
2765 int i;
2766
2767 of_platform_depopulate(&pdev->dev);
2768
2769 for (i = 0; i < info->ctrl->nr_banks; i++) {
2770 bank = &info->ctrl->pin_banks[i];
2771
2772 mutex_lock(&bank->deferred_lock);
2773 while (!list_empty(&bank->deferred_output)) {
2774 cfg = list_first_entry(&bank->deferred_output,
2775 struct rockchip_pin_output_deferred, head);
2776 list_del(&cfg->head);
2777 kfree(cfg);
2778 }
2779 mutex_unlock(&bank->deferred_lock);
2780 }
2781
2782 return 0;
2783 }
2784
2785 static struct rockchip_pin_bank px30_pin_banks[] = {
2786 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2787 IOMUX_SOURCE_PMU,
2788 IOMUX_SOURCE_PMU,
2789 IOMUX_SOURCE_PMU
2790 ),
2791 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
2792 IOMUX_WIDTH_4BIT,
2793 IOMUX_WIDTH_4BIT,
2794 IOMUX_WIDTH_4BIT
2795 ),
2796 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
2797 IOMUX_WIDTH_4BIT,
2798 IOMUX_WIDTH_4BIT,
2799 IOMUX_WIDTH_4BIT
2800 ),
2801 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
2802 IOMUX_WIDTH_4BIT,
2803 IOMUX_WIDTH_4BIT,
2804 IOMUX_WIDTH_4BIT
2805 ),
2806 };
2807
2808 static struct rockchip_pin_ctrl px30_pin_ctrl = {
2809 .pin_banks = px30_pin_banks,
2810 .nr_banks = ARRAY_SIZE(px30_pin_banks),
2811 .label = "PX30-GPIO",
2812 .type = PX30,
2813 .grf_mux_offset = 0x0,
2814 .pmu_mux_offset = 0x0,
2815 .iomux_routes = px30_mux_route_data,
2816 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
2817 .pull_calc_reg = px30_calc_pull_reg_and_bit,
2818 .drv_calc_reg = px30_calc_drv_reg_and_bit,
2819 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
2820 };
2821
2822 static struct rockchip_pin_bank rv1108_pin_banks[] = {
2823 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2824 IOMUX_SOURCE_PMU,
2825 IOMUX_SOURCE_PMU,
2826 IOMUX_SOURCE_PMU),
2827 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2828 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
2829 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
2830 };
2831
2832 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
2833 .pin_banks = rv1108_pin_banks,
2834 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
2835 .label = "RV1108-GPIO",
2836 .type = RV1108,
2837 .grf_mux_offset = 0x10,
2838 .pmu_mux_offset = 0x0,
2839 .iomux_recalced = rv1108_mux_recalced_data,
2840 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
2841 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
2842 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
2843 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
2844 };
2845
2846 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2847 PIN_BANK(0, 32, "gpio0"),
2848 PIN_BANK(1, 32, "gpio1"),
2849 PIN_BANK(2, 32, "gpio2"),
2850 PIN_BANK(3, 32, "gpio3"),
2851 };
2852
2853 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2854 .pin_banks = rk2928_pin_banks,
2855 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
2856 .label = "RK2928-GPIO",
2857 .type = RK2928,
2858 .grf_mux_offset = 0xa8,
2859 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2860 };
2861
2862 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2863 PIN_BANK(0, 32, "gpio0"),
2864 PIN_BANK(1, 32, "gpio1"),
2865 PIN_BANK(2, 32, "gpio2"),
2866 };
2867
2868 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2869 .pin_banks = rk3036_pin_banks,
2870 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
2871 .label = "RK3036-GPIO",
2872 .type = RK2928,
2873 .grf_mux_offset = 0xa8,
2874 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2875 };
2876
2877 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2878 PIN_BANK(0, 32, "gpio0"),
2879 PIN_BANK(1, 32, "gpio1"),
2880 PIN_BANK(2, 32, "gpio2"),
2881 PIN_BANK(3, 32, "gpio3"),
2882 PIN_BANK(4, 32, "gpio4"),
2883 PIN_BANK(6, 16, "gpio6"),
2884 };
2885
2886 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2887 .pin_banks = rk3066a_pin_banks,
2888 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
2889 .label = "RK3066a-GPIO",
2890 .type = RK2928,
2891 .grf_mux_offset = 0xa8,
2892 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2893 };
2894
2895 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2896 PIN_BANK(0, 32, "gpio0"),
2897 PIN_BANK(1, 32, "gpio1"),
2898 PIN_BANK(2, 32, "gpio2"),
2899 PIN_BANK(3, 32, "gpio3"),
2900 };
2901
2902 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2903 .pin_banks = rk3066b_pin_banks,
2904 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
2905 .label = "RK3066b-GPIO",
2906 .type = RK3066B,
2907 .grf_mux_offset = 0x60,
2908 };
2909
2910 static struct rockchip_pin_bank rk3128_pin_banks[] = {
2911 PIN_BANK(0, 32, "gpio0"),
2912 PIN_BANK(1, 32, "gpio1"),
2913 PIN_BANK(2, 32, "gpio2"),
2914 PIN_BANK(3, 32, "gpio3"),
2915 };
2916
2917 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
2918 .pin_banks = rk3128_pin_banks,
2919 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
2920 .label = "RK3128-GPIO",
2921 .type = RK3128,
2922 .grf_mux_offset = 0xa8,
2923 .iomux_recalced = rk3128_mux_recalced_data,
2924 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
2925 .iomux_routes = rk3128_mux_route_data,
2926 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
2927 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
2928 };
2929
2930 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2931 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2932 PIN_BANK(1, 32, "gpio1"),
2933 PIN_BANK(2, 32, "gpio2"),
2934 PIN_BANK(3, 32, "gpio3"),
2935 };
2936
2937 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2938 .pin_banks = rk3188_pin_banks,
2939 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
2940 .label = "RK3188-GPIO",
2941 .type = RK3188,
2942 .grf_mux_offset = 0x60,
2943 .iomux_routes = rk3188_mux_route_data,
2944 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
2945 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
2946 };
2947
2948 static struct rockchip_pin_bank rk3228_pin_banks[] = {
2949 PIN_BANK(0, 32, "gpio0"),
2950 PIN_BANK(1, 32, "gpio1"),
2951 PIN_BANK(2, 32, "gpio2"),
2952 PIN_BANK(3, 32, "gpio3"),
2953 };
2954
2955 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2956 .pin_banks = rk3228_pin_banks,
2957 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
2958 .label = "RK3228-GPIO",
2959 .type = RK3288,
2960 .grf_mux_offset = 0x0,
2961 .iomux_routes = rk3228_mux_route_data,
2962 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
2963 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
2964 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
2965 };
2966
2967 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2968 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2969 IOMUX_SOURCE_PMU,
2970 IOMUX_SOURCE_PMU,
2971 IOMUX_UNROUTED
2972 ),
2973 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2974 IOMUX_UNROUTED,
2975 IOMUX_UNROUTED,
2976 0
2977 ),
2978 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2979 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2980 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2981 IOMUX_WIDTH_4BIT,
2982 0,
2983 0
2984 ),
2985 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2986 0,
2987 0,
2988 IOMUX_UNROUTED
2989 ),
2990 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2991 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2992 0,
2993 IOMUX_WIDTH_4BIT,
2994 IOMUX_UNROUTED
2995 ),
2996 PIN_BANK(8, 16, "gpio8"),
2997 };
2998
2999 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3000 .pin_banks = rk3288_pin_banks,
3001 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3002 .label = "RK3288-GPIO",
3003 .type = RK3288,
3004 .grf_mux_offset = 0x0,
3005 .pmu_mux_offset = 0x84,
3006 .iomux_routes = rk3288_mux_route_data,
3007 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
3008 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
3009 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
3010 };
3011
3012 static struct rockchip_pin_bank rk3308_pin_banks[] = {
3013 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
3014 IOMUX_WIDTH_2BIT,
3015 IOMUX_WIDTH_2BIT,
3016 IOMUX_WIDTH_2BIT),
3017 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
3018 IOMUX_WIDTH_2BIT,
3019 IOMUX_WIDTH_2BIT,
3020 IOMUX_WIDTH_2BIT),
3021 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
3022 IOMUX_WIDTH_2BIT,
3023 IOMUX_WIDTH_2BIT,
3024 IOMUX_WIDTH_2BIT),
3025 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
3026 IOMUX_WIDTH_2BIT,
3027 IOMUX_WIDTH_2BIT,
3028 IOMUX_WIDTH_2BIT),
3029 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
3030 IOMUX_WIDTH_2BIT,
3031 IOMUX_WIDTH_2BIT,
3032 IOMUX_WIDTH_2BIT),
3033 };
3034
3035 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
3036 .pin_banks = rk3308_pin_banks,
3037 .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
3038 .label = "RK3308-GPIO",
3039 .type = RK3308,
3040 .grf_mux_offset = 0x0,
3041 .iomux_recalced = rk3308_mux_recalced_data,
3042 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
3043 .iomux_routes = rk3308_mux_route_data,
3044 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
3045 .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
3046 .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
3047 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
3048 };
3049
3050 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3051 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3052 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3053 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3054 IOMUX_WIDTH_3BIT,
3055 IOMUX_WIDTH_3BIT,
3056 0),
3057 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3058 IOMUX_WIDTH_3BIT,
3059 IOMUX_WIDTH_3BIT,
3060 0,
3061 0),
3062 };
3063
3064 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3065 .pin_banks = rk3328_pin_banks,
3066 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
3067 .label = "RK3328-GPIO",
3068 .type = RK3288,
3069 .grf_mux_offset = 0x0,
3070 .iomux_recalced = rk3328_mux_recalced_data,
3071 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
3072 .iomux_routes = rk3328_mux_route_data,
3073 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
3074 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3075 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3076 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
3077 };
3078
3079 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3080 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3081 IOMUX_SOURCE_PMU,
3082 IOMUX_SOURCE_PMU,
3083 IOMUX_SOURCE_PMU
3084 ),
3085 PIN_BANK(1, 32, "gpio1"),
3086 PIN_BANK(2, 32, "gpio2"),
3087 PIN_BANK(3, 32, "gpio3"),
3088 };
3089
3090 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3091 .pin_banks = rk3368_pin_banks,
3092 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
3093 .label = "RK3368-GPIO",
3094 .type = RK3368,
3095 .grf_mux_offset = 0x0,
3096 .pmu_mux_offset = 0x0,
3097 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
3098 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
3099 };
3100
3101 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3102 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3103 IOMUX_SOURCE_PMU,
3104 IOMUX_SOURCE_PMU,
3105 IOMUX_SOURCE_PMU,
3106 IOMUX_SOURCE_PMU,
3107 DRV_TYPE_IO_1V8_ONLY,
3108 DRV_TYPE_IO_1V8_ONLY,
3109 DRV_TYPE_IO_DEFAULT,
3110 DRV_TYPE_IO_DEFAULT,
3111 0x80,
3112 0x88,
3113 -1,
3114 -1,
3115 PULL_TYPE_IO_1V8_ONLY,
3116 PULL_TYPE_IO_1V8_ONLY,
3117 PULL_TYPE_IO_DEFAULT,
3118 PULL_TYPE_IO_DEFAULT
3119 ),
3120 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3121 IOMUX_SOURCE_PMU,
3122 IOMUX_SOURCE_PMU,
3123 IOMUX_SOURCE_PMU,
3124 DRV_TYPE_IO_1V8_OR_3V0,
3125 DRV_TYPE_IO_1V8_OR_3V0,
3126 DRV_TYPE_IO_1V8_OR_3V0,
3127 DRV_TYPE_IO_1V8_OR_3V0,
3128 0xa0,
3129 0xa8,
3130 0xb0,
3131 0xb8
3132 ),
3133 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3134 DRV_TYPE_IO_1V8_OR_3V0,
3135 DRV_TYPE_IO_1V8_ONLY,
3136 DRV_TYPE_IO_1V8_ONLY,
3137 PULL_TYPE_IO_DEFAULT,
3138 PULL_TYPE_IO_DEFAULT,
3139 PULL_TYPE_IO_1V8_ONLY,
3140 PULL_TYPE_IO_1V8_ONLY
3141 ),
3142 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3143 DRV_TYPE_IO_3V3_ONLY,
3144 DRV_TYPE_IO_3V3_ONLY,
3145 DRV_TYPE_IO_1V8_OR_3V0
3146 ),
3147 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3148 DRV_TYPE_IO_1V8_3V0_AUTO,
3149 DRV_TYPE_IO_1V8_OR_3V0,
3150 DRV_TYPE_IO_1V8_OR_3V0
3151 ),
3152 };
3153
3154 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3155 .pin_banks = rk3399_pin_banks,
3156 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
3157 .label = "RK3399-GPIO",
3158 .type = RK3399,
3159 .grf_mux_offset = 0xe000,
3160 .pmu_mux_offset = 0x0,
3161 .grf_drv_offset = 0xe100,
3162 .pmu_drv_offset = 0x80,
3163 .iomux_routes = rk3399_mux_route_data,
3164 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
3165 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
3166 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
3167 };
3168
3169 static struct rockchip_pin_bank rk3568_pin_banks[] = {
3170 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3171 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3172 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3173 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
3174 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3175 IOMUX_WIDTH_4BIT,
3176 IOMUX_WIDTH_4BIT,
3177 IOMUX_WIDTH_4BIT),
3178 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3179 IOMUX_WIDTH_4BIT,
3180 IOMUX_WIDTH_4BIT,
3181 IOMUX_WIDTH_4BIT),
3182 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3183 IOMUX_WIDTH_4BIT,
3184 IOMUX_WIDTH_4BIT,
3185 IOMUX_WIDTH_4BIT),
3186 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3187 IOMUX_WIDTH_4BIT,
3188 IOMUX_WIDTH_4BIT,
3189 IOMUX_WIDTH_4BIT),
3190 };
3191
3192 static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
3193 .pin_banks = rk3568_pin_banks,
3194 .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
3195 .label = "RK3568-GPIO",
3196 .type = RK3568,
3197 .grf_mux_offset = 0x0,
3198 .pmu_mux_offset = 0x0,
3199 .grf_drv_offset = 0x0200,
3200 .pmu_drv_offset = 0x0070,
3201 .iomux_routes = rk3568_mux_route_data,
3202 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
3203 .pull_calc_reg = rk3568_calc_pull_reg_and_bit,
3204 .drv_calc_reg = rk3568_calc_drv_reg_and_bit,
3205 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
3206 };
3207
3208 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3209 { .compatible = "rockchip,px30-pinctrl",
3210 .data = &px30_pin_ctrl },
3211 { .compatible = "rockchip,rv1108-pinctrl",
3212 .data = &rv1108_pin_ctrl },
3213 { .compatible = "rockchip,rk2928-pinctrl",
3214 .data = &rk2928_pin_ctrl },
3215 { .compatible = "rockchip,rk3036-pinctrl",
3216 .data = &rk3036_pin_ctrl },
3217 { .compatible = "rockchip,rk3066a-pinctrl",
3218 .data = &rk3066a_pin_ctrl },
3219 { .compatible = "rockchip,rk3066b-pinctrl",
3220 .data = &rk3066b_pin_ctrl },
3221 { .compatible = "rockchip,rk3128-pinctrl",
3222 .data = (void *)&rk3128_pin_ctrl },
3223 { .compatible = "rockchip,rk3188-pinctrl",
3224 .data = &rk3188_pin_ctrl },
3225 { .compatible = "rockchip,rk3228-pinctrl",
3226 .data = &rk3228_pin_ctrl },
3227 { .compatible = "rockchip,rk3288-pinctrl",
3228 .data = &rk3288_pin_ctrl },
3229 { .compatible = "rockchip,rk3308-pinctrl",
3230 .data = &rk3308_pin_ctrl },
3231 { .compatible = "rockchip,rk3328-pinctrl",
3232 .data = &rk3328_pin_ctrl },
3233 { .compatible = "rockchip,rk3368-pinctrl",
3234 .data = &rk3368_pin_ctrl },
3235 { .compatible = "rockchip,rk3399-pinctrl",
3236 .data = &rk3399_pin_ctrl },
3237 { .compatible = "rockchip,rk3568-pinctrl",
3238 .data = &rk3568_pin_ctrl },
3239 {},
3240 };
3241
3242 static struct platform_driver rockchip_pinctrl_driver = {
3243 .probe = rockchip_pinctrl_probe,
3244 .remove = rockchip_pinctrl_remove,
3245 .driver = {
3246 .name = "rockchip-pinctrl",
3247 .pm = &rockchip_pinctrl_dev_pm_ops,
3248 .of_match_table = rockchip_pinctrl_dt_match,
3249 },
3250 };
3251
rockchip_pinctrl_drv_register(void)3252 static int __init rockchip_pinctrl_drv_register(void)
3253 {
3254 return platform_driver_register(&rockchip_pinctrl_driver);
3255 }
3256 postcore_initcall(rockchip_pinctrl_drv_register);
3257
rockchip_pinctrl_drv_unregister(void)3258 static void __exit rockchip_pinctrl_drv_unregister(void)
3259 {
3260 platform_driver_unregister(&rockchip_pinctrl_driver);
3261 }
3262 module_exit(rockchip_pinctrl_drv_unregister);
3263
3264 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
3265 MODULE_LICENSE("GPL");
3266 MODULE_ALIAS("platform:pinctrl-rockchip");
3267 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
3268
