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/Linux-v5.10/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #define S_DIV_ROUND_UP(n, d) \ argument
11 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
18 v = (tmax - tmin) * percent; in linear_inter()
21 return max_t(s32, min_result, v - 1); in linear_inter()
33 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
34 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
44 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
45 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
51 const unsigned long bit_rate = clk_req->bitclk_rate; in msm_dsi_dphy_timing_calc()
[all …]
/Linux-v5.10/drivers/scsi/libsas/
Dsas_init.c1 // SPDX-License-Identifier: GPL-2.0-only
32 spin_lock_init(&task->task_state_lock); in sas_alloc_task()
33 task->task_state_flags = SAS_TASK_STATE_PENDING; in sas_alloc_task()
52 task->slow_task = slow; in sas_alloc_slow_task()
53 slow->task = task; in sas_alloc_slow_task()
54 timer_setup(&slow->timer, NULL, 0); in sas_alloc_slow_task()
55 init_completion(&slow->completion); in sas_alloc_slow_task()
64 kfree(task->slow_task); in sas_free_task()
70 /*------------ SAS addr hash -----------*/
80 for (b = (SAS_ADDR_SIZE - 1); b >= 0; b--) { in sas_hash_addr()
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Dsas_expander.c1 // SPDX-License-Identifier: GPL-2.0
29 /* ---------- SMP task management ---------- */
34 struct sas_task *task = slow->task; in smp_task_timedout()
37 spin_lock_irqsave(&task->task_state_lock, flags); in smp_task_timedout()
38 if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) { in smp_task_timedout()
39 task->task_state_flags |= SAS_TASK_STATE_ABORTED; in smp_task_timedout()
40 complete(&task->slow_task->completion); in smp_task_timedout()
42 spin_unlock_irqrestore(&task->task_state_lock, flags); in smp_task_timedout()
47 del_timer(&task->slow_task->timer); in smp_task_done()
48 complete(&task->slow_task->completion); in smp_task_done()
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/Linux-v5.10/drivers/scsi/aic94xx/
Daic94xx_scb.c1 // SPDX-License-Identifier: GPL-2.0-only
19 /* ---------- EMPTY SCB ---------- */
36 static void get_lrate_mode(struct asd_phy *phy, u8 oob_mode) in get_lrate_mode() argument
38 struct sas_phy *sas_phy = phy->sas_phy.phy; in get_lrate_mode()
43 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS; in get_lrate_mode()
44 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS; in get_lrate_mode()
47 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS; in get_lrate_mode()
48 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS; in get_lrate_mode()
51 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS; in get_lrate_mode()
52 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS; in get_lrate_mode()
[all …]
/Linux-v5.10/drivers/nfc/
Dmei_phy.c1 // SPDX-License-Identifier: GPL-2.0
74 16, 1, (skb)->data, (skb)->len, false); \
81 16, 1, (skb)->data, (skb)->len, false); \
87 pr_debug("cmd=%02d status=%d req_id=%d rsvd=%d size=%d\n", \
88 (_hdr)->cmd, (_hdr)->status, (_hdr)->req_id, \
89 (_hdr)->reserved, (_hdr)->data_size); \
92 static int mei_nfc_if_version(struct nfc_mei_phy *phy) in mei_nfc_if_version() argument
109 r = mei_cldev_send(phy->cldev, (u8 *)&cmd, sizeof(struct mei_nfc_cmd)); in mei_nfc_if_version()
121 return -ENOMEM; in mei_nfc_if_version()
123 bytes_recv = mei_cldev_recv(phy->cldev, (u8 *)reply, if_version_length); in mei_nfc_if_version()
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/Linux-v5.10/drivers/net/wireless/broadcom/b43/
Dlo.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 G PHY LO (LocalOscillator) Measuring and Control routines
8 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
10 Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
33 list_for_each_entry(c, &lo->calib_list, list) { in b43_find_lo_calib()
34 if (!b43_compare_bbatt(&c->bbatt, bbatt)) in b43_find_lo_calib()
36 if (!b43_compare_rfatt(&c->rfatt, rfatt)) in b43_find_lo_calib()
44 /* Write the LocalOscillator Control (adjust) value-pair. */
47 struct b43_phy *phy = &dev->phy; in b43_lo_write() local
51 if (unlikely(abs(control->i) > 16 || abs(control->q) > 16)) { in b43_lo_write()
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/Linux-v5.10/drivers/dma/
Dzx_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
22 #include "virt-dma.h"
24 #define DRIVER_NAME "zx-dma"
26 #define DMA_MAX_SIZE (0x10000 - 512)
99 int id; /* Request phy chan id */
103 struct zx_dma_phy *phy; member
120 spinlock_t lock; /* lock for ch and phy */
122 struct zx_dma_phy *phy; member
138 static void zx_dma_terminate_chan(struct zx_dma_phy *phy, struct zx_dma_dev *d) in zx_dma_terminate_chan() argument
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Dk3dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013 - 2015 Linaro Ltd.
8 #include <linux/dma-mapping.h>
23 #include "virt-dma.h"
25 #define DRIVER_NAME "k3-dma"
83 struct k3_dma_phy *phy; member
105 struct k3_dma_phy *phy; member
134 static void k3_dma_pause_dma(struct k3_dma_phy *phy, bool on) in k3_dma_pause_dma() argument
139 val = readl_relaxed(phy->base + CX_CFG); in k3_dma_pause_dma()
141 writel_relaxed(val, phy->base + CX_CFG); in k3_dma_pause_dma()
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Dpxa_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
22 #include <linux/dma/pxa-dma.h>
25 #include "virt-dma.h"
36 #define PXA_DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */
38 #define PXA_DCSR_REQPEND BIT(8) /* Request Pending (read-only) */
39 #define PXA_DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */
64 #define PXA_DCMD_ENDIAN BIT(18) /* Device Endian-ness. */
71 #define PXA_DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
74 #define PDMA_MAX_DESC_BYTES (PXA_DCMD_LENGTH & ~((1 << PDMA_ALIGNMENT) - 1))
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/Linux-v5.10/drivers/phy/freescale/
Dphy-fsl-imx8-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
15 #include <linux/phy/phy.h>
47 ((x) < 32) ? 0xe0 | ((x) - 16) : \
48 ((x) < 64) ? 0xc0 | ((x) - 32) : \
49 ((x) < 128) ? 0x80 | ((x) - 64) : \
50 ((x) - 128))
51 #define CN(x) (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f))
52 #define CO(x) ((CO_BUF) >> (8 - (x)) & 0x03)
54 /* PHY power on is active low */
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/Linux-v5.10/drivers/phy/intel/
Dphy-intel-keembay-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Keem Bay eMMC PHY driver
14 #include <linux/phy/phy.h>
18 /* eMMC/SD/SDIO core/phy configuration registers */
53 static int keembay_emmc_phy_power(struct phy *phy, bool on_off) in keembay_emmc_phy_power() argument
55 struct keembay_emmc_phy *priv = phy_get_drvdata(phy); in keembay_emmc_phy_power()
66 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
69 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in keembay_emmc_phy_power()
73 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK, in keembay_emmc_phy_power()
76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power()
[all …]
Dphy-intel-lgm-emmc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel eMMC PHY driver
14 #include <linux/phy/phy.h>
18 /* eMMC phy register definitions */
51 static int intel_emmc_phy_power(struct phy *phy, bool on_off) in intel_emmc_phy_power() argument
53 struct intel_emmc_phy *priv = phy_get_drvdata(phy); in intel_emmc_phy_power()
64 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
67 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
75 rate = clk_get_rate(priv->emmcclk); in intel_emmc_phy_power()
78 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate); in intel_emmc_phy_power()
[all …]
/Linux-v5.10/drivers/scsi/mpt3sas/
Dmpt3sas_transport.c5 * Copyright (C) 2012-2014 LSI Corporation
6 * Copyright (C) 2013-2014 Avago Technologies
7 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
22 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
41 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
64 * _transport_sas_node_find_by_sas_address - sas node search
67 * Context: Calling function should acquire ioc->sas_node_lock.
76 if (ioc->sas_hba.sas_address == sas_address) in _transport_sas_node_find_by_sas_address()
77 return &ioc->sas_hba; in _transport_sas_node_find_by_sas_address()
84 * _transport_convert_phy_link_rate -
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/Linux-v5.10/drivers/phy/mediatek/
Dphy-mtk-xsphy.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/phy/phy.h>
17 #include <linux/phy/phy.h>
20 /* u2 phy banks */
25 /* u3 phy shared banks */
29 /* u3 phy banks */
92 struct phy *phy; member
94 struct clk *ref_clk; /* reference clock of anolog phy */
119 void __iomem *pbase = inst->port_base; in u2_phy_slew_rate_calibrate()
125 if (inst->eye_src) in u2_phy_slew_rate_calibrate()
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/Linux-v5.10/drivers/net/ethernet/chelsio/cxgb3/
Daq100x.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
65 static int aq100x_reset(struct cphy *phy, int wait) in aq100x_reset() argument
71 int err = t3_phy_reset(phy, MDIO_MMD_VEND1, 3000); in aq100x_reset()
74 CH_WARN(phy->adapter, "PHY%d: reset failed (0x%x).\n", in aq100x_reset()
75 phy->mdio.prtad, err); in aq100x_reset()
80 static int aq100x_intr_enable(struct cphy *phy) in aq100x_intr_enable() argument
82 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AQ_IMASK_PMA, IMASK_PMA); in aq100x_intr_enable()
86 err = t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, IMASK_GLOBAL); in aq100x_intr_enable()
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/Linux-v5.10/drivers/phy/samsung/
Dphy-samsung-ufs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * UFS PHY driver for Samsung SoC
18 #include <linux/phy/phy.h>
22 #include "phy-samsung-ufs.h"
24 #define for_each_phy_lane(phy, i) \ argument
25 for (i = 0; i < (phy)->lane_cnt; i++)
27 for (; (cfg)->id; (cfg)++)
31 static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy, in samsung_ufs_phy_config() argument
39 writel(cfg->val, (phy)->reg_pma + cfg->off_0); in samsung_ufs_phy_config()
42 if (cfg->id == PHY_TRSV_BLK) in samsung_ufs_phy_config()
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/Linux-v5.10/drivers/media/platform/ti-vpe/
Dcal-camerarx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI Camera Access Layer (CAL) - CAMERARX
5 * Copyright (c) 2015-2020 Texas Instruments Inc.
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-subdev.h>
28 /* ------------------------------------------------------------------
30 * ------------------------------------------------------------------
33 static inline u32 camerarx_read(struct cal_camerarx *phy, u32 offset) in camerarx_read() argument
35 return ioread32(phy->base + offset); in camerarx_read()
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/Linux-v5.10/drivers/pci/controller/
Dpcie-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
18 #include <linux/phy/phy.h>
23 #include "pcie-rockchip.h"
27 struct device *dev = rockchip->dev; in rockchip_pcie_parse_dt()
29 struct device_node *node = dev->of_node; in rockchip_pcie_parse_dt()
33 if (rockchip->is_rc) { in rockchip_pcie_parse_dt()
36 "axi-base"); in rockchip_pcie_parse_dt()
37 rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); in rockchip_pcie_parse_dt()
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/Linux-v5.10/arch/powerpc/boot/dts/fsl/
Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_s7_1d>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&rgmii_phy1>;
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/Linux-v5.10/drivers/gpu/drm/hisilicon/kirin/
Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2014-2016 Hisilicon Limited.
88 struct mipi_phy_params phy; member
121 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) in dsi_calc_phy_rate() argument
151 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
152 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
154 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
155 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
156 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
190 phy->pll_fbd_p = 0; in dsi_calc_phy_rate()
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/Linux-v5.10/drivers/net/wireless/mediatek/mt76/mt7615/
Ddebugfs.c1 // SPDX-License-Identifier: ISC
33 mt7615_mac_set_scs(&dev->phy, val); in mt7615_scs_set()
46 *val = dev->phy.scs_en; in mt7615_scs_get()
70 *val = dev->pm.enable; in mt7615_pm_get()
82 dev->pm.idle_timeout = msecs_to_jiffies(val); in mt7615_pm_idle_timeout_set()
92 *val = jiffies_to_msecs(dev->pm.idle_timeout); in mt7615_pm_idle_timeout_get()
137 dev->fw_debug = val; in mt7615_fw_debug_set()
140 mt7615_mcu_fw_log_2_host(dev, dev->fw_debug ? 2 : 0); in mt7615_fw_debug_set()
151 *val = dev->fw_debug; in mt7615_fw_debug_get()
170 return -ENOMEM; in mt7615_reset_test_set()
[all …]
/Linux-v5.10/drivers/phy/qualcomm/
Dphy-qcom-qusb2.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/nvmem-consumer.h>
16 #include <linux/phy/phy.h>
23 #include <dt-bindings/phy/phy-qcom-qusb2.h>
105 * if yes, then offset gives index in the reg-layout
123 /* set of registers with offsets different per-PHY */
240 /* true if PHY has PLL_TEST register to select clk_scheme */
246 /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
287 "vdda-pll", "vdda-phy-dpdm",
292 /* struct override_param - structure holding qusb2 v2 phy overriding param
[all …]
/Linux-v5.10/drivers/usb/phy/
Dphy-gpio-vbus-usb.c1 // SPDX-License-Identifier: GPL-2.0
3 * gpio-vbus.c - simple GPIO VBUS sensing driver for B peripheral devices
25 * with internal transceivers. It can control a D+ pullup GPIO and
33 struct usb_phy phy; member
60 struct regulator *vbus_draw = gpio_vbus->vbus_draw; in set_vbus_draw()
67 enabled = gpio_vbus->vbus_draw_enabled; in set_vbus_draw()
74 gpio_vbus->vbus_draw_enabled = 1; in set_vbus_draw()
81 gpio_vbus->vbus_draw_enabled = 0; in set_vbus_draw()
84 gpio_vbus->mA = mA; in set_vbus_draw()
89 return gpiod_get_value(gpio_vbus->vbus_gpiod); in is_vbus_powered()
[all …]
/Linux-v5.10/drivers/phy/marvell/
Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
9 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
13 #include <linux/arm-smccc.h>
18 #include <linux/phy.h>
19 #include <linux/phy/phy.h>
123 return -EOPNOTSUPP; in mvebu_a3700_comphy_smc()
125 return -EINVAL; in mvebu_a3700_comphy_smc()
135 /* Unused PHY mux value is 0x0 */ in mvebu_a3700_comphy_get_fw_mode()
137 return -EINVAL; in mvebu_a3700_comphy_get_fw_mode()
148 return -EINVAL; in mvebu_a3700_comphy_get_fw_mode()
[all …]
/Linux-v5.10/drivers/scsi/
Dscsi_transport_sas.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2005-2006 Dell Inc.
13 * introduces two additional intermediate objects: The SAS PHY
14 * as represented by struct sas_phy defines an "outgoing" PHY on
15 * a SAS HBA or Expander, and the SAS remote PHY represented by
16 * struct sas_rphy defines an "incoming" PHY on a SAS Expander or
18 * underlying hardware for a PHY and a remote PHY is the exactly
52 #define to_sas_host_attrs(host) ((struct sas_host_attrs *)(host)->shost_data)
101 return -EINVAL; \
150 { SAS_PHY_DISABLED, "Phy disabled" },
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