Lines Matching +full:d +full:- +full:phy

4  * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 	#address-cells = <2>;
42 	#size-cells = <2>;
43 	interrupt-parent = <&mpic>;
58 			phy-handle = <&phy_sgmii_s7_1c>;
59 			phy-connection-type = "sgmii";
63 			phy-handle = <&phy_sgmii_s7_1d>;
64 			phy-connection-type = "sgmii";
68 			phy-handle = <&rgmii_phy1>;
69 			phy-connection-type = "rgmii";
73 			phy-handle = <&rgmii_phy2>;
74 			phy-connection-type = "rgmii";
78 			phy-handle = <&phy_sgmii_s3_1c>;
79 			phy-connection-type = "sgmii";
83 			phy-handle = <&phy_sgmii_s7_1f>;
84 			phy-connection-type = "sgmii";
88 			phy-handle = <&phy_sgmii_s2_1c>;
89 			phy-connection-type = "xgmii";
93 			phy-handle = <&phy_sgmii_s7_1e>;
94 			phy-connection-type = "xgmii";
100 	mdio-mux-emi1 {
101 		compatible = "mdio-mux-mmioreg", "mdio-mux";
102 		mdio-parent-bus = <&mdio0>;
103 		#address-cells = <1>;
104 		#size-cells = <0>;
106 		mux-mask = <0xe0>;
109 			#address-cells = <1>;
110 			#size-cells = <0>;
113 			rgmii_phy1: ethernet-phy@1 {
119 			#address-cells = <1>;
120 			#size-cells = <0>;
123 			rgmii_phy2: ethernet-phy@2 {
129 			#address-cells = <1>;
130 			#size-cells = <0>;
133 			phy_sgmii_s1_1c: ethernet-phy@1c {
137 			phy_sgmii_s1_1d: ethernet-phy@1d {
141 			phy_sgmii_s1_1e: ethernet-phy@1e {
145 			phy_sgmii_s1_1f: ethernet-phy@1f {
151 			#address-cells = <1>;
152 			#size-cells = <0>;
155 			phy_sgmii_s2_1c: ethernet-phy@1c {
159 			phy_sgmii_s2_1d: ethernet-phy@1d {
163 			phy_sgmii_s2_1e: ethernet-phy@1e {
167 			phy_sgmii_s2_1f: ethernet-phy@1f {
173 			#address-cells = <1>;
174 			#size-cells = <0>;
178 			phy_sgmii_s3_1c: ethernet-phy@1c {
182 			phy_sgmii_s3_1d: ethernet-phy@1d {
186 			phy_sgmii_s3_1e: ethernet-phy@1e {
190 			phy_sgmii_s3_1f: ethernet-phy@1f {
196 			#address-cells = <1>;
197 			#size-cells = <0>;
201 			phy_sgmii_s5_1c: ethernet-phy@1c {
205 			phy_sgmii_s5_1d: ethernet-phy@1d {
209 			phy_sgmii_s5_1e: ethernet-phy@1e {
213 			phy_sgmii_s5_1f: ethernet-phy@1f {
219 			#address-cells = <1>;
220 			#size-cells = <0>;
224 			phy_sgmii_s6_1c: ethernet-phy@1c {
228 			phy_sgmii_s6_1d: ethernet-phy@1d {
232 			phy_sgmii_s6_1e: ethernet-phy@1e {
236 			phy_sgmii_s6_1f: ethernet-phy@1f {
242 			#address-cells = <1>;
243 			#size-cells = <0>;
246 			phy_sgmii_s7_1c: ethernet-phy@1c {
250 			phy_sgmii_s7_1d: ethernet-phy@1d {
254 			phy_sgmii_s7_1e: ethernet-phy@1e {
258 			phy_sgmii_s7_1f: ethernet-phy@1f {
265 /include/ "t2081si-post.dtsi"