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/Linux-v5.10/drivers/mfd/
Dtmio_core.c9 #define CNF_CMD 0x04
10 #define CNF_CTL_BASE 0x10
11 #define CNF_INT_PIN 0x3d
12 #define CNF_STOP_CLK_CTL 0x40
13 #define CNF_GCLK_CTL 0x41
14 #define CNF_SD_CLK_MODE 0x42
15 #define CNF_PIN_STATUS 0x44
16 #define CNF_PWR_CTL_1 0x48
17 #define CNF_PWR_CTL_2 0x49
18 #define CNF_PWR_CTL_3 0x4a
[all …]
Dtc6387xb.c30 .start = 0x800,
31 .end = 0x9ff,
35 .start = 0,
36 .end = 0,
53 return 0; in tc6387xb_suspend()
65 tmio_core_mmc_resume(tc6387xb->scr + 0x200, 0, in tc6387xb_resume()
66 tc6387xb_mmc_resources[0].start & 0xfffe); in tc6387xb_resume()
68 return 0; in tc6387xb_resume()
81 tmio_core_mmc_pwr(tc6387xb->scr + 0x200, 0, state); in tc6387xb_mmc_pwr()
88 tmio_core_mmc_clk_div(tc6387xb->scr + 0x200, 0, state); in tc6387xb_mmc_clk_div()
[all …]
Dwm97xx-core.c23 #define WM9705_VENDOR_ID 0x574d4c05
24 #define WM9712_VENDOR_ID 0x574d4c12
25 #define WM9713_VENDOR_ID 0x574d4c13
26 #define WM97xx_VENDOR_ID_MASK 0xffffffff
42 case AC97_GPIO_CFG ... 0x5c: in wm97xx_readable_reg()
44 case 0x74 ... AC97_VENDOR_ID2: in wm97xx_readable_reg()
63 { 0x02, 0x8000 },
64 { 0x04, 0x8000 },
65 { 0x06, 0x8000 },
66 { 0x0a, 0x8000 },
[all …]
Dt7l66xb.c41 .start = 0x800,
42 .end = 0x9ff,
52 #define SCR_REVID 0x08 /* b Revision ID */
53 #define SCR_IMR 0x42 /* b Interrupt Mask */
54 #define SCR_DEV_CTL 0xe0 /* b Device control */
55 #define SCR_ISR 0xe1 /* b Interrupt Status */
56 #define SCR_GPO_OC 0xf0 /* b GPO output control */
57 #define SCR_GPO_OS 0xf1 /* b GPO output enable */
58 #define SCR_GPI_S 0xf2 /* w GPI status */
59 #define SCR_APDC 0xf8 /* b Active pullup down ctrl */
[all …]
/Linux-v5.10/arch/x86/include/uapi/asm/
Dboot.h6 #define NORMAL_VGA 0xffff /* 80x25 mode */
7 #define EXTENDED_VGA 0xfffe /* 80x50 mode */
8 #define ASK_VGA 0xfffd /* ask for it at bootup */
/Linux-v5.10/Documentation/devicetree/bindings/dma/
Ddma-controller.yaml26 reg = <0x48000000 0x1000>;
27 interrupts = <0 12 0x4
28 0 13 0x4
29 0 14 0x4
30 0 15 0x4>;
34 dma-channel-mask = <0xfffe>;
/Linux-v5.10/include/net/
Daf_ieee802154.h18 IEEE802154_ADDR_NONE = 0x0,
19 /* RESERVED = 0x01, */
20 IEEE802154_ADDR_SHORT = 0x2, /* 16-bit address + PANid */
21 IEEE802154_ADDR_LONG = 0x3, /* 64-bit address + PANid */
36 #define IEEE802154_PANID_BROADCAST 0xffff
37 #define IEEE802154_ADDR_BROADCAST 0xffff
38 #define IEEE802154_ADDR_UNDEF 0xfffe
46 #define SOL_IEEE802154 0
48 #define WPAN_WANTACK 0
53 #define WPAN_SECURITY_DEFAULT 0
/Linux-v5.10/include/linux/mtd/
Dnftl.h15 #define BLOCK_NIL 0xffff /* last block of a chain */
16 #define BLOCK_FREE 0xfffe /* free block */
17 #define BLOCK_NOTEXPLORED 0xfffd /* non explored block, only used during mounting */
18 #define BLOCK_RESERVED 0xfffc /* bios block or bad block */
/Linux-v5.10/drivers/gpu/drm/radeon/
Dr600_dma.c61 return (rptr & 0x3fffc) >> 2; in r600_dma_get_rptr()
75 return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2; in r600_dma_get_wptr()
89 WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc); in r600_dma_set_wptr()
118 * Returns 0 for success, error for failure.
127 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0); in r600_dma_resume()
128 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); in r600_dma_resume()
139 WREG32(DMA_RB_RPTR, 0); in r600_dma_resume()
140 WREG32(DMA_RB_WPTR, 0); in r600_dma_resume()
144 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); in r600_dma_resume()
146 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_dma_resume()
[all …]
/Linux-v5.10/drivers/gpu/drm/gma500/
Dpsb_device.c24 return 0; in psb_output_init()
38 #define PSB_BLC_MAX_PWM_REG_FREQ 0xFFFE
39 #define PSB_BLC_MIN_PWM_REG_FREQ 0x2
41 #define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
89 return 0; in psb_backlight_setup()
103 return 0; in psb_set_brightness()
117 memset(&props, 0, sizeof(struct backlight_properties)); in psb_backlight_init()
127 if (ret < 0) { in psb_backlight_init()
140 return 0; in psb_backlight_init()
197 return 0; in psb_save_display_registers()
[all …]
Dmdfld_device.c21 #define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
27 #define BRIGHTNESS_MASK 0xFF
28 #define BLC_POLARITY_NORMAL 0
33 #define MDFLD_BLC_MAX_PWM_REG_FREQ 0xFFFE
34 #define MDFLD_BLC_MIN_PWM_REG_FREQ 0x2
36 #define MDFLD_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
55 u32 adjusted_level = 0; in mdfld_set_brightness()
65 if (mdfld_get_panel_type(dev, 0) == TC35876X) { in mdfld_set_brightness()
66 if (dev_priv->dpi_panel_on[0] || in mdfld_set_brightness()
71 if (dev_priv->dpi_panel_on[0]) in mdfld_set_brightness()
[all …]
/Linux-v5.10/drivers/watchdog/
Dibmasr.c37 #define TOPAZ_ASR_TOGGLE 0x40
38 #define TOPAZ_ASR_DISABLE 0x80
41 #define PEARL_BASE 0xe04
42 #define PEARL_WRITE 0xe06
43 #define PEARL_READ 0xe07
45 #define PEARL_ASR_DISABLE_MASK 0x80 /* bit 7: disable = 1, enable = 0 */
46 #define PEARL_ASR_TOGGLE_MASK 0x40 /* bit 6: 0, then 1, then 0 */
49 #define JASPER_ASR_REG_OFFSET 0x38
51 #define JASPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1, enable = 0 */
52 #define JASPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */
[all …]
/Linux-v5.10/drivers/pwm/
Dpwm-imx27.c8 * - When disabled the output is driven to 0 independent of the configured
25 #define MX3_PWMCR 0x00 /* PWM Control Register */
26 #define MX3_PWMSR 0x04 /* PWM Status Register */
27 #define MX3_PWMSAR 0x0C /* PWM Sample Register */
28 #define MX3_PWMPR 0x10 /* PWM Period Register */
39 #define MX3_PWMCR_POUTC_NORMAL 0
44 #define MX3_PWMCR_CLKSRC_OFF 0
54 #define MX3_PWMCR_REPEAT_1X 0
59 #define MX3_PWMCR_EN BIT(0)
66 #define MX3_PWMSR_FIFOAV GENMASK(2, 0)
[all …]
/Linux-v5.10/drivers/net/wireless/intersil/orinoco/
Dhermes_rid.h7 #define HERMES_RID_CNFPORTTYPE 0xFC00
8 #define HERMES_RID_CNFOWNMACADDR 0xFC01
9 #define HERMES_RID_CNFDESIREDSSID 0xFC02
10 #define HERMES_RID_CNFOWNCHANNEL 0xFC03
11 #define HERMES_RID_CNFOWNSSID 0xFC04
12 #define HERMES_RID_CNFOWNATIMWINDOW 0xFC05
13 #define HERMES_RID_CNFSYSTEMSCALE 0xFC06
14 #define HERMES_RID_CNFMAXDATALEN 0xFC07
15 #define HERMES_RID_CNFWDSADDRESS 0xFC08
16 #define HERMES_RID_CNFPMENABLED 0xFC09
[all …]
/Linux-v5.10/arch/powerpc/platforms/powernv/
Dopal-lpc.c29 if (opal_lpc_chip_id < 0 || port > 0xffff) in opal_lpc_inb()
30 return 0xff; in opal_lpc_inb()
32 return rc ? 0xff : be32_to_cpu(data); in opal_lpc_inb()
40 if (opal_lpc_chip_id < 0 || port > 0xfffe) in __opal_lpc_inw()
41 return 0xffff; in __opal_lpc_inw()
45 return rc ? 0xffff : be32_to_cpu(data); in __opal_lpc_inw()
57 if (opal_lpc_chip_id < 0 || port > 0xfffc) in __opal_lpc_inl()
58 return 0xffffffff; in __opal_lpc_inl()
65 return rc ? 0xffffffff : be32_to_cpu(data); in __opal_lpc_inl()
75 if (opal_lpc_chip_id < 0 || port > 0xffff) in opal_lpc_outb()
[all …]
/Linux-v5.10/drivers/net/wireless/broadcom/b43/
Dtables.c21 0xFEB93FFD, 0xFEC63FFD, /* 0 */
22 0xFED23FFD, 0xFEDF3FFD,
23 0xFEEC3FFE, 0xFEF83FFE,
24 0xFF053FFE, 0xFF113FFE,
25 0xFF1E3FFE, 0xFF2A3FFF, /* 8 */
26 0xFF373FFF, 0xFF443FFF,
27 0xFF503FFF, 0xFF5D3FFF,
28 0xFF693FFF, 0xFF763FFF,
29 0xFF824000, 0xFF8F4000, /* 16 */
30 0xFF9B4000, 0xFFA84000,
[all …]
/Linux-v5.10/drivers/phy/lantiq/
Dphy-lantiq-vrx200-pcie.c29 #define PCIE_PHY_PLL_CTRL1 0x44
31 #define PCIE_PHY_PLL_CTRL2 0x46
32 #define PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK GENMASK(7, 0)
36 #define PCIE_PHY_PLL_CTRL3 0x48
40 #define PCIE_PHY_PLL_CTRL4 0x4a
41 #define PCIE_PHY_PLL_CTRL5 0x4c
42 #define PCIE_PHY_PLL_CTRL6 0x4e
43 #define PCIE_PHY_PLL_CTRL7 0x50
44 #define PCIE_PHY_PLL_A_CTRL1 0x52
46 #define PCIE_PHY_PLL_A_CTRL2 0x54
[all …]
/Linux-v5.10/drivers/pnp/pnpbios/
Dpnpbios.h17 #define PNP_SUCCESS 0x00
18 #define PNP_NOT_SET_STATICALLY 0x7f
19 #define PNP_UNKNOWN_FUNCTION 0x81
20 #define PNP_FUNCTION_NOT_SUPPORTED 0x82
21 #define PNP_INVALID_HANDLE 0x83
22 #define PNP_BAD_PARAMETER 0x84
23 #define PNP_SET_FAILED 0x85
24 #define PNP_EVENTS_NOT_PENDING 0x86
25 #define PNP_SYSTEM_NOT_DOCKED 0x87
26 #define PNP_NO_ISA_PNP_CARDS 0x88
[all …]
/Linux-v5.10/Documentation/admin-guide/
Dsvga.rst37 0..35 - Menu item number (when you have used the menu to view the list of
39 to use). 0..9 correspond to "0".."9", 10..35 to "a".."z". Warning: the
44 0x.... - Hexadecimal video mode ID (also displayed on the menu, see below
61 0 0F00 80x25
62 1 0F01 80x50
63 2 0F02 80x43
64 3 0F03 80x26
74 "0 0F00 80x25" means that the first menu item (the menu items are numbered
75 from "0" to "9" and from "a" to "z") is a 80x25 mode with ID=0x0f00 (see the
112 expressed in a hexadecimal notation (starting with "0x"). You can set a mode
[all …]
/Linux-v5.10/drivers/clocksource/
Dtimer-meson6.c26 #define MESON_ISA_TIMER_MUX 0x00
36 #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_SYSTEM_CLOCK 0x0
37 #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US 0x1
38 #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_10US 0x2
39 #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_100US 0x3
40 #define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1MS 0x4
44 #define MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK GENMASK(1, 0)
45 #define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US 0x0
46 #define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_10US 0x1
47 #define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_100US 0x0
[all …]
Dtimer-cs5535.c70 cs5535_mfgpt_write(timer, MFGPT_REG_COUNTER, 0); in start_timer()
79 return 0; in mfgpt_shutdown()
86 return 0; in mfgpt_set_periodic()
92 return 0; in mfgpt_next_event()
122 cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_COUNTER, 0); in mfgpt_tick()
172 0xF, 0xFFFE); in cs5535_mfgpt_init()
174 return 0; in cs5535_mfgpt_init()
/Linux-v5.10/include/linux/mlx5/
Dvport.h60 MLX5_VPORT_PF = 0x0,
61 MLX5_VPORT_FIRST_VF = 0x1,
62 MLX5_VPORT_ECPF = 0xfffe,
63 MLX5_VPORT_UPLINK = 0xffff
/Linux-v5.10/include/rdma/
Diba.h123 IBA_FIELD_BLOC(field_struct, byte_offset, 0, num_bits)
126 field_struct, (byte_offset)&0xFFFE, \
132 field_struct, (byte_offset)&0xFFFC, \
138 field_struct, byte_offset, GENMASK_ULL(63, 0), 64
/Linux-v5.10/drivers/net/wireless/broadcom/b43legacy/
Dilt.c23 0xFEB93FFD, 0xFEC63FFD, /* 0 */
24 0xFED23FFD, 0xFEDF3FFD,
25 0xFEEC3FFE, 0xFEF83FFE,
26 0xFF053FFE, 0xFF113FFE,
27 0xFF1E3FFE, 0xFF2A3FFF, /* 8 */
28 0xFF373FFF, 0xFF443FFF,
29 0xFF503FFF, 0xFF5D3FFF,
30 0xFF693FFF, 0xFF763FFF,
31 0xFF824000, 0xFF8F4000, /* 16 */
32 0xFF9B4000, 0xFFA84000,
[all …]
/Linux-v5.10/drivers/hwmon/
Djc42.c25 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
28 #define JC42_REG_CAP 0x00
29 #define JC42_REG_CONFIG 0x01
30 #define JC42_REG_TEMP_UPPER 0x02
31 #define JC42_REG_TEMP_LOWER 0x03
32 #define JC42_REG_TEMP_CRITICAL 0x04
33 #define JC42_REG_TEMP 0x05
34 #define JC42_REG_MANID 0x06
35 #define JC42_REG_DEVICEID 0x07
36 #define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */
[all …]

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