Lines Matching +full:0 +full:xfffe
8 * - When disabled the output is driven to 0 independent of the configured
25 #define MX3_PWMCR 0x00 /* PWM Control Register */
26 #define MX3_PWMSR 0x04 /* PWM Status Register */
27 #define MX3_PWMSAR 0x0C /* PWM Sample Register */
28 #define MX3_PWMPR 0x10 /* PWM Period Register */
39 #define MX3_PWMCR_POUTC_NORMAL 0
44 #define MX3_PWMCR_CLKSRC_OFF 0
54 #define MX3_PWMCR_REPEAT_1X 0
59 #define MX3_PWMCR_EN BIT(0)
66 #define MX3_PWMSR_FIFOAV GENMASK(2, 0)
67 #define MX3_PWMSR_FIFOAV_EMPTY 0
79 /* PWMPR register value of 0xffff has the same effect as 0xfffe */
80 #define MX3_PWMPR_MAX 0xfffe
112 return 0; in pwm_imx27_clk_prepare_enable()
130 if (ret < 0) in pwm_imx27_get_state()
179 int wait_count = 0; in pwm_imx27_sw_reset()
234 prescale = period_cycles / 0x10000 + 1; in pwm_imx27_apply()
248 period_cycles = 0; in pwm_imx27_apply()
290 return 0; in pwm_imx27_apply()
348 imx->mmio_base = devm_platform_ioremap_resource(pdev, 0); in pwm_imx27_probe()