25 	0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
28 #define JC42_REG_CAP		0x00
29 #define JC42_REG_CONFIG		0x01
30 #define JC42_REG_TEMP_UPPER	0x02
31 #define JC42_REG_TEMP_LOWER	0x03
32 #define JC42_REG_TEMP_CRITICAL	0x04
33 #define JC42_REG_TEMP		0x05
34 #define JC42_REG_MANID		0x06
35 #define JC42_REG_DEVICEID	0x07
36 #define JC42_REG_SMBUS		0x22 /* NXP and Atmel, possibly others? */
49 #define JC42_CFG_HYST_MASK	(0x03 << 9)
55 #define ADT_MANID		0x11d4  /* Analog Devices */
56 #define ATMEL_MANID		0x001f  /* Atmel */
57 #define ATMEL_MANID2		0x1114	/* Atmel */
58 #define MAX_MANID		0x004d  /* Maxim */
59 #define IDT_MANID		0x00b3  /* IDT */
60 #define MCP_MANID		0x0054  /* Microchip */
61 #define NXP_MANID		0x1131  /* NXP Semiconductors */
62 #define ONS_MANID		0x1b09  /* ON Semiconductor */
63 #define STM_MANID		0x104a  /* ST Microelectronics */
64 #define GT_MANID		0x1c68	/* Giantec */
65 #define GT_MANID2		0x132d	/* Giantec, 2nd mfg ID */
73 #define ADT7408_DEVID		0x0801
74 #define ADT7408_DEVID_MASK	0xffff
77 #define AT30TS00_DEVID		0x8201
78 #define AT30TS00_DEVID_MASK	0xffff
80 #define AT30TSE004_DEVID	0x2200
81 #define AT30TSE004_DEVID_MASK	0xffff
84 #define GT30TS00_DEVID		0x2200
85 #define GT30TS00_DEVID_MASK	0xff00
87 #define GT34TS02_DEVID		0x3300
88 #define GT34TS02_DEVID_MASK	0xff00
91 #define TSE2004_DEVID		0x2200
92 #define TSE2004_DEVID_MASK	0xff00
94 #define TS3000_DEVID		0x2900  /* Also matches TSE2002 */
95 #define TS3000_DEVID_MASK	0xff00
97 #define TS3001_DEVID		0x3000
98 #define TS3001_DEVID_MASK	0xff00
101 #define MAX6604_DEVID		0x3e00
102 #define MAX6604_DEVID_MASK	0xffff
105 #define MCP9804_DEVID		0x0200
106 #define MCP9804_DEVID_MASK	0xfffc
108 #define MCP9808_DEVID		0x0400
109 #define MCP9808_DEVID_MASK	0xfffc
111 #define MCP98242_DEVID		0x2000
112 #define MCP98242_DEVID_MASK	0xfffc
114 #define MCP98243_DEVID		0x2100
115 #define MCP98243_DEVID_MASK	0xfffc
117 #define MCP98244_DEVID		0x2200
118 #define MCP98244_DEVID_MASK	0xfffc
120 #define MCP9843_DEVID		0x0000	/* Also matches mcp9805 */
121 #define MCP9843_DEVID_MASK	0xfffe
124 #define SE97_DEVID		0xa200
125 #define SE97_DEVID_MASK		0xfffc
127 #define SE98_DEVID		0xa100
128 #define SE98_DEVID_MASK		0xfffc
131 #define CAT6095_DEVID		0x0800	/* Also matches CAT34TS02 */
132 #define CAT6095_DEVID_MASK	0xffe0
134 #define CAT34TS02C_DEVID	0x0a00
135 #define CAT34TS02C_DEVID_MASK	0xfff0
137 #define CAT34TS04_DEVID		0x2200
138 #define CAT34TS04_DEVID_MASK	0xfff0
141 #define STTS424_DEVID		0x0101
142 #define STTS424_DEVID_MASK	0xffff
144 #define STTS424E_DEVID		0x0000
145 #define STTS424E_DEVID_MASK	0xfffe
147 #define STTS2002_DEVID		0x0300
148 #define STTS2002_DEVID_MASK	0xffff
150 #define STTS2004_DEVID		0x2201
151 #define STTS2004_DEVID_MASK	0xffff
153 #define STTS3000_DEVID		0x0200
154 #define STTS3000_DEVID_MASK	0xffff
156 static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
193 	t_input = 0,
220 #define JC42_TEMP_MIN		0
230 	return (ntemp * 2 / 125) & 0x1fff;  in jc42_temp_to_reg()
251 		for (i = 0; i < t_num_temp; i++) {  in jc42_update_device()
253 			if (val < 0) {  in jc42_update_device()
279 		return 0;  in jc42_read()
282 		return 0;  in jc42_read()
285 		return 0;  in jc42_read()
288 		return 0;  in jc42_read()
294 		return 0;  in jc42_read()
300 		return 0;  in jc42_read()
303 		return 0;  in jc42_read()
306 		return 0;  in jc42_read()
309 		return 0;  in jc42_read()
350 		hyst = 0;  in jc42_write()
351 		if (diff > 0) {  in jc42_write()
403 		mode = 0;  in jc42_is_visible()
409 /* Return 0 if detection is successful, -ENODEV otherwise */
424 	if (cap < 0 || config < 0 || manid < 0 || devid < 0)  in jc42_detect()
427 	if ((cap & 0xff00) || (config & 0xf800))  in jc42_detect()
430 	for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {  in jc42_detect()
435 			return 0;  in jc42_detect()
477 	if (cap < 0)  in jc42_probe()
492 		if (smbus < 0)  in jc42_probe()
499 	if (config < 0)  in jc42_probe()
528 	return 0;  in jc42_remove()
540 	return 0;  in jc42_suspend()
550 	return 0;  in jc42_resume()
564 	{ "jc42", 0 },